blob: cd308729860c145327529583b2a42e411bc6f686 [file] [log] [blame]
Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers2c8f6532011-09-02 17:16:34 -070017#include "assembler_x86.h"
18
Elliott Hughes1aa246d2012-12-13 09:29:36 -080019#include "base/casts.h"
Ian Rogers166db042013-07-26 12:05:57 -070020#include "entrypoints/quick/quick_entrypoints.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070021#include "memory_region.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070022#include "thread.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070023
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070024namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070025namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070026
Ian Rogersb033c752011-07-20 12:22:35 -070027std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
28 return os << "XMM" << static_cast<int>(reg);
29}
30
31std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
32 return os << "ST" << static_cast<int>(reg);
33}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070034
Ian Rogers2c8f6532011-09-02 17:16:34 -070035void X86Assembler::call(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070036 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
37 EmitUint8(0xFF);
38 EmitRegisterOperand(2, reg);
39}
40
41
Ian Rogers2c8f6532011-09-02 17:16:34 -070042void X86Assembler::call(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070043 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
44 EmitUint8(0xFF);
45 EmitOperand(2, address);
46}
47
48
Ian Rogers2c8f6532011-09-02 17:16:34 -070049void X86Assembler::call(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070050 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
51 EmitUint8(0xE8);
52 static const int kSize = 5;
Nicolas Geoffray1cf95282014-12-12 19:22:03 +000053 // Offset by one because we already have emitted the opcode.
54 EmitLabel(label, kSize - 1);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070055}
56
57
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +000058void X86Assembler::call(const ExternalLabel& label) {
59 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
60 intptr_t call_start = buffer_.GetPosition();
61 EmitUint8(0xE8);
62 EmitInt32(label.address());
63 static const intptr_t kCallExternalLabelSize = 5;
64 DCHECK_EQ((buffer_.GetPosition() - call_start), kCallExternalLabelSize);
65}
66
67
Ian Rogers2c8f6532011-09-02 17:16:34 -070068void X86Assembler::pushl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070069 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
70 EmitUint8(0x50 + reg);
71}
72
73
Ian Rogers2c8f6532011-09-02 17:16:34 -070074void X86Assembler::pushl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070075 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
76 EmitUint8(0xFF);
77 EmitOperand(6, address);
78}
79
80
Ian Rogers2c8f6532011-09-02 17:16:34 -070081void X86Assembler::pushl(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070082 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Ian Rogers44fb0d02012-03-23 16:46:24 -070083 if (imm.is_int8()) {
84 EmitUint8(0x6A);
85 EmitUint8(imm.value() & 0xFF);
86 } else {
87 EmitUint8(0x68);
88 EmitImmediate(imm);
89 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070090}
91
92
Ian Rogers2c8f6532011-09-02 17:16:34 -070093void X86Assembler::popl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070094 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
95 EmitUint8(0x58 + reg);
96}
97
98
Ian Rogers2c8f6532011-09-02 17:16:34 -070099void X86Assembler::popl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700100 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
101 EmitUint8(0x8F);
102 EmitOperand(0, address);
103}
104
105
Ian Rogers2c8f6532011-09-02 17:16:34 -0700106void X86Assembler::movl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700107 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
108 EmitUint8(0xB8 + dst);
109 EmitImmediate(imm);
110}
111
112
Ian Rogers2c8f6532011-09-02 17:16:34 -0700113void X86Assembler::movl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700114 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
115 EmitUint8(0x89);
116 EmitRegisterOperand(src, dst);
117}
118
119
Ian Rogers2c8f6532011-09-02 17:16:34 -0700120void X86Assembler::movl(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700121 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
122 EmitUint8(0x8B);
123 EmitOperand(dst, src);
124}
125
126
Ian Rogers2c8f6532011-09-02 17:16:34 -0700127void X86Assembler::movl(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700128 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
129 EmitUint8(0x89);
130 EmitOperand(src, dst);
131}
132
133
Ian Rogers2c8f6532011-09-02 17:16:34 -0700134void X86Assembler::movl(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700135 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
136 EmitUint8(0xC7);
137 EmitOperand(0, dst);
138 EmitImmediate(imm);
139}
140
Ian Rogersbdb03912011-09-14 00:55:44 -0700141void X86Assembler::movl(const Address& dst, Label* lbl) {
142 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
143 EmitUint8(0xC7);
144 EmitOperand(0, dst);
145 EmitLabel(lbl, dst.length_ + 5);
146}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700147
Mark Mendell7a08fb52015-07-15 14:09:35 -0400148void X86Assembler::movntl(const Address& dst, Register src) {
149 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
150 EmitUint8(0x0F);
151 EmitUint8(0xC3);
152 EmitOperand(src, dst);
153}
154
Mark Mendell09ed1a32015-03-25 08:30:06 -0400155void X86Assembler::bswapl(Register dst) {
156 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
157 EmitUint8(0x0F);
158 EmitUint8(0xC8 + dst);
159}
160
Mark Mendellbcee0922015-09-15 21:45:01 -0400161void X86Assembler::bsfl(Register dst, Register src) {
162 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
163 EmitUint8(0x0F);
164 EmitUint8(0xBC);
165 EmitRegisterOperand(dst, src);
166}
167
168void X86Assembler::bsfl(Register dst, const Address& src) {
169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
170 EmitUint8(0x0F);
171 EmitUint8(0xBC);
172 EmitOperand(dst, src);
173}
174
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400175void X86Assembler::bsrl(Register dst, Register src) {
176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
177 EmitUint8(0x0F);
178 EmitUint8(0xBD);
179 EmitRegisterOperand(dst, src);
180}
181
182void X86Assembler::bsrl(Register dst, const Address& src) {
183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
184 EmitUint8(0x0F);
185 EmitUint8(0xBD);
186 EmitOperand(dst, src);
187}
188
Aart Bikc39dac12016-01-21 08:59:48 -0800189void X86Assembler::popcntl(Register dst, Register src) {
190 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
191 EmitUint8(0xF3);
192 EmitUint8(0x0F);
193 EmitUint8(0xB8);
194 EmitRegisterOperand(dst, src);
195}
196
197void X86Assembler::popcntl(Register dst, const Address& src) {
198 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
199 EmitUint8(0xF3);
200 EmitUint8(0x0F);
201 EmitUint8(0xB8);
202 EmitOperand(dst, src);
203}
204
Ian Rogers2c8f6532011-09-02 17:16:34 -0700205void X86Assembler::movzxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700206 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
207 EmitUint8(0x0F);
208 EmitUint8(0xB6);
209 EmitRegisterOperand(dst, src);
210}
211
212
Ian Rogers2c8f6532011-09-02 17:16:34 -0700213void X86Assembler::movzxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700214 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
215 EmitUint8(0x0F);
216 EmitUint8(0xB6);
217 EmitOperand(dst, src);
218}
219
220
Ian Rogers2c8f6532011-09-02 17:16:34 -0700221void X86Assembler::movsxb(Register dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700222 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
223 EmitUint8(0x0F);
224 EmitUint8(0xBE);
225 EmitRegisterOperand(dst, src);
226}
227
228
Ian Rogers2c8f6532011-09-02 17:16:34 -0700229void X86Assembler::movsxb(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700230 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
231 EmitUint8(0x0F);
232 EmitUint8(0xBE);
233 EmitOperand(dst, src);
234}
235
236
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700237void X86Assembler::movb(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700238 LOG(FATAL) << "Use movzxb or movsxb instead.";
239}
240
241
Ian Rogers2c8f6532011-09-02 17:16:34 -0700242void X86Assembler::movb(const Address& dst, ByteRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700243 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
244 EmitUint8(0x88);
245 EmitOperand(src, dst);
246}
247
248
Ian Rogers2c8f6532011-09-02 17:16:34 -0700249void X86Assembler::movb(const Address& dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700250 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
251 EmitUint8(0xC6);
252 EmitOperand(EAX, dst);
253 CHECK(imm.is_int8());
254 EmitUint8(imm.value() & 0xFF);
255}
256
257
Ian Rogers2c8f6532011-09-02 17:16:34 -0700258void X86Assembler::movzxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700259 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
260 EmitUint8(0x0F);
261 EmitUint8(0xB7);
262 EmitRegisterOperand(dst, src);
263}
264
265
Ian Rogers2c8f6532011-09-02 17:16:34 -0700266void X86Assembler::movzxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700267 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
268 EmitUint8(0x0F);
269 EmitUint8(0xB7);
270 EmitOperand(dst, src);
271}
272
273
Ian Rogers2c8f6532011-09-02 17:16:34 -0700274void X86Assembler::movsxw(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700275 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
276 EmitUint8(0x0F);
277 EmitUint8(0xBF);
278 EmitRegisterOperand(dst, src);
279}
280
281
Ian Rogers2c8f6532011-09-02 17:16:34 -0700282void X86Assembler::movsxw(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700283 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
284 EmitUint8(0x0F);
285 EmitUint8(0xBF);
286 EmitOperand(dst, src);
287}
288
289
Elliott Hughes1bac54f2012-03-16 12:48:31 -0700290void X86Assembler::movw(Register /*dst*/, const Address& /*src*/) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700291 LOG(FATAL) << "Use movzxw or movsxw instead.";
292}
293
294
Ian Rogers2c8f6532011-09-02 17:16:34 -0700295void X86Assembler::movw(const Address& dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700296 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
297 EmitOperandSizeOverride();
298 EmitUint8(0x89);
299 EmitOperand(src, dst);
300}
301
302
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100303void X86Assembler::movw(const Address& dst, const Immediate& imm) {
304 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
305 EmitOperandSizeOverride();
306 EmitUint8(0xC7);
307 EmitOperand(0, dst);
Nicolas Geoffrayb6e72062014-10-07 14:54:48 +0100308 CHECK(imm.is_uint16() || imm.is_int16());
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100309 EmitUint8(imm.value() & 0xFF);
310 EmitUint8(imm.value() >> 8);
311}
312
313
Ian Rogers2c8f6532011-09-02 17:16:34 -0700314void X86Assembler::leal(Register dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700315 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
316 EmitUint8(0x8D);
317 EmitOperand(dst, src);
318}
319
320
Ian Rogers2c8f6532011-09-02 17:16:34 -0700321void X86Assembler::cmovl(Condition condition, Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700322 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
323 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700324 EmitUint8(0x40 + condition);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700325 EmitRegisterOperand(dst, src);
326}
327
328
Mark Mendellabdac472016-02-12 13:49:03 -0500329void X86Assembler::cmovl(Condition condition, Register dst, const Address& src) {
330 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
331 EmitUint8(0x0F);
332 EmitUint8(0x40 + condition);
333 EmitOperand(dst, src);
334}
335
336
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000337void X86Assembler::setb(Condition condition, Register dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700338 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
339 EmitUint8(0x0F);
Ian Rogersb033c752011-07-20 12:22:35 -0700340 EmitUint8(0x90 + condition);
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000341 EmitOperand(0, Operand(dst));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700342}
343
344
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100345void X86Assembler::movaps(XmmRegister dst, XmmRegister src) {
346 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
347 EmitUint8(0x0F);
348 EmitUint8(0x28);
349 EmitXmmRegisterOperand(dst, src);
350}
351
352
Ian Rogers2c8f6532011-09-02 17:16:34 -0700353void X86Assembler::movss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700354 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
355 EmitUint8(0xF3);
356 EmitUint8(0x0F);
357 EmitUint8(0x10);
358 EmitOperand(dst, src);
359}
360
361
Ian Rogers2c8f6532011-09-02 17:16:34 -0700362void X86Assembler::movss(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700363 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
364 EmitUint8(0xF3);
365 EmitUint8(0x0F);
366 EmitUint8(0x11);
367 EmitOperand(src, dst);
368}
369
370
Ian Rogers2c8f6532011-09-02 17:16:34 -0700371void X86Assembler::movss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700372 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
373 EmitUint8(0xF3);
374 EmitUint8(0x0F);
375 EmitUint8(0x11);
376 EmitXmmRegisterOperand(src, dst);
377}
378
379
Ian Rogers2c8f6532011-09-02 17:16:34 -0700380void X86Assembler::movd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700381 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
382 EmitUint8(0x66);
383 EmitUint8(0x0F);
384 EmitUint8(0x6E);
385 EmitOperand(dst, Operand(src));
386}
387
388
Ian Rogers2c8f6532011-09-02 17:16:34 -0700389void X86Assembler::movd(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700390 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
391 EmitUint8(0x66);
392 EmitUint8(0x0F);
393 EmitUint8(0x7E);
394 EmitOperand(src, Operand(dst));
395}
396
397
Ian Rogers2c8f6532011-09-02 17:16:34 -0700398void X86Assembler::addss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700399 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
400 EmitUint8(0xF3);
401 EmitUint8(0x0F);
402 EmitUint8(0x58);
403 EmitXmmRegisterOperand(dst, src);
404}
405
406
Ian Rogers2c8f6532011-09-02 17:16:34 -0700407void X86Assembler::addss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700408 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
409 EmitUint8(0xF3);
410 EmitUint8(0x0F);
411 EmitUint8(0x58);
412 EmitOperand(dst, src);
413}
414
415
Ian Rogers2c8f6532011-09-02 17:16:34 -0700416void X86Assembler::subss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700417 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
418 EmitUint8(0xF3);
419 EmitUint8(0x0F);
420 EmitUint8(0x5C);
421 EmitXmmRegisterOperand(dst, src);
422}
423
424
Ian Rogers2c8f6532011-09-02 17:16:34 -0700425void X86Assembler::subss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700426 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
427 EmitUint8(0xF3);
428 EmitUint8(0x0F);
429 EmitUint8(0x5C);
430 EmitOperand(dst, src);
431}
432
433
Ian Rogers2c8f6532011-09-02 17:16:34 -0700434void X86Assembler::mulss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700435 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
436 EmitUint8(0xF3);
437 EmitUint8(0x0F);
438 EmitUint8(0x59);
439 EmitXmmRegisterOperand(dst, src);
440}
441
442
Ian Rogers2c8f6532011-09-02 17:16:34 -0700443void X86Assembler::mulss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700444 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
445 EmitUint8(0xF3);
446 EmitUint8(0x0F);
447 EmitUint8(0x59);
448 EmitOperand(dst, src);
449}
450
451
Ian Rogers2c8f6532011-09-02 17:16:34 -0700452void X86Assembler::divss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700453 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
454 EmitUint8(0xF3);
455 EmitUint8(0x0F);
456 EmitUint8(0x5E);
457 EmitXmmRegisterOperand(dst, src);
458}
459
460
Ian Rogers2c8f6532011-09-02 17:16:34 -0700461void X86Assembler::divss(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700462 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
463 EmitUint8(0xF3);
464 EmitUint8(0x0F);
465 EmitUint8(0x5E);
466 EmitOperand(dst, src);
467}
468
469
Ian Rogers2c8f6532011-09-02 17:16:34 -0700470void X86Assembler::flds(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700471 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
472 EmitUint8(0xD9);
473 EmitOperand(0, src);
474}
475
476
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500477void X86Assembler::fsts(const Address& dst) {
478 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
479 EmitUint8(0xD9);
480 EmitOperand(2, dst);
481}
482
483
Ian Rogers2c8f6532011-09-02 17:16:34 -0700484void X86Assembler::fstps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
486 EmitUint8(0xD9);
487 EmitOperand(3, dst);
488}
489
490
Ian Rogers2c8f6532011-09-02 17:16:34 -0700491void X86Assembler::movsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700492 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
493 EmitUint8(0xF2);
494 EmitUint8(0x0F);
495 EmitUint8(0x10);
496 EmitOperand(dst, src);
497}
498
499
Ian Rogers2c8f6532011-09-02 17:16:34 -0700500void X86Assembler::movsd(const Address& dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700501 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
502 EmitUint8(0xF2);
503 EmitUint8(0x0F);
504 EmitUint8(0x11);
505 EmitOperand(src, dst);
506}
507
508
Ian Rogers2c8f6532011-09-02 17:16:34 -0700509void X86Assembler::movsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700510 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
511 EmitUint8(0xF2);
512 EmitUint8(0x0F);
513 EmitUint8(0x11);
514 EmitXmmRegisterOperand(src, dst);
515}
516
517
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000518void X86Assembler::movhpd(XmmRegister dst, const Address& src) {
519 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
520 EmitUint8(0x66);
521 EmitUint8(0x0F);
522 EmitUint8(0x16);
523 EmitOperand(dst, src);
524}
525
526
527void X86Assembler::movhpd(const Address& dst, XmmRegister src) {
528 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
529 EmitUint8(0x66);
530 EmitUint8(0x0F);
531 EmitUint8(0x17);
532 EmitOperand(src, dst);
533}
534
535
536void X86Assembler::psrldq(XmmRegister reg, const Immediate& shift_count) {
537 DCHECK(shift_count.is_uint8());
538
539 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
540 EmitUint8(0x66);
541 EmitUint8(0x0F);
542 EmitUint8(0x73);
543 EmitXmmRegisterOperand(3, reg);
544 EmitUint8(shift_count.value());
545}
546
547
Calin Juravle52c48962014-12-16 17:02:57 +0000548void X86Assembler::psrlq(XmmRegister reg, const Immediate& shift_count) {
549 DCHECK(shift_count.is_uint8());
550
551 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
552 EmitUint8(0x66);
553 EmitUint8(0x0F);
554 EmitUint8(0x73);
555 EmitXmmRegisterOperand(2, reg);
556 EmitUint8(shift_count.value());
557}
558
559
560void X86Assembler::punpckldq(XmmRegister dst, XmmRegister src) {
561 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
562 EmitUint8(0x66);
563 EmitUint8(0x0F);
564 EmitUint8(0x62);
565 EmitXmmRegisterOperand(dst, src);
566}
567
568
Ian Rogers2c8f6532011-09-02 17:16:34 -0700569void X86Assembler::addsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700570 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
571 EmitUint8(0xF2);
572 EmitUint8(0x0F);
573 EmitUint8(0x58);
574 EmitXmmRegisterOperand(dst, src);
575}
576
577
Ian Rogers2c8f6532011-09-02 17:16:34 -0700578void X86Assembler::addsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700579 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
580 EmitUint8(0xF2);
581 EmitUint8(0x0F);
582 EmitUint8(0x58);
583 EmitOperand(dst, src);
584}
585
586
Ian Rogers2c8f6532011-09-02 17:16:34 -0700587void X86Assembler::subsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700588 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
589 EmitUint8(0xF2);
590 EmitUint8(0x0F);
591 EmitUint8(0x5C);
592 EmitXmmRegisterOperand(dst, src);
593}
594
595
Ian Rogers2c8f6532011-09-02 17:16:34 -0700596void X86Assembler::subsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700597 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
598 EmitUint8(0xF2);
599 EmitUint8(0x0F);
600 EmitUint8(0x5C);
601 EmitOperand(dst, src);
602}
603
604
Ian Rogers2c8f6532011-09-02 17:16:34 -0700605void X86Assembler::mulsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700606 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
607 EmitUint8(0xF2);
608 EmitUint8(0x0F);
609 EmitUint8(0x59);
610 EmitXmmRegisterOperand(dst, src);
611}
612
613
Ian Rogers2c8f6532011-09-02 17:16:34 -0700614void X86Assembler::mulsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700615 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
616 EmitUint8(0xF2);
617 EmitUint8(0x0F);
618 EmitUint8(0x59);
619 EmitOperand(dst, src);
620}
621
622
Ian Rogers2c8f6532011-09-02 17:16:34 -0700623void X86Assembler::divsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700624 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
625 EmitUint8(0xF2);
626 EmitUint8(0x0F);
627 EmitUint8(0x5E);
628 EmitXmmRegisterOperand(dst, src);
629}
630
631
Ian Rogers2c8f6532011-09-02 17:16:34 -0700632void X86Assembler::divsd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700633 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
634 EmitUint8(0xF2);
635 EmitUint8(0x0F);
636 EmitUint8(0x5E);
637 EmitOperand(dst, src);
638}
639
640
Ian Rogers2c8f6532011-09-02 17:16:34 -0700641void X86Assembler::cvtsi2ss(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700642 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
643 EmitUint8(0xF3);
644 EmitUint8(0x0F);
645 EmitUint8(0x2A);
646 EmitOperand(dst, Operand(src));
647}
648
649
Ian Rogers2c8f6532011-09-02 17:16:34 -0700650void X86Assembler::cvtsi2sd(XmmRegister dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700651 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
652 EmitUint8(0xF2);
653 EmitUint8(0x0F);
654 EmitUint8(0x2A);
655 EmitOperand(dst, Operand(src));
656}
657
658
Ian Rogers2c8f6532011-09-02 17:16:34 -0700659void X86Assembler::cvtss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700660 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
661 EmitUint8(0xF3);
662 EmitUint8(0x0F);
663 EmitUint8(0x2D);
664 EmitXmmRegisterOperand(dst, src);
665}
666
667
Ian Rogers2c8f6532011-09-02 17:16:34 -0700668void X86Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700669 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
670 EmitUint8(0xF3);
671 EmitUint8(0x0F);
672 EmitUint8(0x5A);
673 EmitXmmRegisterOperand(dst, src);
674}
675
676
Ian Rogers2c8f6532011-09-02 17:16:34 -0700677void X86Assembler::cvtsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700678 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
679 EmitUint8(0xF2);
680 EmitUint8(0x0F);
681 EmitUint8(0x2D);
682 EmitXmmRegisterOperand(dst, src);
683}
684
685
Ian Rogers2c8f6532011-09-02 17:16:34 -0700686void X86Assembler::cvttss2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700687 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
688 EmitUint8(0xF3);
689 EmitUint8(0x0F);
690 EmitUint8(0x2C);
691 EmitXmmRegisterOperand(dst, src);
692}
693
694
Ian Rogers2c8f6532011-09-02 17:16:34 -0700695void X86Assembler::cvttsd2si(Register dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700696 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
697 EmitUint8(0xF2);
698 EmitUint8(0x0F);
699 EmitUint8(0x2C);
700 EmitXmmRegisterOperand(dst, src);
701}
702
703
Ian Rogers2c8f6532011-09-02 17:16:34 -0700704void X86Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700705 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
706 EmitUint8(0xF2);
707 EmitUint8(0x0F);
708 EmitUint8(0x5A);
709 EmitXmmRegisterOperand(dst, src);
710}
711
712
Ian Rogers2c8f6532011-09-02 17:16:34 -0700713void X86Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700714 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
715 EmitUint8(0xF3);
716 EmitUint8(0x0F);
717 EmitUint8(0xE6);
718 EmitXmmRegisterOperand(dst, src);
719}
720
721
Ian Rogers2c8f6532011-09-02 17:16:34 -0700722void X86Assembler::comiss(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700723 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
724 EmitUint8(0x0F);
725 EmitUint8(0x2F);
726 EmitXmmRegisterOperand(a, b);
727}
728
729
Aart Bik18ba1212016-08-01 14:11:20 -0700730void X86Assembler::comiss(XmmRegister a, const Address& b) {
731 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
732 EmitUint8(0x0F);
733 EmitUint8(0x2F);
734 EmitOperand(a, b);
735}
736
737
Ian Rogers2c8f6532011-09-02 17:16:34 -0700738void X86Assembler::comisd(XmmRegister a, XmmRegister b) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700739 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
740 EmitUint8(0x66);
741 EmitUint8(0x0F);
742 EmitUint8(0x2F);
743 EmitXmmRegisterOperand(a, b);
744}
745
746
Aart Bik18ba1212016-08-01 14:11:20 -0700747void X86Assembler::comisd(XmmRegister a, const Address& b) {
748 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
749 EmitUint8(0x66);
750 EmitUint8(0x0F);
751 EmitUint8(0x2F);
752 EmitOperand(a, b);
753}
754
755
Calin Juravleddb7df22014-11-25 20:56:51 +0000756void X86Assembler::ucomiss(XmmRegister a, XmmRegister b) {
757 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
758 EmitUint8(0x0F);
759 EmitUint8(0x2E);
760 EmitXmmRegisterOperand(a, b);
761}
762
763
Mark Mendell9f51f262015-10-30 09:21:37 -0400764void X86Assembler::ucomiss(XmmRegister a, const Address& b) {
765 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
766 EmitUint8(0x0F);
767 EmitUint8(0x2E);
768 EmitOperand(a, b);
769}
770
771
Calin Juravleddb7df22014-11-25 20:56:51 +0000772void X86Assembler::ucomisd(XmmRegister a, XmmRegister b) {
773 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
774 EmitUint8(0x66);
775 EmitUint8(0x0F);
776 EmitUint8(0x2E);
777 EmitXmmRegisterOperand(a, b);
778}
779
780
Mark Mendell9f51f262015-10-30 09:21:37 -0400781void X86Assembler::ucomisd(XmmRegister a, const Address& b) {
782 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
783 EmitUint8(0x66);
784 EmitUint8(0x0F);
785 EmitUint8(0x2E);
786 EmitOperand(a, b);
787}
788
789
Mark Mendellfb8d2792015-03-31 22:16:59 -0400790void X86Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) {
791 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
792 EmitUint8(0x66);
793 EmitUint8(0x0F);
794 EmitUint8(0x3A);
795 EmitUint8(0x0B);
796 EmitXmmRegisterOperand(dst, src);
797 EmitUint8(imm.value());
798}
799
800
801void X86Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) {
802 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
803 EmitUint8(0x66);
804 EmitUint8(0x0F);
805 EmitUint8(0x3A);
806 EmitUint8(0x0A);
807 EmitXmmRegisterOperand(dst, src);
808 EmitUint8(imm.value());
809}
810
811
Ian Rogers2c8f6532011-09-02 17:16:34 -0700812void X86Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700813 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
814 EmitUint8(0xF2);
815 EmitUint8(0x0F);
816 EmitUint8(0x51);
817 EmitXmmRegisterOperand(dst, src);
818}
819
820
Ian Rogers2c8f6532011-09-02 17:16:34 -0700821void X86Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700822 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
823 EmitUint8(0xF3);
824 EmitUint8(0x0F);
825 EmitUint8(0x51);
826 EmitXmmRegisterOperand(dst, src);
827}
828
829
Ian Rogers2c8f6532011-09-02 17:16:34 -0700830void X86Assembler::xorpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700831 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
832 EmitUint8(0x66);
833 EmitUint8(0x0F);
834 EmitUint8(0x57);
835 EmitOperand(dst, src);
836}
837
838
Ian Rogers2c8f6532011-09-02 17:16:34 -0700839void X86Assembler::xorpd(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700840 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
841 EmitUint8(0x66);
842 EmitUint8(0x0F);
843 EmitUint8(0x57);
844 EmitXmmRegisterOperand(dst, src);
845}
846
847
Mark Mendell09ed1a32015-03-25 08:30:06 -0400848void X86Assembler::andps(XmmRegister dst, XmmRegister src) {
849 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
850 EmitUint8(0x0F);
851 EmitUint8(0x54);
852 EmitXmmRegisterOperand(dst, src);
853}
854
855
856void X86Assembler::andpd(XmmRegister dst, XmmRegister src) {
857 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
858 EmitUint8(0x66);
859 EmitUint8(0x0F);
860 EmitUint8(0x54);
861 EmitXmmRegisterOperand(dst, src);
862}
863
864
865void X86Assembler::orpd(XmmRegister dst, XmmRegister src) {
866 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
867 EmitUint8(0x66);
868 EmitUint8(0x0F);
869 EmitUint8(0x56);
870 EmitXmmRegisterOperand(dst, src);
871}
872
873
Ian Rogers2c8f6532011-09-02 17:16:34 -0700874void X86Assembler::xorps(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700875 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
876 EmitUint8(0x0F);
877 EmitUint8(0x57);
878 EmitOperand(dst, src);
879}
880
881
Mark Mendell09ed1a32015-03-25 08:30:06 -0400882void X86Assembler::orps(XmmRegister dst, XmmRegister src) {
883 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
884 EmitUint8(0x0F);
885 EmitUint8(0x56);
886 EmitXmmRegisterOperand(dst, src);
887}
888
889
Ian Rogers2c8f6532011-09-02 17:16:34 -0700890void X86Assembler::xorps(XmmRegister dst, XmmRegister src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700891 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
892 EmitUint8(0x0F);
893 EmitUint8(0x57);
894 EmitXmmRegisterOperand(dst, src);
895}
896
897
Mark Mendell09ed1a32015-03-25 08:30:06 -0400898void X86Assembler::andps(XmmRegister dst, const Address& src) {
899 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
900 EmitUint8(0x0F);
901 EmitUint8(0x54);
902 EmitOperand(dst, src);
903}
904
905
Ian Rogers2c8f6532011-09-02 17:16:34 -0700906void X86Assembler::andpd(XmmRegister dst, const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700907 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
908 EmitUint8(0x66);
909 EmitUint8(0x0F);
910 EmitUint8(0x54);
911 EmitOperand(dst, src);
912}
913
914
Ian Rogers2c8f6532011-09-02 17:16:34 -0700915void X86Assembler::fldl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700916 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
917 EmitUint8(0xDD);
918 EmitOperand(0, src);
919}
920
921
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500922void X86Assembler::fstl(const Address& dst) {
923 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
924 EmitUint8(0xDD);
925 EmitOperand(2, dst);
926}
927
928
Ian Rogers2c8f6532011-09-02 17:16:34 -0700929void X86Assembler::fstpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700930 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
931 EmitUint8(0xDD);
932 EmitOperand(3, dst);
933}
934
935
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500936void X86Assembler::fstsw() {
937 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
938 EmitUint8(0x9B);
939 EmitUint8(0xDF);
940 EmitUint8(0xE0);
941}
942
943
Ian Rogers2c8f6532011-09-02 17:16:34 -0700944void X86Assembler::fnstcw(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700945 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
946 EmitUint8(0xD9);
947 EmitOperand(7, dst);
948}
949
950
Ian Rogers2c8f6532011-09-02 17:16:34 -0700951void X86Assembler::fldcw(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700952 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
953 EmitUint8(0xD9);
954 EmitOperand(5, src);
955}
956
957
Ian Rogers2c8f6532011-09-02 17:16:34 -0700958void X86Assembler::fistpl(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700959 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
960 EmitUint8(0xDF);
961 EmitOperand(7, dst);
962}
963
964
Ian Rogers2c8f6532011-09-02 17:16:34 -0700965void X86Assembler::fistps(const Address& dst) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700966 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
967 EmitUint8(0xDB);
968 EmitOperand(3, dst);
969}
970
971
Ian Rogers2c8f6532011-09-02 17:16:34 -0700972void X86Assembler::fildl(const Address& src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700973 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
974 EmitUint8(0xDF);
975 EmitOperand(5, src);
976}
977
978
Roland Levillain0a186012015-04-13 17:00:20 +0100979void X86Assembler::filds(const Address& src) {
980 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
981 EmitUint8(0xDB);
982 EmitOperand(0, src);
983}
984
985
Ian Rogers2c8f6532011-09-02 17:16:34 -0700986void X86Assembler::fincstp() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700987 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
988 EmitUint8(0xD9);
989 EmitUint8(0xF7);
990}
991
992
Ian Rogers2c8f6532011-09-02 17:16:34 -0700993void X86Assembler::ffree(const Immediate& index) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700994 CHECK_LT(index.value(), 7);
995 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
996 EmitUint8(0xDD);
997 EmitUint8(0xC0 + index.value());
998}
999
1000
Ian Rogers2c8f6532011-09-02 17:16:34 -07001001void X86Assembler::fsin() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001002 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1003 EmitUint8(0xD9);
1004 EmitUint8(0xFE);
1005}
1006
1007
Ian Rogers2c8f6532011-09-02 17:16:34 -07001008void X86Assembler::fcos() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001009 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1010 EmitUint8(0xD9);
1011 EmitUint8(0xFF);
1012}
1013
1014
Ian Rogers2c8f6532011-09-02 17:16:34 -07001015void X86Assembler::fptan() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001016 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1017 EmitUint8(0xD9);
1018 EmitUint8(0xF2);
1019}
1020
1021
Mark Mendell24f2dfa2015-01-14 19:51:45 -05001022void X86Assembler::fucompp() {
1023 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1024 EmitUint8(0xDA);
1025 EmitUint8(0xE9);
1026}
1027
1028
1029void X86Assembler::fprem() {
1030 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1031 EmitUint8(0xD9);
1032 EmitUint8(0xF8);
1033}
1034
1035
Ian Rogers2c8f6532011-09-02 17:16:34 -07001036void X86Assembler::xchgl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001037 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1038 EmitUint8(0x87);
1039 EmitRegisterOperand(dst, src);
1040}
1041
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001042
Ian Rogers7caad772012-03-30 01:07:54 -07001043void X86Assembler::xchgl(Register reg, const Address& address) {
1044 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1045 EmitUint8(0x87);
1046 EmitOperand(reg, address);
1047}
1048
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001049
Serguei Katkov3b625932016-05-06 10:24:17 +06001050void X86Assembler::cmpb(const Address& address, const Immediate& imm) {
1051 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1052 EmitUint8(0x80);
1053 EmitOperand(7, address);
1054 EmitUint8(imm.value() & 0xFF);
1055}
1056
1057
Nicolas Geoffray3c049742014-09-24 18:10:46 +01001058void X86Assembler::cmpw(const Address& address, const Immediate& imm) {
1059 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1060 EmitUint8(0x66);
1061 EmitComplex(7, address, imm);
1062}
1063
1064
Ian Rogers2c8f6532011-09-02 17:16:34 -07001065void X86Assembler::cmpl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001066 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1067 EmitComplex(7, Operand(reg), imm);
1068}
1069
1070
Ian Rogers2c8f6532011-09-02 17:16:34 -07001071void X86Assembler::cmpl(Register reg0, Register reg1) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001072 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1073 EmitUint8(0x3B);
1074 EmitOperand(reg0, Operand(reg1));
1075}
1076
1077
Ian Rogers2c8f6532011-09-02 17:16:34 -07001078void X86Assembler::cmpl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001079 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1080 EmitUint8(0x3B);
1081 EmitOperand(reg, address);
1082}
1083
1084
Ian Rogers2c8f6532011-09-02 17:16:34 -07001085void X86Assembler::addl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001086 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1087 EmitUint8(0x03);
1088 EmitRegisterOperand(dst, src);
1089}
1090
1091
Ian Rogers2c8f6532011-09-02 17:16:34 -07001092void X86Assembler::addl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001093 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1094 EmitUint8(0x03);
1095 EmitOperand(reg, address);
1096}
1097
1098
Ian Rogers2c8f6532011-09-02 17:16:34 -07001099void X86Assembler::cmpl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001100 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1101 EmitUint8(0x39);
1102 EmitOperand(reg, address);
1103}
1104
1105
Ian Rogers2c8f6532011-09-02 17:16:34 -07001106void X86Assembler::cmpl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001107 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1108 EmitComplex(7, address, imm);
1109}
1110
1111
Ian Rogers2c8f6532011-09-02 17:16:34 -07001112void X86Assembler::testl(Register reg1, Register reg2) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001113 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1114 EmitUint8(0x85);
1115 EmitRegisterOperand(reg1, reg2);
1116}
1117
1118
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +01001119void X86Assembler::testl(Register reg, const Address& address) {
1120 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1121 EmitUint8(0x85);
1122 EmitOperand(reg, address);
1123}
1124
1125
Ian Rogers2c8f6532011-09-02 17:16:34 -07001126void X86Assembler::testl(Register reg, const Immediate& immediate) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001127 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1128 // For registers that have a byte variant (EAX, EBX, ECX, and EDX)
1129 // we only test the byte register to keep the encoding short.
1130 if (immediate.is_uint8() && reg < 4) {
1131 // Use zero-extended 8-bit immediate.
1132 if (reg == EAX) {
1133 EmitUint8(0xA8);
1134 } else {
1135 EmitUint8(0xF6);
1136 EmitUint8(0xC0 + reg);
1137 }
1138 EmitUint8(immediate.value() & 0xFF);
1139 } else if (reg == EAX) {
1140 // Use short form if the destination is EAX.
1141 EmitUint8(0xA9);
1142 EmitImmediate(immediate);
1143 } else {
1144 EmitUint8(0xF7);
1145 EmitOperand(0, Operand(reg));
1146 EmitImmediate(immediate);
1147 }
1148}
1149
1150
Vladimir Marko953437b2016-08-24 08:30:46 +00001151void X86Assembler::testb(const Address& dst, const Immediate& imm) {
1152 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1153 EmitUint8(0xF6);
1154 EmitOperand(EAX, dst);
1155 CHECK(imm.is_int8());
1156 EmitUint8(imm.value() & 0xFF);
1157}
1158
1159
1160void X86Assembler::testl(const Address& dst, const Immediate& imm) {
1161 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1162 EmitUint8(0xF7);
1163 EmitOperand(0, dst);
1164 EmitImmediate(imm);
1165}
1166
1167
Ian Rogers2c8f6532011-09-02 17:16:34 -07001168void X86Assembler::andl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001169 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1170 EmitUint8(0x23);
1171 EmitOperand(dst, Operand(src));
1172}
1173
1174
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001175void X86Assembler::andl(Register reg, const Address& address) {
1176 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1177 EmitUint8(0x23);
1178 EmitOperand(reg, address);
1179}
1180
1181
Ian Rogers2c8f6532011-09-02 17:16:34 -07001182void X86Assembler::andl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001183 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1184 EmitComplex(4, Operand(dst), imm);
1185}
1186
1187
Ian Rogers2c8f6532011-09-02 17:16:34 -07001188void X86Assembler::orl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001189 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1190 EmitUint8(0x0B);
1191 EmitOperand(dst, Operand(src));
1192}
1193
1194
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001195void X86Assembler::orl(Register reg, const Address& address) {
1196 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1197 EmitUint8(0x0B);
1198 EmitOperand(reg, address);
1199}
1200
1201
Ian Rogers2c8f6532011-09-02 17:16:34 -07001202void X86Assembler::orl(Register dst, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001203 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1204 EmitComplex(1, Operand(dst), imm);
1205}
1206
1207
Ian Rogers2c8f6532011-09-02 17:16:34 -07001208void X86Assembler::xorl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001209 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1210 EmitUint8(0x33);
1211 EmitOperand(dst, Operand(src));
1212}
1213
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001214
1215void X86Assembler::xorl(Register reg, const Address& address) {
1216 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1217 EmitUint8(0x33);
1218 EmitOperand(reg, address);
1219}
1220
1221
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +01001222void X86Assembler::xorl(Register dst, const Immediate& imm) {
1223 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1224 EmitComplex(6, Operand(dst), imm);
1225}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001226
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +00001227
Ian Rogers2c8f6532011-09-02 17:16:34 -07001228void X86Assembler::addl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001229 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1230 EmitComplex(0, Operand(reg), imm);
1231}
1232
1233
Ian Rogers2c8f6532011-09-02 17:16:34 -07001234void X86Assembler::addl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001235 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1236 EmitUint8(0x01);
1237 EmitOperand(reg, address);
1238}
1239
1240
Ian Rogers2c8f6532011-09-02 17:16:34 -07001241void X86Assembler::addl(const Address& address, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001242 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1243 EmitComplex(0, address, imm);
1244}
1245
1246
Ian Rogers2c8f6532011-09-02 17:16:34 -07001247void X86Assembler::adcl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001248 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1249 EmitComplex(2, Operand(reg), imm);
1250}
1251
1252
Ian Rogers2c8f6532011-09-02 17:16:34 -07001253void X86Assembler::adcl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001254 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1255 EmitUint8(0x13);
1256 EmitOperand(dst, Operand(src));
1257}
1258
1259
Ian Rogers2c8f6532011-09-02 17:16:34 -07001260void X86Assembler::adcl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001261 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1262 EmitUint8(0x13);
1263 EmitOperand(dst, address);
1264}
1265
1266
Ian Rogers2c8f6532011-09-02 17:16:34 -07001267void X86Assembler::subl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001268 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1269 EmitUint8(0x2B);
1270 EmitOperand(dst, Operand(src));
1271}
1272
1273
Ian Rogers2c8f6532011-09-02 17:16:34 -07001274void X86Assembler::subl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001275 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1276 EmitComplex(5, Operand(reg), imm);
1277}
1278
1279
Ian Rogers2c8f6532011-09-02 17:16:34 -07001280void X86Assembler::subl(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001281 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1282 EmitUint8(0x2B);
1283 EmitOperand(reg, address);
1284}
1285
1286
Mark Mendell09ed1a32015-03-25 08:30:06 -04001287void X86Assembler::subl(const Address& address, Register reg) {
1288 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1289 EmitUint8(0x29);
1290 EmitOperand(reg, address);
1291}
1292
1293
Ian Rogers2c8f6532011-09-02 17:16:34 -07001294void X86Assembler::cdq() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001295 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1296 EmitUint8(0x99);
1297}
1298
1299
Ian Rogers2c8f6532011-09-02 17:16:34 -07001300void X86Assembler::idivl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001301 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1302 EmitUint8(0xF7);
1303 EmitUint8(0xF8 | reg);
1304}
1305
1306
Ian Rogers2c8f6532011-09-02 17:16:34 -07001307void X86Assembler::imull(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001308 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1309 EmitUint8(0x0F);
1310 EmitUint8(0xAF);
1311 EmitOperand(dst, Operand(src));
1312}
1313
1314
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001315void X86Assembler::imull(Register dst, Register src, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001316 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -04001317 // See whether imm can be represented as a sign-extended 8bit value.
1318 int32_t v32 = static_cast<int32_t>(imm.value());
1319 if (IsInt<8>(v32)) {
1320 // Sign-extension works.
1321 EmitUint8(0x6B);
1322 EmitOperand(dst, Operand(src));
1323 EmitUint8(static_cast<uint8_t>(v32 & 0xFF));
1324 } else {
1325 // Not representable, use full immediate.
1326 EmitUint8(0x69);
1327 EmitOperand(dst, Operand(src));
1328 EmitImmediate(imm);
1329 }
1330}
1331
1332
1333void X86Assembler::imull(Register reg, const Immediate& imm) {
1334 imull(reg, reg, imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001335}
1336
1337
Ian Rogers2c8f6532011-09-02 17:16:34 -07001338void X86Assembler::imull(Register reg, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001339 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1340 EmitUint8(0x0F);
1341 EmitUint8(0xAF);
1342 EmitOperand(reg, address);
1343}
1344
1345
Ian Rogers2c8f6532011-09-02 17:16:34 -07001346void X86Assembler::imull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001347 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1348 EmitUint8(0xF7);
1349 EmitOperand(5, Operand(reg));
1350}
1351
1352
Ian Rogers2c8f6532011-09-02 17:16:34 -07001353void X86Assembler::imull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001354 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1355 EmitUint8(0xF7);
1356 EmitOperand(5, address);
1357}
1358
1359
Ian Rogers2c8f6532011-09-02 17:16:34 -07001360void X86Assembler::mull(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001361 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1362 EmitUint8(0xF7);
1363 EmitOperand(4, Operand(reg));
1364}
1365
1366
Ian Rogers2c8f6532011-09-02 17:16:34 -07001367void X86Assembler::mull(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001368 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1369 EmitUint8(0xF7);
1370 EmitOperand(4, address);
1371}
1372
1373
Ian Rogers2c8f6532011-09-02 17:16:34 -07001374void X86Assembler::sbbl(Register dst, Register src) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001375 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1376 EmitUint8(0x1B);
1377 EmitOperand(dst, Operand(src));
1378}
1379
1380
Ian Rogers2c8f6532011-09-02 17:16:34 -07001381void X86Assembler::sbbl(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001382 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1383 EmitComplex(3, Operand(reg), imm);
1384}
1385
1386
Ian Rogers2c8f6532011-09-02 17:16:34 -07001387void X86Assembler::sbbl(Register dst, const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001388 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1389 EmitUint8(0x1B);
1390 EmitOperand(dst, address);
1391}
1392
1393
Mark Mendell09ed1a32015-03-25 08:30:06 -04001394void X86Assembler::sbbl(const Address& address, Register src) {
1395 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1396 EmitUint8(0x19);
1397 EmitOperand(src, address);
1398}
1399
1400
Ian Rogers2c8f6532011-09-02 17:16:34 -07001401void X86Assembler::incl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001402 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1403 EmitUint8(0x40 + reg);
1404}
1405
1406
Ian Rogers2c8f6532011-09-02 17:16:34 -07001407void X86Assembler::incl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001408 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1409 EmitUint8(0xFF);
1410 EmitOperand(0, address);
1411}
1412
1413
Ian Rogers2c8f6532011-09-02 17:16:34 -07001414void X86Assembler::decl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001415 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1416 EmitUint8(0x48 + reg);
1417}
1418
1419
Ian Rogers2c8f6532011-09-02 17:16:34 -07001420void X86Assembler::decl(const Address& address) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001421 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1422 EmitUint8(0xFF);
1423 EmitOperand(1, address);
1424}
1425
1426
Ian Rogers2c8f6532011-09-02 17:16:34 -07001427void X86Assembler::shll(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001428 EmitGenericShift(4, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001429}
1430
1431
Ian Rogers2c8f6532011-09-02 17:16:34 -07001432void X86Assembler::shll(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001433 EmitGenericShift(4, Operand(operand), shifter);
1434}
1435
1436
1437void X86Assembler::shll(const Address& address, const Immediate& imm) {
1438 EmitGenericShift(4, address, imm);
1439}
1440
1441
1442void X86Assembler::shll(const Address& address, Register shifter) {
1443 EmitGenericShift(4, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001444}
1445
1446
Ian Rogers2c8f6532011-09-02 17:16:34 -07001447void X86Assembler::shrl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001448 EmitGenericShift(5, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001449}
1450
1451
Ian Rogers2c8f6532011-09-02 17:16:34 -07001452void X86Assembler::shrl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001453 EmitGenericShift(5, Operand(operand), shifter);
1454}
1455
1456
1457void X86Assembler::shrl(const Address& address, const Immediate& imm) {
1458 EmitGenericShift(5, address, imm);
1459}
1460
1461
1462void X86Assembler::shrl(const Address& address, Register shifter) {
1463 EmitGenericShift(5, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001464}
1465
1466
Ian Rogers2c8f6532011-09-02 17:16:34 -07001467void X86Assembler::sarl(Register reg, const Immediate& imm) {
Mark P Mendell73945692015-04-29 14:56:17 +00001468 EmitGenericShift(7, Operand(reg), imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001469}
1470
1471
Ian Rogers2c8f6532011-09-02 17:16:34 -07001472void X86Assembler::sarl(Register operand, Register shifter) {
Mark P Mendell73945692015-04-29 14:56:17 +00001473 EmitGenericShift(7, Operand(operand), shifter);
1474}
1475
1476
1477void X86Assembler::sarl(const Address& address, const Immediate& imm) {
1478 EmitGenericShift(7, address, imm);
1479}
1480
1481
1482void X86Assembler::sarl(const Address& address, Register shifter) {
1483 EmitGenericShift(7, address, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001484}
1485
1486
Calin Juravle9aec02f2014-11-18 23:06:35 +00001487void X86Assembler::shld(Register dst, Register src, Register shifter) {
1488 DCHECK_EQ(ECX, shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001489 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1490 EmitUint8(0x0F);
1491 EmitUint8(0xA5);
1492 EmitRegisterOperand(src, dst);
1493}
1494
1495
Mark P Mendell73945692015-04-29 14:56:17 +00001496void X86Assembler::shld(Register dst, Register src, const Immediate& imm) {
1497 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1498 EmitUint8(0x0F);
1499 EmitUint8(0xA4);
1500 EmitRegisterOperand(src, dst);
1501 EmitUint8(imm.value() & 0xFF);
1502}
1503
1504
Calin Juravle9aec02f2014-11-18 23:06:35 +00001505void X86Assembler::shrd(Register dst, Register src, Register shifter) {
1506 DCHECK_EQ(ECX, shifter);
1507 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1508 EmitUint8(0x0F);
1509 EmitUint8(0xAD);
1510 EmitRegisterOperand(src, dst);
1511}
1512
1513
Mark P Mendell73945692015-04-29 14:56:17 +00001514void X86Assembler::shrd(Register dst, Register src, const Immediate& imm) {
1515 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1516 EmitUint8(0x0F);
1517 EmitUint8(0xAC);
1518 EmitRegisterOperand(src, dst);
1519 EmitUint8(imm.value() & 0xFF);
1520}
1521
1522
Mark Mendellbcee0922015-09-15 21:45:01 -04001523void X86Assembler::roll(Register reg, const Immediate& imm) {
1524 EmitGenericShift(0, Operand(reg), imm);
1525}
1526
1527
1528void X86Assembler::roll(Register operand, Register shifter) {
1529 EmitGenericShift(0, Operand(operand), shifter);
1530}
1531
1532
1533void X86Assembler::rorl(Register reg, const Immediate& imm) {
1534 EmitGenericShift(1, Operand(reg), imm);
1535}
1536
1537
1538void X86Assembler::rorl(Register operand, Register shifter) {
1539 EmitGenericShift(1, Operand(operand), shifter);
1540}
1541
1542
Ian Rogers2c8f6532011-09-02 17:16:34 -07001543void X86Assembler::negl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001544 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1545 EmitUint8(0xF7);
1546 EmitOperand(3, Operand(reg));
1547}
1548
1549
Ian Rogers2c8f6532011-09-02 17:16:34 -07001550void X86Assembler::notl(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001551 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1552 EmitUint8(0xF7);
1553 EmitUint8(0xD0 | reg);
1554}
1555
1556
Ian Rogers2c8f6532011-09-02 17:16:34 -07001557void X86Assembler::enter(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001558 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1559 EmitUint8(0xC8);
1560 CHECK(imm.is_uint16());
1561 EmitUint8(imm.value() & 0xFF);
1562 EmitUint8((imm.value() >> 8) & 0xFF);
1563 EmitUint8(0x00);
1564}
1565
1566
Ian Rogers2c8f6532011-09-02 17:16:34 -07001567void X86Assembler::leave() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001568 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1569 EmitUint8(0xC9);
1570}
1571
1572
Ian Rogers2c8f6532011-09-02 17:16:34 -07001573void X86Assembler::ret() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001574 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1575 EmitUint8(0xC3);
1576}
1577
1578
Ian Rogers2c8f6532011-09-02 17:16:34 -07001579void X86Assembler::ret(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001580 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1581 EmitUint8(0xC2);
1582 CHECK(imm.is_uint16());
1583 EmitUint8(imm.value() & 0xFF);
1584 EmitUint8((imm.value() >> 8) & 0xFF);
1585}
1586
1587
1588
Ian Rogers2c8f6532011-09-02 17:16:34 -07001589void X86Assembler::nop() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001590 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1591 EmitUint8(0x90);
1592}
1593
1594
Ian Rogers2c8f6532011-09-02 17:16:34 -07001595void X86Assembler::int3() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001596 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1597 EmitUint8(0xCC);
1598}
1599
1600
Ian Rogers2c8f6532011-09-02 17:16:34 -07001601void X86Assembler::hlt() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001602 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1603 EmitUint8(0xF4);
1604}
1605
1606
Ian Rogers2c8f6532011-09-02 17:16:34 -07001607void X86Assembler::j(Condition condition, Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001608 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1609 if (label->IsBound()) {
1610 static const int kShortSize = 2;
1611 static const int kLongSize = 6;
1612 int offset = label->Position() - buffer_.Size();
1613 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08001614 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001615 EmitUint8(0x70 + condition);
1616 EmitUint8((offset - kShortSize) & 0xFF);
1617 } else {
1618 EmitUint8(0x0F);
1619 EmitUint8(0x80 + condition);
1620 EmitInt32(offset - kLongSize);
1621 }
1622 } else {
1623 EmitUint8(0x0F);
1624 EmitUint8(0x80 + condition);
1625 EmitLabelLink(label);
1626 }
1627}
1628
1629
Mark Mendell73f455e2015-08-21 09:30:05 -04001630void X86Assembler::j(Condition condition, NearLabel* label) {
1631 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1632 if (label->IsBound()) {
1633 static const int kShortSize = 2;
1634 int offset = label->Position() - buffer_.Size();
1635 CHECK_LE(offset, 0);
1636 CHECK(IsInt<8>(offset - kShortSize));
1637 EmitUint8(0x70 + condition);
1638 EmitUint8((offset - kShortSize) & 0xFF);
1639 } else {
1640 EmitUint8(0x70 + condition);
1641 EmitLabelLink(label);
1642 }
1643}
1644
1645
1646void X86Assembler::jecxz(NearLabel* label) {
1647 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1648 if (label->IsBound()) {
1649 static const int kShortSize = 2;
1650 int offset = label->Position() - buffer_.Size();
1651 CHECK_LE(offset, 0);
1652 CHECK(IsInt<8>(offset - kShortSize));
1653 EmitUint8(0xE3);
1654 EmitUint8((offset - kShortSize) & 0xFF);
1655 } else {
1656 EmitUint8(0xE3);
1657 EmitLabelLink(label);
1658 }
1659}
1660
1661
Ian Rogers2c8f6532011-09-02 17:16:34 -07001662void X86Assembler::jmp(Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001663 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1664 EmitUint8(0xFF);
1665 EmitRegisterOperand(4, reg);
1666}
1667
Ian Rogers7caad772012-03-30 01:07:54 -07001668void X86Assembler::jmp(const Address& address) {
1669 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1670 EmitUint8(0xFF);
1671 EmitOperand(4, address);
1672}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001673
Ian Rogers2c8f6532011-09-02 17:16:34 -07001674void X86Assembler::jmp(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001675 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1676 if (label->IsBound()) {
1677 static const int kShortSize = 2;
1678 static const int kLongSize = 5;
1679 int offset = label->Position() - buffer_.Size();
1680 CHECK_LE(offset, 0);
Andreas Gampeab1eb0d2015-02-13 19:23:55 -08001681 if (IsInt<8>(offset - kShortSize)) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001682 EmitUint8(0xEB);
1683 EmitUint8((offset - kShortSize) & 0xFF);
1684 } else {
1685 EmitUint8(0xE9);
1686 EmitInt32(offset - kLongSize);
1687 }
1688 } else {
1689 EmitUint8(0xE9);
1690 EmitLabelLink(label);
1691 }
1692}
1693
1694
Mark Mendell73f455e2015-08-21 09:30:05 -04001695void X86Assembler::jmp(NearLabel* label) {
1696 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1697 if (label->IsBound()) {
1698 static const int kShortSize = 2;
1699 int offset = label->Position() - buffer_.Size();
1700 CHECK_LE(offset, 0);
1701 CHECK(IsInt<8>(offset - kShortSize));
1702 EmitUint8(0xEB);
1703 EmitUint8((offset - kShortSize) & 0xFF);
1704 } else {
1705 EmitUint8(0xEB);
1706 EmitLabelLink(label);
1707 }
1708}
1709
1710
jessicahandojob03d6402016-09-07 12:16:53 -07001711void X86Assembler::repne_scasb() {
1712 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1713 EmitUint8(0xF2);
1714 EmitUint8(0xAE);
1715}
1716
1717
Andreas Gampe21030dd2015-05-07 14:46:15 -07001718void X86Assembler::repne_scasw() {
1719 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1720 EmitUint8(0x66);
1721 EmitUint8(0xF2);
1722 EmitUint8(0xAF);
1723}
1724
1725
jessicahandojob03d6402016-09-07 12:16:53 -07001726void X86Assembler::repe_cmpsb() {
1727 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1728 EmitUint8(0xF2);
1729 EmitUint8(0xA6);
1730}
1731
1732
agicsaki71311f82015-07-27 11:34:13 -07001733void X86Assembler::repe_cmpsw() {
1734 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1735 EmitUint8(0x66);
1736 EmitUint8(0xF3);
1737 EmitUint8(0xA7);
1738}
1739
1740
agicsaki970abfb2015-07-31 10:31:14 -07001741void X86Assembler::repe_cmpsl() {
1742 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1743 EmitUint8(0xF3);
1744 EmitUint8(0xA7);
1745}
1746
1747
jessicahandojob03d6402016-09-07 12:16:53 -07001748void X86Assembler::rep_movsb() {
1749 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1750 EmitUint8(0xF3);
1751 EmitUint8(0xA4);
1752}
1753
1754
Mark Mendellb9c4bbe2015-07-01 14:26:52 -04001755void X86Assembler::rep_movsw() {
1756 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1757 EmitUint8(0x66);
1758 EmitUint8(0xF3);
1759 EmitUint8(0xA5);
1760}
1761
1762
Ian Rogers2c8f6532011-09-02 17:16:34 -07001763X86Assembler* X86Assembler::lock() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001764 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1765 EmitUint8(0xF0);
Ian Rogers0d666d82011-08-14 16:03:46 -07001766 return this;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001767}
1768
1769
Ian Rogers2c8f6532011-09-02 17:16:34 -07001770void X86Assembler::cmpxchgl(const Address& address, Register reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001771 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1772 EmitUint8(0x0F);
1773 EmitUint8(0xB1);
1774 EmitOperand(reg, address);
1775}
1776
Mark Mendell58d25fd2015-04-03 14:52:31 -04001777
1778void X86Assembler::cmpxchg8b(const Address& address) {
1779 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1780 EmitUint8(0x0F);
1781 EmitUint8(0xC7);
1782 EmitOperand(1, address);
1783}
1784
1785
Elliott Hughes79ab9e32012-03-12 15:41:35 -07001786void X86Assembler::mfence() {
1787 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1788 EmitUint8(0x0F);
1789 EmitUint8(0xAE);
1790 EmitUint8(0xF0);
1791}
1792
Ian Rogers2c8f6532011-09-02 17:16:34 -07001793X86Assembler* X86Assembler::fs() {
Ian Rogersb033c752011-07-20 12:22:35 -07001794 // TODO: fs is a prefix and not an instruction
1795 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1796 EmitUint8(0x64);
Ian Rogers0d666d82011-08-14 16:03:46 -07001797 return this;
Ian Rogersb033c752011-07-20 12:22:35 -07001798}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001799
Ian Rogersbefbd572014-03-06 01:13:39 -08001800X86Assembler* X86Assembler::gs() {
1801 // TODO: fs is a prefix and not an instruction
1802 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1803 EmitUint8(0x65);
1804 return this;
1805}
1806
Ian Rogers2c8f6532011-09-02 17:16:34 -07001807void X86Assembler::AddImmediate(Register reg, const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001808 int value = imm.value();
1809 if (value > 0) {
1810 if (value == 1) {
1811 incl(reg);
1812 } else if (value != 0) {
1813 addl(reg, imm);
1814 }
1815 } else if (value < 0) {
1816 value = -value;
1817 if (value == 1) {
1818 decl(reg);
1819 } else if (value != 0) {
1820 subl(reg, Immediate(value));
1821 }
1822 }
1823}
1824
1825
Roland Levillain647b9ed2014-11-27 12:06:00 +00001826void X86Assembler::LoadLongConstant(XmmRegister dst, int64_t value) {
1827 // TODO: Need to have a code constants table.
1828 pushl(Immediate(High32Bits(value)));
1829 pushl(Immediate(Low32Bits(value)));
1830 movsd(dst, Address(ESP, 0));
1831 addl(ESP, Immediate(2 * sizeof(int32_t)));
1832}
1833
1834
Ian Rogers2c8f6532011-09-02 17:16:34 -07001835void X86Assembler::LoadDoubleConstant(XmmRegister dst, double value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001836 // TODO: Need to have a code constants table.
1837 int64_t constant = bit_cast<int64_t, double>(value);
Roland Levillain647b9ed2014-11-27 12:06:00 +00001838 LoadLongConstant(dst, constant);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001839}
1840
1841
Ian Rogers2c8f6532011-09-02 17:16:34 -07001842void X86Assembler::Align(int alignment, int offset) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001843 CHECK(IsPowerOfTwo(alignment));
1844 // Emit nop instruction until the real position is aligned.
1845 while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) {
1846 nop();
1847 }
1848}
1849
1850
Ian Rogers2c8f6532011-09-02 17:16:34 -07001851void X86Assembler::Bind(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001852 int bound = buffer_.Size();
1853 CHECK(!label->IsBound()); // Labels can only be bound once.
1854 while (label->IsLinked()) {
1855 int position = label->LinkPosition();
1856 int next = buffer_.Load<int32_t>(position);
1857 buffer_.Store<int32_t>(position, bound - (position + 4));
1858 label->position_ = next;
1859 }
1860 label->BindTo(bound);
1861}
1862
1863
Mark Mendell73f455e2015-08-21 09:30:05 -04001864void X86Assembler::Bind(NearLabel* label) {
1865 int bound = buffer_.Size();
1866 CHECK(!label->IsBound()); // Labels can only be bound once.
1867 while (label->IsLinked()) {
1868 int position = label->LinkPosition();
1869 uint8_t delta = buffer_.Load<uint8_t>(position);
1870 int offset = bound - (position + 1);
1871 CHECK(IsInt<8>(offset));
1872 buffer_.Store<int8_t>(position, offset);
1873 label->position_ = delta != 0u ? label->position_ - delta : 0;
1874 }
1875 label->BindTo(bound);
1876}
1877
1878
Ian Rogers44fb0d02012-03-23 16:46:24 -07001879void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
1880 CHECK_GE(reg_or_opcode, 0);
1881 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001882 const int length = operand.length_;
1883 CHECK_GT(length, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07001884 // Emit the ModRM byte updated with the given reg value.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001885 CHECK_EQ(operand.encoding_[0] & 0x38, 0);
Ian Rogers44fb0d02012-03-23 16:46:24 -07001886 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001887 // Emit the rest of the encoded operand.
1888 for (int i = 1; i < length; i++) {
1889 EmitUint8(operand.encoding_[i]);
1890 }
Mark Mendell0616ae02015-04-17 12:49:27 -04001891 AssemblerFixup* fixup = operand.GetFixup();
1892 if (fixup != nullptr) {
1893 EmitFixup(fixup);
1894 }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001895}
1896
1897
Ian Rogers2c8f6532011-09-02 17:16:34 -07001898void X86Assembler::EmitImmediate(const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001899 EmitInt32(imm.value());
1900}
1901
1902
Ian Rogers44fb0d02012-03-23 16:46:24 -07001903void X86Assembler::EmitComplex(int reg_or_opcode,
Ian Rogers2c8f6532011-09-02 17:16:34 -07001904 const Operand& operand,
1905 const Immediate& immediate) {
Ian Rogers44fb0d02012-03-23 16:46:24 -07001906 CHECK_GE(reg_or_opcode, 0);
1907 CHECK_LT(reg_or_opcode, 8);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001908 if (immediate.is_int8()) {
1909 // Use sign-extended 8-bit immediate.
1910 EmitUint8(0x83);
Ian Rogers44fb0d02012-03-23 16:46:24 -07001911 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001912 EmitUint8(immediate.value() & 0xFF);
1913 } else if (operand.IsRegister(EAX)) {
1914 // Use short form if the destination is eax.
Ian Rogers44fb0d02012-03-23 16:46:24 -07001915 EmitUint8(0x05 + (reg_or_opcode << 3));
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001916 EmitImmediate(immediate);
1917 } else {
1918 EmitUint8(0x81);
Ian Rogers44fb0d02012-03-23 16:46:24 -07001919 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001920 EmitImmediate(immediate);
1921 }
1922}
1923
1924
Ian Rogers2c8f6532011-09-02 17:16:34 -07001925void X86Assembler::EmitLabel(Label* label, int instruction_size) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001926 if (label->IsBound()) {
1927 int offset = label->Position() - buffer_.Size();
1928 CHECK_LE(offset, 0);
1929 EmitInt32(offset - instruction_size);
1930 } else {
1931 EmitLabelLink(label);
1932 }
1933}
1934
1935
Ian Rogers2c8f6532011-09-02 17:16:34 -07001936void X86Assembler::EmitLabelLink(Label* label) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001937 CHECK(!label->IsBound());
1938 int position = buffer_.Size();
1939 EmitInt32(label->position_);
1940 label->LinkTo(position);
1941}
1942
1943
Mark Mendell73f455e2015-08-21 09:30:05 -04001944void X86Assembler::EmitLabelLink(NearLabel* label) {
1945 CHECK(!label->IsBound());
1946 int position = buffer_.Size();
1947 if (label->IsLinked()) {
1948 // Save the delta in the byte that we have to play with.
1949 uint32_t delta = position - label->LinkPosition();
1950 CHECK(IsUint<8>(delta));
1951 EmitUint8(delta & 0xFF);
1952 } else {
1953 EmitUint8(0);
1954 }
1955 label->LinkTo(position);
1956}
1957
1958
Ian Rogers44fb0d02012-03-23 16:46:24 -07001959void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00001960 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07001961 const Immediate& imm) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001962 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1963 CHECK(imm.is_int8());
1964 if (imm.value() == 1) {
1965 EmitUint8(0xD1);
Mark P Mendell73945692015-04-29 14:56:17 +00001966 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001967 } else {
1968 EmitUint8(0xC1);
Mark P Mendell73945692015-04-29 14:56:17 +00001969 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001970 EmitUint8(imm.value() & 0xFF);
1971 }
1972}
1973
1974
Ian Rogers44fb0d02012-03-23 16:46:24 -07001975void X86Assembler::EmitGenericShift(int reg_or_opcode,
Mark P Mendell73945692015-04-29 14:56:17 +00001976 const Operand& operand,
Ian Rogers2c8f6532011-09-02 17:16:34 -07001977 Register shifter) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001978 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1979 CHECK_EQ(shifter, ECX);
1980 EmitUint8(0xD3);
Mark P Mendell73945692015-04-29 14:56:17 +00001981 EmitOperand(reg_or_opcode, operand);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -07001982}
1983
Mark Mendell0616ae02015-04-17 12:49:27 -04001984void X86Assembler::AddConstantArea() {
Vladimir Marko93205e32016-04-13 11:59:46 +01001985 ArrayRef<const int32_t> area = constant_area_.GetBuffer();
Mark Mendell0616ae02015-04-17 12:49:27 -04001986 // Generate the data for the literal area.
1987 for (size_t i = 0, e = area.size(); i < e; i++) {
1988 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1989 EmitInt32(area[i]);
1990 }
1991}
1992
Mark Mendell805b3b52015-09-18 14:10:29 -04001993size_t ConstantArea::AppendInt32(int32_t v) {
1994 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04001995 buffer_.push_back(v);
1996 return result;
1997}
1998
Mark Mendell805b3b52015-09-18 14:10:29 -04001999size_t ConstantArea::AddInt32(int32_t v) {
2000 for (size_t i = 0, e = buffer_.size(); i < e; i++) {
2001 if (v == buffer_[i]) {
2002 return i * elem_size_;
2003 }
2004 }
2005
2006 // Didn't match anything.
2007 return AppendInt32(v);
2008}
2009
2010size_t ConstantArea::AddInt64(int64_t v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002011 int32_t v_low = Low32Bits(v);
2012 int32_t v_high = High32Bits(v);
2013 if (buffer_.size() > 1) {
2014 // Ensure we don't pass the end of the buffer.
2015 for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) {
2016 if (v_low == buffer_[i] && v_high == buffer_[i + 1]) {
Mark Mendell805b3b52015-09-18 14:10:29 -04002017 return i * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002018 }
2019 }
2020 }
2021
2022 // Didn't match anything.
Mark Mendell805b3b52015-09-18 14:10:29 -04002023 size_t result = buffer_.size() * elem_size_;
Mark Mendell0616ae02015-04-17 12:49:27 -04002024 buffer_.push_back(v_low);
2025 buffer_.push_back(v_high);
2026 return result;
2027}
2028
Mark Mendell805b3b52015-09-18 14:10:29 -04002029size_t ConstantArea::AddDouble(double v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002030 // Treat the value as a 64-bit integer value.
2031 return AddInt64(bit_cast<int64_t, double>(v));
2032}
2033
Mark Mendell805b3b52015-09-18 14:10:29 -04002034size_t ConstantArea::AddFloat(float v) {
Mark Mendell0616ae02015-04-17 12:49:27 -04002035 // Treat the value as a 32-bit integer value.
2036 return AddInt32(bit_cast<int32_t, float>(v));
2037}
2038
Ian Rogers2c8f6532011-09-02 17:16:34 -07002039} // namespace x86
Ian Rogersb033c752011-07-20 12:22:35 -07002040} // namespace art