Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Processor capabilities determination functions. |
| 3 | * |
| 4 | * Copyright (C) xxxx the Anonymous |
Ralf Baechle | 010b853 | 2006-01-29 18:42:08 +0000 | [diff] [blame] | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 7 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/init.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/ptrace.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 17 | #include <linux/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/stddef.h> |
Paul Gortmaker | 73bc256 | 2011-07-23 16:30:40 -0400 | [diff] [blame] | 19 | #include <linux/export.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
Ralf Baechle | 5759906 | 2007-02-18 19:07:31 +0000 | [diff] [blame] | 21 | #include <asm/bugs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <asm/cpu.h> |
Maciej W. Rozycki | f684362 | 2015-04-03 23:27:26 +0100 | [diff] [blame] | 23 | #include <asm/cpu-features.h> |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 24 | #include <asm/cpu-type.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #include <asm/fpu.h> |
| 26 | #include <asm/mipsregs.h> |
Paul Burton | 30ee615 | 2014-03-27 10:57:30 +0000 | [diff] [blame] | 27 | #include <asm/mipsmtregs.h> |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 28 | #include <asm/msa.h> |
David Daney | 654f57b | 2008-09-23 00:07:16 -0700 | [diff] [blame] | 29 | #include <asm/watch.h> |
Paul Gortmaker | 06372a6 | 2011-07-23 16:26:41 -0400 | [diff] [blame] | 30 | #include <asm/elf.h> |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 31 | #include <asm/pgtable-bits.h> |
Chris Dearman | a074f0e | 2009-07-10 01:51:27 -0700 | [diff] [blame] | 32 | #include <asm/spram.h> |
Linus Torvalds | 7c0f6ba | 2016-12-24 11:46:01 -0800 | [diff] [blame] | 33 | #include <linux/uaccess.h> |
David Daney | 949e51b | 2010-10-14 11:32:33 -0700 | [diff] [blame] | 34 | |
Paul Burton | e14f1db | 2015-07-27 12:58:23 -0700 | [diff] [blame] | 35 | /* Hardware capabilities */ |
| 36 | unsigned int elf_hwcap __read_mostly; |
Marcin Nowakowski | 05510f2 | 2017-03-07 14:19:56 +0100 | [diff] [blame] | 37 | EXPORT_SYMBOL_GPL(elf_hwcap); |
Paul Burton | e14f1db | 2015-07-27 12:58:23 -0700 | [diff] [blame] | 38 | |
Maciej W. Rozycki | f684362 | 2015-04-03 23:27:26 +0100 | [diff] [blame] | 39 | /* |
Maciej W. Rozycki | 7aecd5c | 2015-04-03 23:27:54 +0100 | [diff] [blame] | 40 | * Get the FPU Implementation/Revision. |
| 41 | */ |
| 42 | static inline unsigned long cpu_get_fpu_id(void) |
| 43 | { |
| 44 | unsigned long tmp, fpu_id; |
| 45 | |
| 46 | tmp = read_c0_status(); |
| 47 | __enable_fpu(FPU_AS_IS); |
| 48 | fpu_id = read_32bit_cp1_register(CP1_REVISION); |
| 49 | write_c0_status(tmp); |
| 50 | return fpu_id; |
| 51 | } |
| 52 | |
| 53 | /* |
| 54 | * Check if the CPU has an external FPU. |
| 55 | */ |
| 56 | static inline int __cpu_has_fpu(void) |
| 57 | { |
| 58 | return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; |
| 59 | } |
| 60 | |
| 61 | static inline unsigned long cpu_get_msa_id(void) |
| 62 | { |
| 63 | unsigned long status, msa_id; |
| 64 | |
| 65 | status = read_c0_status(); |
| 66 | __enable_fpu(FPU_64BIT); |
| 67 | enable_msa(); |
| 68 | msa_id = read_msa_ir(); |
| 69 | disable_msa(); |
| 70 | write_c0_status(status); |
| 71 | return msa_id; |
| 72 | } |
| 73 | |
| 74 | /* |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 75 | * Determine the FCSR mask for FPU hardware. |
| 76 | */ |
| 77 | static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) |
| 78 | { |
| 79 | unsigned long sr, mask, fcsr, fcsr0, fcsr1; |
| 80 | |
Maciej W. Rozycki | 90b712d | 2015-06-02 17:50:59 +0100 | [diff] [blame] | 81 | fcsr = c->fpu_csr31; |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 82 | mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; |
| 83 | |
| 84 | sr = read_c0_status(); |
| 85 | __enable_fpu(FPU_AS_IS); |
| 86 | |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 87 | fcsr0 = fcsr & mask; |
| 88 | write_32bit_cp1_register(CP1_STATUS, fcsr0); |
| 89 | fcsr0 = read_32bit_cp1_register(CP1_STATUS); |
| 90 | |
| 91 | fcsr1 = fcsr | ~mask; |
| 92 | write_32bit_cp1_register(CP1_STATUS, fcsr1); |
| 93 | fcsr1 = read_32bit_cp1_register(CP1_STATUS); |
| 94 | |
| 95 | write_32bit_cp1_register(CP1_STATUS, fcsr); |
| 96 | |
| 97 | write_c0_status(sr); |
| 98 | |
| 99 | c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; |
| 100 | } |
| 101 | |
| 102 | /* |
Maciej W. Rozycki | 93adeaf | 2015-11-13 00:48:15 +0000 | [diff] [blame] | 103 | * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes |
| 104 | * supported by FPU hardware. |
| 105 | */ |
| 106 | static void cpu_set_fpu_2008(struct cpuinfo_mips *c) |
| 107 | { |
| 108 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | |
| 109 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | |
| 110 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { |
| 111 | unsigned long sr, fir, fcsr, fcsr0, fcsr1; |
| 112 | |
| 113 | sr = read_c0_status(); |
| 114 | __enable_fpu(FPU_AS_IS); |
| 115 | |
| 116 | fir = read_32bit_cp1_register(CP1_REVISION); |
| 117 | if (fir & MIPS_FPIR_HAS2008) { |
| 118 | fcsr = read_32bit_cp1_register(CP1_STATUS); |
| 119 | |
| 120 | fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); |
| 121 | write_32bit_cp1_register(CP1_STATUS, fcsr0); |
| 122 | fcsr0 = read_32bit_cp1_register(CP1_STATUS); |
| 123 | |
| 124 | fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; |
| 125 | write_32bit_cp1_register(CP1_STATUS, fcsr1); |
| 126 | fcsr1 = read_32bit_cp1_register(CP1_STATUS); |
| 127 | |
| 128 | write_32bit_cp1_register(CP1_STATUS, fcsr); |
| 129 | |
| 130 | if (!(fcsr0 & FPU_CSR_NAN2008)) |
| 131 | c->options |= MIPS_CPU_NAN_LEGACY; |
| 132 | if (fcsr1 & FPU_CSR_NAN2008) |
| 133 | c->options |= MIPS_CPU_NAN_2008; |
| 134 | |
| 135 | if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008) |
| 136 | c->fpu_msk31 &= ~FPU_CSR_ABS2008; |
| 137 | else |
| 138 | c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008; |
| 139 | |
| 140 | if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008) |
| 141 | c->fpu_msk31 &= ~FPU_CSR_NAN2008; |
| 142 | else |
| 143 | c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008; |
| 144 | } else { |
| 145 | c->options |= MIPS_CPU_NAN_LEGACY; |
| 146 | } |
| 147 | |
| 148 | write_c0_status(sr); |
| 149 | } else { |
| 150 | c->options |= MIPS_CPU_NAN_LEGACY; |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | /* |
Maciej W. Rozycki | 503943e | 2015-11-13 00:48:29 +0000 | [diff] [blame] | 155 | * IEEE 754 conformance mode to use. Affects the NaN encoding and the |
| 156 | * ABS.fmt/NEG.fmt execution mode. |
| 157 | */ |
| 158 | static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT; |
| 159 | |
| 160 | /* |
| 161 | * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes |
| 162 | * to support by the FPU emulator according to the IEEE 754 conformance |
| 163 | * mode selected. Note that "relaxed" straps the emulator so that it |
| 164 | * allows 2008-NaN binaries even for legacy processors. |
Maciej W. Rozycki | 93adeaf | 2015-11-13 00:48:15 +0000 | [diff] [blame] | 165 | */ |
| 166 | static void cpu_set_nofpu_2008(struct cpuinfo_mips *c) |
| 167 | { |
Maciej W. Rozycki | 503943e | 2015-11-13 00:48:29 +0000 | [diff] [blame] | 168 | c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY); |
Maciej W. Rozycki | 93adeaf | 2015-11-13 00:48:15 +0000 | [diff] [blame] | 169 | c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); |
Maciej W. Rozycki | 503943e | 2015-11-13 00:48:29 +0000 | [diff] [blame] | 170 | c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); |
| 171 | |
| 172 | switch (ieee754) { |
| 173 | case STRICT: |
| 174 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | |
| 175 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | |
| 176 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { |
| 177 | c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; |
| 178 | } else { |
| 179 | c->options |= MIPS_CPU_NAN_LEGACY; |
| 180 | c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; |
| 181 | } |
| 182 | break; |
| 183 | case LEGACY: |
Maciej W. Rozycki | 93adeaf | 2015-11-13 00:48:15 +0000 | [diff] [blame] | 184 | c->options |= MIPS_CPU_NAN_LEGACY; |
| 185 | c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; |
Maciej W. Rozycki | 503943e | 2015-11-13 00:48:29 +0000 | [diff] [blame] | 186 | break; |
| 187 | case STD2008: |
| 188 | c->options |= MIPS_CPU_NAN_2008; |
| 189 | c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; |
| 190 | c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; |
| 191 | break; |
| 192 | case RELAXED: |
| 193 | c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; |
| 194 | break; |
Maciej W. Rozycki | 93adeaf | 2015-11-13 00:48:15 +0000 | [diff] [blame] | 195 | } |
| 196 | } |
| 197 | |
| 198 | /* |
Maciej W. Rozycki | 503943e | 2015-11-13 00:48:29 +0000 | [diff] [blame] | 199 | * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode |
| 200 | * according to the "ieee754=" parameter. |
| 201 | */ |
| 202 | static void cpu_set_nan_2008(struct cpuinfo_mips *c) |
| 203 | { |
| 204 | switch (ieee754) { |
| 205 | case STRICT: |
| 206 | mips_use_nan_legacy = !!cpu_has_nan_legacy; |
| 207 | mips_use_nan_2008 = !!cpu_has_nan_2008; |
| 208 | break; |
| 209 | case LEGACY: |
| 210 | mips_use_nan_legacy = !!cpu_has_nan_legacy; |
| 211 | mips_use_nan_2008 = !cpu_has_nan_legacy; |
| 212 | break; |
| 213 | case STD2008: |
| 214 | mips_use_nan_legacy = !cpu_has_nan_2008; |
| 215 | mips_use_nan_2008 = !!cpu_has_nan_2008; |
| 216 | break; |
| 217 | case RELAXED: |
| 218 | mips_use_nan_legacy = true; |
| 219 | mips_use_nan_2008 = true; |
| 220 | break; |
| 221 | } |
| 222 | } |
| 223 | |
| 224 | /* |
| 225 | * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override |
| 226 | * settings: |
| 227 | * |
| 228 | * strict: accept binaries that request a NaN encoding supported by the FPU |
| 229 | * legacy: only accept legacy-NaN binaries |
| 230 | * 2008: only accept 2008-NaN binaries |
| 231 | * relaxed: accept any binaries regardless of whether supported by the FPU |
| 232 | */ |
| 233 | static int __init ieee754_setup(char *s) |
| 234 | { |
| 235 | if (!s) |
| 236 | return -1; |
| 237 | else if (!strcmp(s, "strict")) |
| 238 | ieee754 = STRICT; |
| 239 | else if (!strcmp(s, "legacy")) |
| 240 | ieee754 = LEGACY; |
| 241 | else if (!strcmp(s, "2008")) |
| 242 | ieee754 = STD2008; |
| 243 | else if (!strcmp(s, "relaxed")) |
| 244 | ieee754 = RELAXED; |
| 245 | else |
| 246 | return -1; |
| 247 | |
| 248 | if (!(boot_cpu_data.options & MIPS_CPU_FPU)) |
| 249 | cpu_set_nofpu_2008(&boot_cpu_data); |
| 250 | cpu_set_nan_2008(&boot_cpu_data); |
| 251 | |
| 252 | return 0; |
| 253 | } |
| 254 | |
| 255 | early_param("ieee754", ieee754_setup); |
| 256 | |
| 257 | /* |
Maciej W. Rozycki | f684362 | 2015-04-03 23:27:26 +0100 | [diff] [blame] | 258 | * Set the FIR feature flags for the FPU emulator. |
| 259 | */ |
| 260 | static void cpu_set_nofpu_id(struct cpuinfo_mips *c) |
| 261 | { |
| 262 | u32 value; |
| 263 | |
| 264 | value = 0; |
| 265 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | |
| 266 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | |
| 267 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) |
| 268 | value |= MIPS_FPIR_D | MIPS_FPIR_S; |
| 269 | if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | |
| 270 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) |
| 271 | value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; |
Maciej W. Rozycki | 90d53a9 | 2015-11-13 00:47:28 +0000 | [diff] [blame] | 272 | if (c->options & MIPS_CPU_NAN_2008) |
| 273 | value |= MIPS_FPIR_HAS2008; |
Maciej W. Rozycki | f684362 | 2015-04-03 23:27:26 +0100 | [diff] [blame] | 274 | c->fpu_id = value; |
| 275 | } |
| 276 | |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 277 | /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ |
| 278 | static unsigned int mips_nofpu_msk31; |
| 279 | |
Maciej W. Rozycki | 7aecd5c | 2015-04-03 23:27:54 +0100 | [diff] [blame] | 280 | /* |
| 281 | * Set options for FPU hardware. |
| 282 | */ |
| 283 | static void cpu_set_fpu_opts(struct cpuinfo_mips *c) |
| 284 | { |
| 285 | c->fpu_id = cpu_get_fpu_id(); |
| 286 | mips_nofpu_msk31 = c->fpu_msk31; |
| 287 | |
| 288 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | |
| 289 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | |
| 290 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { |
| 291 | if (c->fpu_id & MIPS_FPIR_3D) |
| 292 | c->ases |= MIPS_ASE_MIPS3D; |
James Hogan | 4e87580 | 2017-03-14 10:15:08 +0000 | [diff] [blame] | 293 | if (c->fpu_id & MIPS_FPIR_UFRP) |
| 294 | c->options |= MIPS_CPU_UFR; |
Maciej W. Rozycki | 7aecd5c | 2015-04-03 23:27:54 +0100 | [diff] [blame] | 295 | if (c->fpu_id & MIPS_FPIR_FREP) |
| 296 | c->options |= MIPS_CPU_FRE; |
| 297 | } |
| 298 | |
| 299 | cpu_set_fpu_fcsr_mask(c); |
Maciej W. Rozycki | 93adeaf | 2015-11-13 00:48:15 +0000 | [diff] [blame] | 300 | cpu_set_fpu_2008(c); |
Maciej W. Rozycki | 503943e | 2015-11-13 00:48:29 +0000 | [diff] [blame] | 301 | cpu_set_nan_2008(c); |
Maciej W. Rozycki | 7aecd5c | 2015-04-03 23:27:54 +0100 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | /* |
| 305 | * Set options for the FPU emulator. |
| 306 | */ |
| 307 | static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) |
| 308 | { |
| 309 | c->options &= ~MIPS_CPU_FPU; |
| 310 | c->fpu_msk31 = mips_nofpu_msk31; |
| 311 | |
Maciej W. Rozycki | 93adeaf | 2015-11-13 00:48:15 +0000 | [diff] [blame] | 312 | cpu_set_nofpu_2008(c); |
Maciej W. Rozycki | 503943e | 2015-11-13 00:48:29 +0000 | [diff] [blame] | 313 | cpu_set_nan_2008(c); |
Maciej W. Rozycki | 7aecd5c | 2015-04-03 23:27:54 +0100 | [diff] [blame] | 314 | cpu_set_nofpu_id(c); |
| 315 | } |
| 316 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 317 | static int mips_fpu_disabled; |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 318 | |
| 319 | static int __init fpu_disable(char *s) |
| 320 | { |
Maciej W. Rozycki | 7aecd5c | 2015-04-03 23:27:54 +0100 | [diff] [blame] | 321 | cpu_set_nofpu_opts(&boot_cpu_data); |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 322 | mips_fpu_disabled = 1; |
| 323 | |
| 324 | return 1; |
| 325 | } |
| 326 | |
| 327 | __setup("nofpu", fpu_disable); |
| 328 | |
Paul Burton | b7fc2cc | 2017-08-23 11:17:54 -0700 | [diff] [blame] | 329 | static int mips_dsp_disabled; |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 330 | |
| 331 | static int __init dsp_disable(char *s) |
| 332 | { |
Steven J. Hill | ee80f7c7 | 2012-08-03 10:26:04 -0500 | [diff] [blame] | 333 | cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 334 | mips_dsp_disabled = 1; |
| 335 | |
| 336 | return 1; |
| 337 | } |
| 338 | |
| 339 | __setup("nodsp", dsp_disable); |
| 340 | |
Markos Chandras | 3d528b3 | 2014-07-14 12:46:13 +0100 | [diff] [blame] | 341 | static int mips_htw_disabled; |
| 342 | |
| 343 | static int __init htw_disable(char *s) |
| 344 | { |
| 345 | mips_htw_disabled = 1; |
| 346 | cpu_data[0].options &= ~MIPS_CPU_HTW; |
| 347 | write_c0_pwctl(read_c0_pwctl() & |
| 348 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); |
| 349 | |
| 350 | return 1; |
| 351 | } |
| 352 | |
| 353 | __setup("nohtw", htw_disable); |
| 354 | |
Markos Chandras | 97f4ad2 | 2014-08-29 09:37:26 +0100 | [diff] [blame] | 355 | static int mips_ftlb_disabled; |
| 356 | static int mips_has_ftlb_configured; |
| 357 | |
Paul Burton | ebd0e0f | 2016-08-19 18:18:27 +0100 | [diff] [blame] | 358 | enum ftlb_flags { |
| 359 | FTLB_EN = 1 << 0, |
| 360 | FTLB_SET_PROB = 1 << 1, |
| 361 | }; |
| 362 | |
| 363 | static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); |
Markos Chandras | 97f4ad2 | 2014-08-29 09:37:26 +0100 | [diff] [blame] | 364 | |
| 365 | static int __init ftlb_disable(char *s) |
| 366 | { |
| 367 | unsigned int config4, mmuextdef; |
| 368 | |
| 369 | /* |
| 370 | * If the core hasn't done any FTLB configuration, there is nothing |
| 371 | * for us to do here. |
| 372 | */ |
| 373 | if (!mips_has_ftlb_configured) |
| 374 | return 1; |
| 375 | |
| 376 | /* Disable it in the boot cpu */ |
Markos Chandras | 912708c | 2015-07-09 10:40:51 +0100 | [diff] [blame] | 377 | if (set_ftlb_enable(&cpu_data[0], 0)) { |
| 378 | pr_warn("Can't turn FTLB off\n"); |
| 379 | return 1; |
| 380 | } |
Markos Chandras | 97f4ad2 | 2014-08-29 09:37:26 +0100 | [diff] [blame] | 381 | |
Markos Chandras | 97f4ad2 | 2014-08-29 09:37:26 +0100 | [diff] [blame] | 382 | config4 = read_c0_config4(); |
| 383 | |
| 384 | /* Check that FTLB has been disabled */ |
| 385 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; |
| 386 | /* MMUSIZEEXT == VTLB ON, FTLB OFF */ |
| 387 | if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { |
| 388 | /* This should never happen */ |
| 389 | pr_warn("FTLB could not be disabled!\n"); |
| 390 | return 1; |
| 391 | } |
| 392 | |
| 393 | mips_ftlb_disabled = 1; |
| 394 | mips_has_ftlb_configured = 0; |
| 395 | |
| 396 | /* |
| 397 | * noftlb is mainly used for debug purposes so print |
| 398 | * an informative message instead of using pr_debug() |
| 399 | */ |
| 400 | pr_info("FTLB has been disabled\n"); |
| 401 | |
| 402 | /* |
| 403 | * Some of these bits are duplicated in the decode_config4. |
| 404 | * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case |
| 405 | * once FTLB has been disabled so undo what decode_config4 did. |
| 406 | */ |
| 407 | cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * |
| 408 | cpu_data[0].tlbsizeftlbsets; |
| 409 | cpu_data[0].tlbsizeftlbsets = 0; |
| 410 | cpu_data[0].tlbsizeftlbways = 0; |
| 411 | |
| 412 | return 1; |
| 413 | } |
| 414 | |
| 415 | __setup("noftlb", ftlb_disable); |
| 416 | |
| 417 | |
Marc St-Jean | 9267a30 | 2007-06-14 15:55:31 -0600 | [diff] [blame] | 418 | static inline void check_errata(void) |
| 419 | { |
| 420 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 421 | |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 422 | switch (current_cpu_type()) { |
Marc St-Jean | 9267a30 | 2007-06-14 15:55:31 -0600 | [diff] [blame] | 423 | case CPU_34K: |
| 424 | /* |
| 425 | * Erratum "RPS May Cause Incorrect Instruction Execution" |
Ralf Baechle | b633648 | 2014-05-23 16:29:44 +0200 | [diff] [blame] | 426 | * This code only handles VPE0, any SMP/RTOS code |
Marc St-Jean | 9267a30 | 2007-06-14 15:55:31 -0600 | [diff] [blame] | 427 | * making use of VPE1 will be responsable for that VPE. |
| 428 | */ |
| 429 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) |
| 430 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); |
| 431 | break; |
| 432 | default: |
| 433 | break; |
| 434 | } |
| 435 | } |
| 436 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 437 | void __init check_bugs32(void) |
| 438 | { |
Marc St-Jean | 9267a30 | 2007-06-14 15:55:31 -0600 | [diff] [blame] | 439 | check_errata(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | } |
| 441 | |
| 442 | /* |
| 443 | * Probe whether cpu has config register by trying to play with |
| 444 | * alternate cache bit and see whether it matters. |
| 445 | * It's used by cpu_probe to distinguish between R3000A and R3081. |
| 446 | */ |
| 447 | static inline int cpu_has_confreg(void) |
| 448 | { |
| 449 | #ifdef CONFIG_CPU_R3000 |
| 450 | extern unsigned long r3k_cache_size(unsigned long); |
| 451 | unsigned long size1, size2; |
| 452 | unsigned long cfg = read_c0_conf(); |
| 453 | |
| 454 | size1 = r3k_cache_size(ST0_ISC); |
| 455 | write_c0_conf(cfg ^ R30XX_CONF_AC); |
| 456 | size2 = r3k_cache_size(ST0_ISC); |
| 457 | write_c0_conf(cfg); |
| 458 | return size1 != size2; |
| 459 | #else |
| 460 | return 0; |
| 461 | #endif |
| 462 | } |
| 463 | |
Robert Millan | c094c99 | 2011-04-18 11:37:55 -0700 | [diff] [blame] | 464 | static inline void set_elf_platform(int cpu, const char *plat) |
| 465 | { |
| 466 | if (cpu == 0) |
| 467 | __elf_platform = plat; |
| 468 | } |
| 469 | |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 470 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
| 471 | { |
| 472 | #ifdef __NEED_VMBITS_PROBE |
David Daney | 5b7efa8 | 2010-02-08 12:27:00 -0800 | [diff] [blame] | 473 | write_c0_entryhi(0x3fffffffffffe000ULL); |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 474 | back_to_back_c0_hazard(); |
David Daney | 5b7efa8 | 2010-02-08 12:27:00 -0800 | [diff] [blame] | 475 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 476 | #endif |
| 477 | } |
| 478 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 479 | static void set_isa(struct cpuinfo_mips *c, unsigned int isa) |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 480 | { |
| 481 | switch (isa) { |
| 482 | case MIPS_CPU_ISA_M64R2: |
| 483 | c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; |
| 484 | case MIPS_CPU_ISA_M64R1: |
| 485 | c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; |
| 486 | case MIPS_CPU_ISA_V: |
| 487 | c->isa_level |= MIPS_CPU_ISA_V; |
| 488 | case MIPS_CPU_ISA_IV: |
| 489 | c->isa_level |= MIPS_CPU_ISA_IV; |
| 490 | case MIPS_CPU_ISA_III: |
Ralf Baechle | 1990e54 | 2013-06-26 17:06:34 +0200 | [diff] [blame] | 491 | c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 492 | break; |
| 493 | |
Leonid Yegoshin | 8b8aa63 | 2014-11-13 13:51:51 +0000 | [diff] [blame] | 494 | /* R6 incompatible with everything else */ |
| 495 | case MIPS_CPU_ISA_M64R6: |
| 496 | c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; |
| 497 | case MIPS_CPU_ISA_M32R6: |
| 498 | c->isa_level |= MIPS_CPU_ISA_M32R6; |
| 499 | /* Break here so we don't add incompatible ISAs */ |
| 500 | break; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 501 | case MIPS_CPU_ISA_M32R2: |
| 502 | c->isa_level |= MIPS_CPU_ISA_M32R2; |
| 503 | case MIPS_CPU_ISA_M32R1: |
| 504 | c->isa_level |= MIPS_CPU_ISA_M32R1; |
| 505 | case MIPS_CPU_ISA_II: |
| 506 | c->isa_level |= MIPS_CPU_ISA_II; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 507 | break; |
| 508 | } |
| 509 | } |
| 510 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 511 | static char unknown_isa[] = KERN_ERR \ |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 512 | "Unsupported ISA type, c0.config0: %d."; |
| 513 | |
Markos Chandras | cf0a8aa | 2014-11-10 12:25:34 +0000 | [diff] [blame] | 514 | static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) |
| 515 | { |
| 516 | |
| 517 | unsigned int probability = c->tlbsize / c->tlbsizevtlb; |
| 518 | |
| 519 | /* |
| 520 | * 0 = All TLBWR instructions go to FTLB |
| 521 | * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the |
| 522 | * FTLB and 1 goes to the VTLB. |
| 523 | * 2 = 7:1: As above with 7:1 ratio. |
| 524 | * 3 = 3:1: As above with 3:1 ratio. |
| 525 | * |
| 526 | * Use the linear midpoint as the probability threshold. |
| 527 | */ |
| 528 | if (probability >= 12) |
| 529 | return 1; |
| 530 | else if (probability >= 6) |
| 531 | return 2; |
| 532 | else |
| 533 | /* |
| 534 | * So FTLB is less than 4 times bigger than VTLB. |
| 535 | * A 3:1 ratio can still be useful though. |
| 536 | */ |
| 537 | return 3; |
| 538 | } |
| 539 | |
Paul Burton | ebd0e0f | 2016-08-19 18:18:27 +0100 | [diff] [blame] | 540 | static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 541 | { |
Markos Chandras | 20a7f7e | 2015-07-09 10:40:53 +0100 | [diff] [blame] | 542 | unsigned int config; |
James Hogan | d83b0e8 | 2014-01-22 16:19:40 +0000 | [diff] [blame] | 543 | |
| 544 | /* It's implementation dependent how the FTLB can be enabled */ |
| 545 | switch (c->cputype) { |
| 546 | case CPU_PROAPTIV: |
| 547 | case CPU_P5600: |
Paul Burton | 1091bfa | 2016-02-03 03:26:38 +0000 | [diff] [blame] | 548 | case CPU_P6600: |
James Hogan | d83b0e8 | 2014-01-22 16:19:40 +0000 | [diff] [blame] | 549 | /* proAptiv & related cores use Config6 to enable the FTLB */ |
Markos Chandras | 20a7f7e | 2015-07-09 10:40:53 +0100 | [diff] [blame] | 550 | config = read_c0_config6(); |
Paul Burton | ebd0e0f | 2016-08-19 18:18:27 +0100 | [diff] [blame] | 551 | |
| 552 | if (flags & FTLB_EN) |
| 553 | config |= MIPS_CONF6_FTLBEN; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 554 | else |
Paul Burton | ebd0e0f | 2016-08-19 18:18:27 +0100 | [diff] [blame] | 555 | config &= ~MIPS_CONF6_FTLBEN; |
| 556 | |
| 557 | if (flags & FTLB_SET_PROB) { |
| 558 | config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); |
| 559 | config |= calculate_ftlb_probability(c) |
| 560 | << MIPS_CONF6_FTLBP_SHIFT; |
| 561 | } |
| 562 | |
| 563 | write_c0_config6(config); |
Paul Burton | 67acd8d | 2016-08-19 18:18:28 +0100 | [diff] [blame] | 564 | back_to_back_c0_hazard(); |
Markos Chandras | 20a7f7e | 2015-07-09 10:40:53 +0100 | [diff] [blame] | 565 | break; |
| 566 | case CPU_I6400: |
Paul Burton | 859aeb1 | 2017-06-02 12:39:04 -0700 | [diff] [blame] | 567 | case CPU_I6500: |
Paul Burton | 72c70f0 | 2016-08-19 18:18:26 +0100 | [diff] [blame] | 568 | /* There's no way to disable the FTLB */ |
Paul Burton | ebd0e0f | 2016-08-19 18:18:27 +0100 | [diff] [blame] | 569 | if (!(flags & FTLB_EN)) |
| 570 | return 1; |
| 571 | return 0; |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 572 | case CPU_LOONGSON3: |
Huacai Chen | 06e4814 | 2016-03-03 09:45:11 +0800 | [diff] [blame] | 573 | /* Flush ITLB, DTLB, VTLB and FTLB */ |
| 574 | write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | |
| 575 | LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 576 | /* Loongson-3 cores use Config6 to enable the FTLB */ |
| 577 | config = read_c0_config6(); |
Paul Burton | ebd0e0f | 2016-08-19 18:18:27 +0100 | [diff] [blame] | 578 | if (flags & FTLB_EN) |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 579 | /* Enable FTLB */ |
| 580 | write_c0_config6(config & ~MIPS_CONF6_FTLBDIS); |
| 581 | else |
| 582 | /* Disable FTLB */ |
| 583 | write_c0_config6(config | MIPS_CONF6_FTLBDIS); |
| 584 | break; |
Markos Chandras | 912708c | 2015-07-09 10:40:51 +0100 | [diff] [blame] | 585 | default: |
| 586 | return 1; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 587 | } |
Markos Chandras | 912708c | 2015-07-09 10:40:51 +0100 | [diff] [blame] | 588 | |
| 589 | return 0; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 590 | } |
| 591 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 592 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
| 593 | { |
| 594 | unsigned int config0; |
James Hogan | 2f6f313 | 2015-09-17 17:49:20 +0100 | [diff] [blame] | 595 | int isa, mt; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 596 | |
| 597 | config0 = read_c0_config(); |
| 598 | |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 599 | /* |
| 600 | * Look for Standard TLB or Dual VTLB and FTLB |
| 601 | */ |
James Hogan | 2f6f313 | 2015-09-17 17:49:20 +0100 | [diff] [blame] | 602 | mt = config0 & MIPS_CONF_MT; |
| 603 | if (mt == MIPS_CONF_MT_TLB) |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 604 | c->options |= MIPS_CPU_TLB; |
James Hogan | 2f6f313 | 2015-09-17 17:49:20 +0100 | [diff] [blame] | 605 | else if (mt == MIPS_CONF_MT_FTLB) |
| 606 | c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 607 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 608 | isa = (config0 & MIPS_CONF_AT) >> 13; |
| 609 | switch (isa) { |
| 610 | case 0: |
| 611 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
| 612 | case 0: |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 613 | set_isa(c, MIPS_CPU_ISA_M32R1); |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 614 | break; |
| 615 | case 1: |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 616 | set_isa(c, MIPS_CPU_ISA_M32R2); |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 617 | break; |
Leonid Yegoshin | 8b8aa63 | 2014-11-13 13:51:51 +0000 | [diff] [blame] | 618 | case 2: |
| 619 | set_isa(c, MIPS_CPU_ISA_M32R6); |
| 620 | break; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 621 | default: |
| 622 | goto unknown; |
| 623 | } |
| 624 | break; |
| 625 | case 2: |
| 626 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
| 627 | case 0: |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 628 | set_isa(c, MIPS_CPU_ISA_M64R1); |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 629 | break; |
| 630 | case 1: |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 631 | set_isa(c, MIPS_CPU_ISA_M64R2); |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 632 | break; |
Leonid Yegoshin | 8b8aa63 | 2014-11-13 13:51:51 +0000 | [diff] [blame] | 633 | case 2: |
| 634 | set_isa(c, MIPS_CPU_ISA_M64R6); |
| 635 | break; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 636 | default: |
| 637 | goto unknown; |
| 638 | } |
| 639 | break; |
| 640 | default: |
| 641 | goto unknown; |
| 642 | } |
| 643 | |
| 644 | return config0 & MIPS_CONF_M; |
| 645 | |
| 646 | unknown: |
| 647 | panic(unknown_isa, config0); |
| 648 | } |
| 649 | |
| 650 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) |
| 651 | { |
| 652 | unsigned int config1; |
| 653 | |
| 654 | config1 = read_c0_config1(); |
| 655 | |
| 656 | if (config1 & MIPS_CONF1_MD) |
| 657 | c->ases |= MIPS_ASE_MDMX; |
James Hogan | 30228c4 | 2016-05-11 13:50:53 +0100 | [diff] [blame] | 658 | if (config1 & MIPS_CONF1_PC) |
| 659 | c->options |= MIPS_CPU_PERF; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 660 | if (config1 & MIPS_CONF1_WR) |
| 661 | c->options |= MIPS_CPU_WATCH; |
| 662 | if (config1 & MIPS_CONF1_CA) |
| 663 | c->ases |= MIPS_ASE_MIPS16; |
| 664 | if (config1 & MIPS_CONF1_EP) |
| 665 | c->options |= MIPS_CPU_EJTAG; |
| 666 | if (config1 & MIPS_CONF1_FP) { |
| 667 | c->options |= MIPS_CPU_FPU; |
| 668 | c->options |= MIPS_CPU_32FPR; |
| 669 | } |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 670 | if (cpu_has_tlb) { |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 671 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 672 | c->tlbsizevtlb = c->tlbsize; |
| 673 | c->tlbsizeftlbsets = 0; |
| 674 | } |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 675 | |
| 676 | return config1 & MIPS_CONF_M; |
| 677 | } |
| 678 | |
| 679 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) |
| 680 | { |
| 681 | unsigned int config2; |
| 682 | |
| 683 | config2 = read_c0_config2(); |
| 684 | |
| 685 | if (config2 & MIPS_CONF2_SL) |
| 686 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; |
| 687 | |
| 688 | return config2 & MIPS_CONF_M; |
| 689 | } |
| 690 | |
| 691 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) |
| 692 | { |
| 693 | unsigned int config3; |
| 694 | |
| 695 | config3 = read_c0_config3(); |
| 696 | |
Steven J. Hill | b2ab4f0 | 2012-09-13 16:47:58 -0500 | [diff] [blame] | 697 | if (config3 & MIPS_CONF3_SM) { |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 698 | c->ases |= MIPS_ASE_SMARTMIPS; |
James Hogan | f18bdfa | 2016-05-11 13:50:52 +0100 | [diff] [blame] | 699 | c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; |
Steven J. Hill | b2ab4f0 | 2012-09-13 16:47:58 -0500 | [diff] [blame] | 700 | } |
| 701 | if (config3 & MIPS_CONF3_RXI) |
| 702 | c->options |= MIPS_CPU_RIXI; |
James Hogan | f18bdfa | 2016-05-11 13:50:52 +0100 | [diff] [blame] | 703 | if (config3 & MIPS_CONF3_CTXTC) |
| 704 | c->options |= MIPS_CPU_CTXTC; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 705 | if (config3 & MIPS_CONF3_DSP) |
| 706 | c->ases |= MIPS_ASE_DSP; |
Zubair Lutfullah Kakakhel | b5a6455 | 2016-03-29 15:50:25 +0100 | [diff] [blame] | 707 | if (config3 & MIPS_CONF3_DSP2P) { |
Steven J. Hill | ee80f7c7 | 2012-08-03 10:26:04 -0500 | [diff] [blame] | 708 | c->ases |= MIPS_ASE_DSP2P; |
Zubair Lutfullah Kakakhel | b5a6455 | 2016-03-29 15:50:25 +0100 | [diff] [blame] | 709 | if (cpu_has_mips_r6) |
| 710 | c->ases |= MIPS_ASE_DSP3; |
| 711 | } |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 712 | if (config3 & MIPS_CONF3_VINT) |
| 713 | c->options |= MIPS_CPU_VINT; |
| 714 | if (config3 & MIPS_CONF3_VEIC) |
| 715 | c->options |= MIPS_CPU_VEIC; |
James Hogan | 1282257 | 2016-04-19 09:24:59 +0100 | [diff] [blame] | 716 | if (config3 & MIPS_CONF3_LPA) |
| 717 | c->options |= MIPS_CPU_LPA; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 718 | if (config3 & MIPS_CONF3_MT) |
| 719 | c->ases |= MIPS_ASE_MIPSMT; |
| 720 | if (config3 & MIPS_CONF3_ULRI) |
| 721 | c->options |= MIPS_CPU_ULRI; |
Steven J. Hill | f8fa481 | 2012-12-07 03:51:35 +0000 | [diff] [blame] | 722 | if (config3 & MIPS_CONF3_ISA) |
| 723 | c->options |= MIPS_CPU_MICROMIPS; |
David Daney | 1e7decd | 2013-02-16 23:42:43 +0100 | [diff] [blame] | 724 | if (config3 & MIPS_CONF3_VZ) |
| 725 | c->ases |= MIPS_ASE_VZ; |
Steven J. Hill | 4a0156f | 2013-11-14 16:12:24 +0000 | [diff] [blame] | 726 | if (config3 & MIPS_CONF3_SC) |
| 727 | c->options |= MIPS_CPU_SEGMENTS; |
James Hogan | e06a154 | 2016-05-11 13:50:51 +0100 | [diff] [blame] | 728 | if (config3 & MIPS_CONF3_BI) |
| 729 | c->options |= MIPS_CPU_BADINSTR; |
| 730 | if (config3 & MIPS_CONF3_BP) |
| 731 | c->options |= MIPS_CPU_BADINSTRP; |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 732 | if (config3 & MIPS_CONF3_MSA) |
| 733 | c->ases |= MIPS_ASE_MSA; |
Paul Burton | cab25bc | 2015-09-22 12:03:37 -0700 | [diff] [blame] | 734 | if (config3 & MIPS_CONF3_PW) { |
Markos Chandras | ed4cbc8 | 2015-01-26 13:04:33 +0000 | [diff] [blame] | 735 | c->htw_seq = 0; |
Markos Chandras | 3d528b3 | 2014-07-14 12:46:13 +0100 | [diff] [blame] | 736 | c->options |= MIPS_CPU_HTW; |
Markos Chandras | ed4cbc8 | 2015-01-26 13:04:33 +0000 | [diff] [blame] | 737 | } |
James Hogan | 9b3274b | 2015-02-02 11:45:08 +0000 | [diff] [blame] | 738 | if (config3 & MIPS_CONF3_CDMM) |
| 739 | c->options |= MIPS_CPU_CDMM; |
James Hogan | aaa7be4 | 2015-07-15 16:17:44 +0100 | [diff] [blame] | 740 | if (config3 & MIPS_CONF3_SP) |
| 741 | c->options |= MIPS_CPU_SP; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 742 | |
| 743 | return config3 & MIPS_CONF_M; |
| 744 | } |
| 745 | |
| 746 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) |
| 747 | { |
| 748 | unsigned int config4; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 749 | unsigned int newcf4; |
| 750 | unsigned int mmuextdef; |
| 751 | unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; |
Paul Burton | 2db003a | 2016-05-06 14:36:24 +0100 | [diff] [blame] | 752 | unsigned long asid_mask; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 753 | |
| 754 | config4 = read_c0_config4(); |
| 755 | |
Leonid Yegoshin | 1745c1e | 2013-11-14 16:12:23 +0000 | [diff] [blame] | 756 | if (cpu_has_tlb) { |
| 757 | if (((config4 & MIPS_CONF4_IE) >> 29) == 2) |
| 758 | c->options |= MIPS_CPU_TLBINV; |
James Hogan | 43d104d | 2015-09-17 17:49:21 +0100 | [diff] [blame] | 759 | |
Markos Chandras | e87569c | 2015-07-09 10:40:52 +0100 | [diff] [blame] | 760 | /* |
James Hogan | 43d104d | 2015-09-17 17:49:21 +0100 | [diff] [blame] | 761 | * R6 has dropped the MMUExtDef field from config4. |
| 762 | * On R6 the fields always describe the FTLB, and only if it is |
| 763 | * present according to Config.MT. |
Markos Chandras | e87569c | 2015-07-09 10:40:52 +0100 | [diff] [blame] | 764 | */ |
James Hogan | 43d104d | 2015-09-17 17:49:21 +0100 | [diff] [blame] | 765 | if (!cpu_has_mips_r6) |
| 766 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; |
| 767 | else if (cpu_has_ftlb) |
Markos Chandras | e87569c | 2015-07-09 10:40:52 +0100 | [diff] [blame] | 768 | mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; |
| 769 | else |
James Hogan | 43d104d | 2015-09-17 17:49:21 +0100 | [diff] [blame] | 770 | mmuextdef = 0; |
Markos Chandras | e87569c | 2015-07-09 10:40:52 +0100 | [diff] [blame] | 771 | |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 772 | switch (mmuextdef) { |
| 773 | case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: |
| 774 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; |
| 775 | c->tlbsizevtlb = c->tlbsize; |
| 776 | break; |
| 777 | case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: |
| 778 | c->tlbsizevtlb += |
| 779 | ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> |
| 780 | MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; |
| 781 | c->tlbsize = c->tlbsizevtlb; |
| 782 | ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; |
| 783 | /* fall through */ |
| 784 | case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: |
Markos Chandras | 97f4ad2 | 2014-08-29 09:37:26 +0100 | [diff] [blame] | 785 | if (mips_ftlb_disabled) |
| 786 | break; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 787 | newcf4 = (config4 & ~ftlb_page) | |
| 788 | (page_size_ftlb(mmuextdef) << |
| 789 | MIPS_CONF4_FTLBPAGESIZE_SHIFT); |
| 790 | write_c0_config4(newcf4); |
| 791 | back_to_back_c0_hazard(); |
| 792 | config4 = read_c0_config4(); |
| 793 | if (config4 != newcf4) { |
| 794 | pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", |
| 795 | PAGE_SIZE, config4); |
| 796 | /* Switch FTLB off */ |
| 797 | set_ftlb_enable(c, 0); |
Paul Burton | ebd0e0f | 2016-08-19 18:18:27 +0100 | [diff] [blame] | 798 | mips_ftlb_disabled = 1; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 799 | break; |
| 800 | } |
| 801 | c->tlbsizeftlbsets = 1 << |
| 802 | ((config4 & MIPS_CONF4_FTLBSETS) >> |
| 803 | MIPS_CONF4_FTLBSETS_SHIFT); |
| 804 | c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> |
| 805 | MIPS_CONF4_FTLBWAYS_SHIFT) + 2; |
| 806 | c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; |
Markos Chandras | 97f4ad2 | 2014-08-29 09:37:26 +0100 | [diff] [blame] | 807 | mips_has_ftlb_configured = 1; |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 808 | break; |
| 809 | } |
Leonid Yegoshin | 1745c1e | 2013-11-14 16:12:23 +0000 | [diff] [blame] | 810 | } |
| 811 | |
James Hogan | 9e575f7 | 2016-05-11 15:50:27 +0100 | [diff] [blame] | 812 | c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) |
| 813 | >> MIPS_CONF4_KSCREXIST_SHIFT; |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 814 | |
Paul Burton | 2db003a | 2016-05-06 14:36:24 +0100 | [diff] [blame] | 815 | asid_mask = MIPS_ENTRYHI_ASID; |
| 816 | if (config4 & MIPS_CONF4_AE) |
| 817 | asid_mask |= MIPS_ENTRYHI_ASIDX; |
| 818 | set_cpu_asid_mask(c, asid_mask); |
| 819 | |
| 820 | /* |
| 821 | * Warn if the computed ASID mask doesn't match the mask the kernel |
| 822 | * is built for. This may indicate either a serious problem or an |
| 823 | * easy optimisation opportunity, but either way should be addressed. |
| 824 | */ |
| 825 | WARN_ON(asid_mask != cpu_asid_mask(c)); |
| 826 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 827 | return config4 & MIPS_CONF_M; |
| 828 | } |
| 829 | |
Ralf Baechle | 8b8a7634 | 2013-09-19 11:15:49 +0200 | [diff] [blame] | 830 | static inline unsigned int decode_config5(struct cpuinfo_mips *c) |
| 831 | { |
| 832 | unsigned int config5; |
| 833 | |
| 834 | config5 = read_c0_config5(); |
Paul Burton | d175ed2 | 2014-09-11 08:30:19 +0100 | [diff] [blame] | 835 | config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); |
Ralf Baechle | 8b8a7634 | 2013-09-19 11:15:49 +0200 | [diff] [blame] | 836 | write_c0_config5(config5); |
| 837 | |
Markos Chandras | 4901674 | 2014-01-09 16:04:51 +0000 | [diff] [blame] | 838 | if (config5 & MIPS_CONF5_EVA) |
| 839 | c->options |= MIPS_CPU_EVA; |
Paul Burton | 1f6c52f | 2014-07-14 10:32:14 +0100 | [diff] [blame] | 840 | if (config5 & MIPS_CONF5_MRP) |
| 841 | c->options |= MIPS_CPU_MAAR; |
Markos Chandras | 5aed9da | 2014-12-02 09:46:19 +0000 | [diff] [blame] | 842 | if (config5 & MIPS_CONF5_LLB) |
| 843 | c->options |= MIPS_CPU_RW_LLB; |
Steven J. Hill | c5b3678 | 2015-02-26 18:16:38 -0600 | [diff] [blame] | 844 | if (config5 & MIPS_CONF5_MVH) |
James Hogan | 0f2d988 | 2016-05-18 00:08:49 +0100 | [diff] [blame] | 845 | c->options |= MIPS_CPU_MVH; |
Paul Burton | f270d88 | 2016-02-03 03:15:21 +0000 | [diff] [blame] | 846 | if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) |
| 847 | c->options |= MIPS_CPU_VP; |
Maciej W. Rozycki | 8d1630f | 2017-05-23 13:37:05 +0100 | [diff] [blame] | 848 | if (config5 & MIPS_CONF5_CA2) |
| 849 | c->ases |= MIPS_ASE_MIPS16E2; |
Markos Chandras | 4901674 | 2014-01-09 16:04:51 +0000 | [diff] [blame] | 850 | |
Ralf Baechle | 8b8a7634 | 2013-09-19 11:15:49 +0200 | [diff] [blame] | 851 | return config5 & MIPS_CONF_M; |
| 852 | } |
| 853 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 854 | static void decode_configs(struct cpuinfo_mips *c) |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 855 | { |
| 856 | int ok; |
| 857 | |
| 858 | /* MIPS32 or MIPS64 compliant CPU. */ |
| 859 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | |
| 860 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; |
| 861 | |
| 862 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; |
| 863 | |
Markos Chandras | 97f4ad2 | 2014-08-29 09:37:26 +0100 | [diff] [blame] | 864 | /* Enable FTLB if present and not disabled */ |
Paul Burton | ebd0e0f | 2016-08-19 18:18:27 +0100 | [diff] [blame] | 865 | set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 866 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 867 | ok = decode_config0(c); /* Read Config registers. */ |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 868 | BUG_ON(!ok); /* Arch spec violation! */ |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 869 | if (ok) |
| 870 | ok = decode_config1(c); |
| 871 | if (ok) |
| 872 | ok = decode_config2(c); |
| 873 | if (ok) |
| 874 | ok = decode_config3(c); |
| 875 | if (ok) |
| 876 | ok = decode_config4(c); |
Ralf Baechle | 8b8a7634 | 2013-09-19 11:15:49 +0200 | [diff] [blame] | 877 | if (ok) |
| 878 | ok = decode_config5(c); |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 879 | |
James Hogan | 37fb60f | 2016-05-11 13:50:50 +0100 | [diff] [blame] | 880 | /* Probe the EBase.WG bit */ |
| 881 | if (cpu_has_mips_r2_r6) { |
| 882 | u64 ebase; |
| 883 | unsigned int status; |
| 884 | |
| 885 | /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ |
| 886 | ebase = cpu_has_mips64r6 ? read_c0_ebase_64() |
| 887 | : (s32)read_c0_ebase(); |
| 888 | if (ebase & MIPS_EBASE_WG) { |
| 889 | /* WG bit already set, we can avoid the clumsy probe */ |
| 890 | c->options |= MIPS_CPU_EBASE_WG; |
| 891 | } else { |
| 892 | /* Its UNDEFINED to change EBase while BEV=0 */ |
| 893 | status = read_c0_status(); |
| 894 | write_c0_status(status | ST0_BEV); |
| 895 | irq_enable_hazard(); |
| 896 | /* |
| 897 | * On pre-r6 cores, this may well clobber the upper bits |
| 898 | * of EBase. This is hard to avoid without potentially |
| 899 | * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. |
| 900 | */ |
| 901 | if (cpu_has_mips64r6) |
| 902 | write_c0_ebase_64(ebase | MIPS_EBASE_WG); |
| 903 | else |
| 904 | write_c0_ebase(ebase | MIPS_EBASE_WG); |
| 905 | back_to_back_c0_hazard(); |
| 906 | /* Restore BEV */ |
| 907 | write_c0_status(status); |
| 908 | if (read_c0_ebase() & MIPS_EBASE_WG) { |
| 909 | c->options |= MIPS_CPU_EBASE_WG; |
| 910 | write_c0_ebase(ebase); |
| 911 | } |
| 912 | } |
| 913 | } |
| 914 | |
Paul Burton | ebd0e0f | 2016-08-19 18:18:27 +0100 | [diff] [blame] | 915 | /* configure the FTLB write probability */ |
| 916 | set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); |
| 917 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 918 | mips_probe_watch_registers(c); |
| 919 | |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 920 | #ifndef CONFIG_MIPS_CPS |
Leonid Yegoshin | 8b8aa63 | 2014-11-13 13:51:51 +0000 | [diff] [blame] | 921 | if (cpu_has_mips_r2_r6) { |
Paul Burton | f875a832 | 2017-08-12 19:49:35 -0700 | [diff] [blame] | 922 | unsigned int core; |
| 923 | |
| 924 | core = get_ebase_cpunum(); |
Paul Burton | 30ee615 | 2014-03-27 10:57:30 +0000 | [diff] [blame] | 925 | if (cpu_has_mipsmt) |
Paul Burton | f875a832 | 2017-08-12 19:49:35 -0700 | [diff] [blame] | 926 | core >>= fls(core_nvpes()) - 1; |
| 927 | cpu_set_core(c, core); |
Paul Burton | 30ee615 | 2014-03-27 10:57:30 +0000 | [diff] [blame] | 928 | } |
Paul Burton | 0ee958e | 2014-01-15 10:31:53 +0000 | [diff] [blame] | 929 | #endif |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 930 | } |
| 931 | |
James Hogan | 6ad816e | 2016-05-11 15:50:30 +0100 | [diff] [blame] | 932 | /* |
| 933 | * Probe for certain guest capabilities by writing config bits and reading back. |
| 934 | * Finally write back the original value. |
| 935 | */ |
| 936 | #define probe_gc0_config(name, maxconf, bits) \ |
| 937 | do { \ |
| 938 | unsigned int tmp; \ |
| 939 | tmp = read_gc0_##name(); \ |
| 940 | write_gc0_##name(tmp | (bits)); \ |
| 941 | back_to_back_c0_hazard(); \ |
| 942 | maxconf = read_gc0_##name(); \ |
| 943 | write_gc0_##name(tmp); \ |
| 944 | } while (0) |
| 945 | |
| 946 | /* |
| 947 | * Probe for dynamic guest capabilities by changing certain config bits and |
| 948 | * reading back to see if they change. Finally write back the original value. |
| 949 | */ |
| 950 | #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ |
| 951 | do { \ |
| 952 | maxconf = read_gc0_##name(); \ |
| 953 | write_gc0_##name(maxconf ^ (bits)); \ |
| 954 | back_to_back_c0_hazard(); \ |
| 955 | dynconf = maxconf ^ read_gc0_##name(); \ |
| 956 | write_gc0_##name(maxconf); \ |
| 957 | maxconf |= dynconf; \ |
| 958 | } while (0) |
| 959 | |
| 960 | static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) |
| 961 | { |
| 962 | unsigned int config0; |
| 963 | |
| 964 | probe_gc0_config(config, config0, MIPS_CONF_M); |
| 965 | |
| 966 | if (config0 & MIPS_CONF_M) |
| 967 | c->guest.conf |= BIT(1); |
| 968 | return config0 & MIPS_CONF_M; |
| 969 | } |
| 970 | |
| 971 | static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) |
| 972 | { |
| 973 | unsigned int config1, config1_dyn; |
| 974 | |
| 975 | probe_gc0_config_dyn(config1, config1, config1_dyn, |
| 976 | MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | |
| 977 | MIPS_CONF1_FP); |
| 978 | |
| 979 | if (config1 & MIPS_CONF1_FP) |
| 980 | c->guest.options |= MIPS_CPU_FPU; |
| 981 | if (config1_dyn & MIPS_CONF1_FP) |
| 982 | c->guest.options_dyn |= MIPS_CPU_FPU; |
| 983 | |
| 984 | if (config1 & MIPS_CONF1_WR) |
| 985 | c->guest.options |= MIPS_CPU_WATCH; |
| 986 | if (config1_dyn & MIPS_CONF1_WR) |
| 987 | c->guest.options_dyn |= MIPS_CPU_WATCH; |
| 988 | |
| 989 | if (config1 & MIPS_CONF1_PC) |
| 990 | c->guest.options |= MIPS_CPU_PERF; |
| 991 | if (config1_dyn & MIPS_CONF1_PC) |
| 992 | c->guest.options_dyn |= MIPS_CPU_PERF; |
| 993 | |
| 994 | if (config1 & MIPS_CONF_M) |
| 995 | c->guest.conf |= BIT(2); |
| 996 | return config1 & MIPS_CONF_M; |
| 997 | } |
| 998 | |
| 999 | static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) |
| 1000 | { |
| 1001 | unsigned int config2; |
| 1002 | |
| 1003 | probe_gc0_config(config2, config2, MIPS_CONF_M); |
| 1004 | |
| 1005 | if (config2 & MIPS_CONF_M) |
| 1006 | c->guest.conf |= BIT(3); |
| 1007 | return config2 & MIPS_CONF_M; |
| 1008 | } |
| 1009 | |
| 1010 | static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) |
| 1011 | { |
| 1012 | unsigned int config3, config3_dyn; |
| 1013 | |
| 1014 | probe_gc0_config_dyn(config3, config3, config3_dyn, |
James Hogan | a7c7ad6 | 2017-03-14 10:15:10 +0000 | [diff] [blame] | 1015 | MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI | |
| 1016 | MIPS_CONF3_CTXTC); |
James Hogan | 6ad816e | 2016-05-11 15:50:30 +0100 | [diff] [blame] | 1017 | |
| 1018 | if (config3 & MIPS_CONF3_CTXTC) |
| 1019 | c->guest.options |= MIPS_CPU_CTXTC; |
| 1020 | if (config3_dyn & MIPS_CONF3_CTXTC) |
| 1021 | c->guest.options_dyn |= MIPS_CPU_CTXTC; |
| 1022 | |
| 1023 | if (config3 & MIPS_CONF3_PW) |
| 1024 | c->guest.options |= MIPS_CPU_HTW; |
| 1025 | |
James Hogan | a7c7ad6 | 2017-03-14 10:15:10 +0000 | [diff] [blame] | 1026 | if (config3 & MIPS_CONF3_ULRI) |
| 1027 | c->guest.options |= MIPS_CPU_ULRI; |
| 1028 | |
James Hogan | 6ad816e | 2016-05-11 15:50:30 +0100 | [diff] [blame] | 1029 | if (config3 & MIPS_CONF3_SC) |
| 1030 | c->guest.options |= MIPS_CPU_SEGMENTS; |
| 1031 | |
| 1032 | if (config3 & MIPS_CONF3_BI) |
| 1033 | c->guest.options |= MIPS_CPU_BADINSTR; |
| 1034 | if (config3 & MIPS_CONF3_BP) |
| 1035 | c->guest.options |= MIPS_CPU_BADINSTRP; |
| 1036 | |
| 1037 | if (config3 & MIPS_CONF3_MSA) |
| 1038 | c->guest.ases |= MIPS_ASE_MSA; |
| 1039 | if (config3_dyn & MIPS_CONF3_MSA) |
| 1040 | c->guest.ases_dyn |= MIPS_ASE_MSA; |
| 1041 | |
| 1042 | if (config3 & MIPS_CONF_M) |
| 1043 | c->guest.conf |= BIT(4); |
| 1044 | return config3 & MIPS_CONF_M; |
| 1045 | } |
| 1046 | |
| 1047 | static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) |
| 1048 | { |
| 1049 | unsigned int config4; |
| 1050 | |
| 1051 | probe_gc0_config(config4, config4, |
| 1052 | MIPS_CONF_M | MIPS_CONF4_KSCREXIST); |
| 1053 | |
| 1054 | c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) |
| 1055 | >> MIPS_CONF4_KSCREXIST_SHIFT; |
| 1056 | |
| 1057 | if (config4 & MIPS_CONF_M) |
| 1058 | c->guest.conf |= BIT(5); |
| 1059 | return config4 & MIPS_CONF_M; |
| 1060 | } |
| 1061 | |
| 1062 | static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) |
| 1063 | { |
| 1064 | unsigned int config5, config5_dyn; |
| 1065 | |
| 1066 | probe_gc0_config_dyn(config5, config5, config5_dyn, |
James Hogan | a929bdc | 2017-03-14 10:15:11 +0000 | [diff] [blame] | 1067 | MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP); |
James Hogan | 6ad816e | 2016-05-11 15:50:30 +0100 | [diff] [blame] | 1068 | |
| 1069 | if (config5 & MIPS_CONF5_MRP) |
| 1070 | c->guest.options |= MIPS_CPU_MAAR; |
| 1071 | if (config5_dyn & MIPS_CONF5_MRP) |
| 1072 | c->guest.options_dyn |= MIPS_CPU_MAAR; |
| 1073 | |
| 1074 | if (config5 & MIPS_CONF5_LLB) |
| 1075 | c->guest.options |= MIPS_CPU_RW_LLB; |
| 1076 | |
James Hogan | a929bdc | 2017-03-14 10:15:11 +0000 | [diff] [blame] | 1077 | if (config5 & MIPS_CONF5_MVH) |
| 1078 | c->guest.options |= MIPS_CPU_MVH; |
| 1079 | |
James Hogan | 6ad816e | 2016-05-11 15:50:30 +0100 | [diff] [blame] | 1080 | if (config5 & MIPS_CONF_M) |
| 1081 | c->guest.conf |= BIT(6); |
| 1082 | return config5 & MIPS_CONF_M; |
| 1083 | } |
| 1084 | |
| 1085 | static inline void decode_guest_configs(struct cpuinfo_mips *c) |
| 1086 | { |
| 1087 | unsigned int ok; |
| 1088 | |
| 1089 | ok = decode_guest_config0(c); |
| 1090 | if (ok) |
| 1091 | ok = decode_guest_config1(c); |
| 1092 | if (ok) |
| 1093 | ok = decode_guest_config2(c); |
| 1094 | if (ok) |
| 1095 | ok = decode_guest_config3(c); |
| 1096 | if (ok) |
| 1097 | ok = decode_guest_config4(c); |
| 1098 | if (ok) |
| 1099 | decode_guest_config5(c); |
| 1100 | } |
| 1101 | |
| 1102 | static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) |
| 1103 | { |
| 1104 | unsigned int guestctl0, temp; |
| 1105 | |
| 1106 | guestctl0 = read_c0_guestctl0(); |
| 1107 | |
| 1108 | if (guestctl0 & MIPS_GCTL0_G0E) |
| 1109 | c->options |= MIPS_CPU_GUESTCTL0EXT; |
| 1110 | if (guestctl0 & MIPS_GCTL0_G1) |
| 1111 | c->options |= MIPS_CPU_GUESTCTL1; |
| 1112 | if (guestctl0 & MIPS_GCTL0_G2) |
| 1113 | c->options |= MIPS_CPU_GUESTCTL2; |
| 1114 | if (!(guestctl0 & MIPS_GCTL0_RAD)) { |
| 1115 | c->options |= MIPS_CPU_GUESTID; |
| 1116 | |
| 1117 | /* |
| 1118 | * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 |
| 1119 | * first, otherwise all data accesses will be fully virtualised |
| 1120 | * as if they were performed by guest mode. |
| 1121 | */ |
| 1122 | write_c0_guestctl1(0); |
| 1123 | tlbw_use_hazard(); |
| 1124 | |
| 1125 | write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); |
| 1126 | back_to_back_c0_hazard(); |
| 1127 | temp = read_c0_guestctl0(); |
| 1128 | |
| 1129 | if (temp & MIPS_GCTL0_DRG) { |
| 1130 | write_c0_guestctl0(guestctl0); |
| 1131 | c->options |= MIPS_CPU_DRG; |
| 1132 | } |
| 1133 | } |
| 1134 | } |
| 1135 | |
| 1136 | static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) |
| 1137 | { |
| 1138 | if (cpu_has_guestid) { |
| 1139 | /* determine the number of bits of GuestID available */ |
| 1140 | write_c0_guestctl1(MIPS_GCTL1_ID); |
| 1141 | back_to_back_c0_hazard(); |
| 1142 | c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) |
| 1143 | >> MIPS_GCTL1_ID_SHIFT; |
| 1144 | write_c0_guestctl1(0); |
| 1145 | } |
| 1146 | } |
| 1147 | |
| 1148 | static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) |
| 1149 | { |
| 1150 | /* determine the number of bits of GTOffset available */ |
| 1151 | write_c0_gtoffset(0xffffffff); |
| 1152 | back_to_back_c0_hazard(); |
| 1153 | c->gtoffset_mask = read_c0_gtoffset(); |
| 1154 | write_c0_gtoffset(0); |
| 1155 | } |
| 1156 | |
| 1157 | static inline void cpu_probe_vz(struct cpuinfo_mips *c) |
| 1158 | { |
| 1159 | cpu_probe_guestctl0(c); |
| 1160 | if (cpu_has_guestctl1) |
| 1161 | cpu_probe_guestctl1(c); |
| 1162 | |
| 1163 | cpu_probe_gtoffset(c); |
| 1164 | |
| 1165 | decode_guest_configs(c); |
| 1166 | } |
| 1167 | |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 1168 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1169 | | MIPS_CPU_COUNTER) |
| 1170 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1171 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1172 | { |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1173 | switch (c->processor_id & PRID_IMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1174 | case PRID_IMP_R2000: |
| 1175 | c->cputype = CPU_R2000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1176 | __cpu_name[cpu] = "R2000"; |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1177 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 1178 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1179 | MIPS_CPU_NOFPUEX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1180 | if (__cpu_has_fpu()) |
| 1181 | c->options |= MIPS_CPU_FPU; |
| 1182 | c->tlbsize = 64; |
| 1183 | break; |
| 1184 | case PRID_IMP_R3000: |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1185 | if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1186 | if (cpu_has_confreg()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1187 | c->cputype = CPU_R3081E; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1188 | __cpu_name[cpu] = "R3081"; |
| 1189 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1190 | c->cputype = CPU_R3000A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1191 | __cpu_name[cpu] = "R3000A"; |
| 1192 | } |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1193 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1194 | c->cputype = CPU_R3000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1195 | __cpu_name[cpu] = "R3000"; |
| 1196 | } |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1197 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 1198 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1199 | MIPS_CPU_NOFPUEX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1200 | if (__cpu_has_fpu()) |
| 1201 | c->options |= MIPS_CPU_FPU; |
| 1202 | c->tlbsize = 64; |
| 1203 | break; |
| 1204 | case PRID_IMP_R4000: |
| 1205 | if (read_c0_config() & CONF_SC) { |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1206 | if ((c->processor_id & PRID_REV_MASK) >= |
| 1207 | PRID_REV_R4400) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1208 | c->cputype = CPU_R4400PC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1209 | __cpu_name[cpu] = "R4400PC"; |
| 1210 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1211 | c->cputype = CPU_R4000PC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1212 | __cpu_name[cpu] = "R4000PC"; |
| 1213 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1214 | } else { |
Maciej W. Rozycki | 7f177a5 | 2013-09-23 14:01:53 +0100 | [diff] [blame] | 1215 | int cca = read_c0_config() & CONF_CM_CMASK; |
| 1216 | int mc; |
| 1217 | |
| 1218 | /* |
| 1219 | * SC and MC versions can't be reliably told apart, |
| 1220 | * but only the latter support coherent caching |
| 1221 | * modes so assume the firmware has set the KSEG0 |
| 1222 | * coherency attribute reasonably (if uncached, we |
| 1223 | * assume SC). |
| 1224 | */ |
| 1225 | switch (cca) { |
| 1226 | case CONF_CM_CACHABLE_CE: |
| 1227 | case CONF_CM_CACHABLE_COW: |
| 1228 | case CONF_CM_CACHABLE_CUW: |
| 1229 | mc = 1; |
| 1230 | break; |
| 1231 | default: |
| 1232 | mc = 0; |
| 1233 | break; |
| 1234 | } |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1235 | if ((c->processor_id & PRID_REV_MASK) >= |
| 1236 | PRID_REV_R4400) { |
Maciej W. Rozycki | 7f177a5 | 2013-09-23 14:01:53 +0100 | [diff] [blame] | 1237 | c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; |
| 1238 | __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1239 | } else { |
Maciej W. Rozycki | 7f177a5 | 2013-09-23 14:01:53 +0100 | [diff] [blame] | 1240 | c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; |
| 1241 | __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1242 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1243 | } |
| 1244 | |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1245 | set_isa(c, MIPS_CPU_ISA_III); |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1246 | c->fpu_msk31 |= FPU_CSR_CONDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1247 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1248 | MIPS_CPU_WATCH | MIPS_CPU_VCE | |
| 1249 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1250 | c->tlbsize = 48; |
| 1251 | break; |
| 1252 | case PRID_IMP_VR41XX: |
Yoichi Yuasa | 9f91e50 | 2013-02-21 15:38:19 +0900 | [diff] [blame] | 1253 | set_isa(c, MIPS_CPU_ISA_III); |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1254 | c->fpu_msk31 |= FPU_CSR_CONDX; |
Yoichi Yuasa | 9f91e50 | 2013-02-21 15:38:19 +0900 | [diff] [blame] | 1255 | c->options = R4K_OPTS; |
| 1256 | c->tlbsize = 32; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1257 | switch (c->processor_id & 0xf0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1258 | case PRID_REV_VR4111: |
| 1259 | c->cputype = CPU_VR4111; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1260 | __cpu_name[cpu] = "NEC VR4111"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1261 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1262 | case PRID_REV_VR4121: |
| 1263 | c->cputype = CPU_VR4121; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1264 | __cpu_name[cpu] = "NEC VR4121"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1265 | break; |
| 1266 | case PRID_REV_VR4122: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1267 | if ((c->processor_id & 0xf) < 0x3) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1268 | c->cputype = CPU_VR4122; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1269 | __cpu_name[cpu] = "NEC VR4122"; |
| 1270 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1271 | c->cputype = CPU_VR4181A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1272 | __cpu_name[cpu] = "NEC VR4181A"; |
| 1273 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1274 | break; |
| 1275 | case PRID_REV_VR4130: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1276 | if ((c->processor_id & 0xf) < 0x4) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1277 | c->cputype = CPU_VR4131; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1278 | __cpu_name[cpu] = "NEC VR4131"; |
| 1279 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1280 | c->cputype = CPU_VR4133; |
Yoichi Yuasa | 9f91e50 | 2013-02-21 15:38:19 +0900 | [diff] [blame] | 1281 | c->options |= MIPS_CPU_LLSC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1282 | __cpu_name[cpu] = "NEC VR4133"; |
| 1283 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1284 | break; |
| 1285 | default: |
| 1286 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); |
| 1287 | c->cputype = CPU_VR41XX; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1288 | __cpu_name[cpu] = "NEC Vr41xx"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1289 | break; |
| 1290 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1291 | break; |
| 1292 | case PRID_IMP_R4300: |
| 1293 | c->cputype = CPU_R4300; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1294 | __cpu_name[cpu] = "R4300"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1295 | set_isa(c, MIPS_CPU_ISA_III); |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1296 | c->fpu_msk31 |= FPU_CSR_CONDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1297 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1298 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1299 | c->tlbsize = 32; |
| 1300 | break; |
| 1301 | case PRID_IMP_R4600: |
| 1302 | c->cputype = CPU_R4600; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1303 | __cpu_name[cpu] = "R4600"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1304 | set_isa(c, MIPS_CPU_ISA_III); |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1305 | c->fpu_msk31 |= FPU_CSR_CONDX; |
Thiemo Seufer | 075e750 | 2005-07-27 21:48:12 +0000 | [diff] [blame] | 1306 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 1307 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1308 | c->tlbsize = 48; |
| 1309 | break; |
| 1310 | #if 0 |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1311 | case PRID_IMP_R4650: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1312 | /* |
| 1313 | * This processor doesn't have an MMU, so it's not |
| 1314 | * "real easy" to run Linux on it. It is left purely |
| 1315 | * for documentation. Commented out because it shares |
| 1316 | * it's c0_prid id number with the TX3900. |
| 1317 | */ |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 1318 | c->cputype = CPU_R4650; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1319 | __cpu_name[cpu] = "R4650"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1320 | set_isa(c, MIPS_CPU_ISA_III); |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1321 | c->fpu_msk31 |= FPU_CSR_CONDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1322 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1323 | c->tlbsize = 48; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1324 | break; |
| 1325 | #endif |
| 1326 | case PRID_IMP_TX39: |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1327 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 1328 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1329 | |
| 1330 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { |
| 1331 | c->cputype = CPU_TX3927; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1332 | __cpu_name[cpu] = "TX3927"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1333 | c->tlbsize = 64; |
| 1334 | } else { |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1335 | switch (c->processor_id & PRID_REV_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1336 | case PRID_REV_TX3912: |
| 1337 | c->cputype = CPU_TX3912; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1338 | __cpu_name[cpu] = "TX3912"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1339 | c->tlbsize = 32; |
| 1340 | break; |
| 1341 | case PRID_REV_TX3922: |
| 1342 | c->cputype = CPU_TX3922; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1343 | __cpu_name[cpu] = "TX3922"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1344 | c->tlbsize = 64; |
| 1345 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1346 | } |
| 1347 | } |
| 1348 | break; |
| 1349 | case PRID_IMP_R4700: |
| 1350 | c->cputype = CPU_R4700; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1351 | __cpu_name[cpu] = "R4700"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1352 | set_isa(c, MIPS_CPU_ISA_III); |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1353 | c->fpu_msk31 |= FPU_CSR_CONDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1354 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1355 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1356 | c->tlbsize = 48; |
| 1357 | break; |
| 1358 | case PRID_IMP_TX49: |
| 1359 | c->cputype = CPU_TX49XX; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1360 | __cpu_name[cpu] = "R49XX"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1361 | set_isa(c, MIPS_CPU_ISA_III); |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1362 | c->fpu_msk31 |= FPU_CSR_CONDX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1363 | c->options = R4K_OPTS | MIPS_CPU_LLSC; |
| 1364 | if (!(c->processor_id & 0x08)) |
| 1365 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; |
| 1366 | c->tlbsize = 48; |
| 1367 | break; |
| 1368 | case PRID_IMP_R5000: |
| 1369 | c->cputype = CPU_R5000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1370 | __cpu_name[cpu] = "R5000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1371 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1372 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1373 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1374 | c->tlbsize = 48; |
| 1375 | break; |
| 1376 | case PRID_IMP_R5432: |
| 1377 | c->cputype = CPU_R5432; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1378 | __cpu_name[cpu] = "R5432"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1379 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1380 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1381 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1382 | c->tlbsize = 48; |
| 1383 | break; |
| 1384 | case PRID_IMP_R5500: |
| 1385 | c->cputype = CPU_R5500; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1386 | __cpu_name[cpu] = "R5500"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1387 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1388 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1389 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1390 | c->tlbsize = 48; |
| 1391 | break; |
| 1392 | case PRID_IMP_NEVADA: |
| 1393 | c->cputype = CPU_NEVADA; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1394 | __cpu_name[cpu] = "Nevada"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1395 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1396 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1397 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1398 | c->tlbsize = 48; |
| 1399 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1400 | case PRID_IMP_RM7000: |
| 1401 | c->cputype = CPU_RM7000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1402 | __cpu_name[cpu] = "RM7000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1403 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1404 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1405 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1406 | /* |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1407 | * Undocumented RM7000: Bit 29 in the info register of |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1408 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 |
| 1409 | * entries. |
| 1410 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1411 | * 29 1 => 64 entry JTLB |
| 1412 | * 0 => 48 entry JTLB |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1413 | */ |
| 1414 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; |
| 1415 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1416 | case PRID_IMP_R8000: |
| 1417 | c->cputype = CPU_R8000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1418 | __cpu_name[cpu] = "RM8000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1419 | set_isa(c, MIPS_CPU_ISA_IV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1420 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1421 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 1422 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1423 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ |
| 1424 | break; |
| 1425 | case PRID_IMP_R10000: |
| 1426 | c->cputype = CPU_R10000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1427 | __cpu_name[cpu] = "R10000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1428 | set_isa(c, MIPS_CPU_ISA_IV); |
Ralf Baechle | 8b36612 | 2005-11-22 17:53:59 +0000 | [diff] [blame] | 1429 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1430 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1431 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1432 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1433 | c->tlbsize = 64; |
| 1434 | break; |
| 1435 | case PRID_IMP_R12000: |
| 1436 | c->cputype = CPU_R12000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1437 | __cpu_name[cpu] = "R12000"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1438 | set_isa(c, MIPS_CPU_ISA_IV); |
Ralf Baechle | 8b36612 | 2005-11-22 17:53:59 +0000 | [diff] [blame] | 1439 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1440 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1441 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
Joshua Kinard | 8d5ded1 | 2015-06-02 18:21:33 -0400 | [diff] [blame] | 1442 | MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1443 | c->tlbsize = 64; |
| 1444 | break; |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 1445 | case PRID_IMP_R14000: |
Joshua Kinard | 3057739 | 2015-01-21 07:59:45 -0500 | [diff] [blame] | 1446 | if (((c->processor_id >> 4) & 0x0f) > 2) { |
| 1447 | c->cputype = CPU_R16000; |
| 1448 | __cpu_name[cpu] = "R16000"; |
| 1449 | } else { |
| 1450 | c->cputype = CPU_R14000; |
| 1451 | __cpu_name[cpu] = "R14000"; |
| 1452 | } |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1453 | set_isa(c, MIPS_CPU_ISA_IV); |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 1454 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
Steven J. Hill | 03751e7 | 2012-05-10 23:21:18 -0500 | [diff] [blame] | 1455 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 1456 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
Joshua Kinard | 8d5ded1 | 2015-06-02 18:21:33 -0400 | [diff] [blame] | 1457 | MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 1458 | c->tlbsize = 64; |
| 1459 | break; |
Huacai Chen | 2685919 | 2014-02-16 16:01:18 +0800 | [diff] [blame] | 1460 | case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 1461 | switch (c->processor_id & PRID_REV_MASK) { |
| 1462 | case PRID_REV_LOONGSON2E: |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1463 | c->cputype = CPU_LOONGSON2; |
| 1464 | __cpu_name[cpu] = "ICT Loongson-2"; |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 1465 | set_elf_platform(cpu, "loongson2e"); |
Huacai Chen | 7352c8b | 2014-11-04 14:13:23 +0800 | [diff] [blame] | 1466 | set_isa(c, MIPS_CPU_ISA_III); |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1467 | c->fpu_msk31 |= FPU_CSR_CONDX; |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 1468 | break; |
| 1469 | case PRID_REV_LOONGSON2F: |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1470 | c->cputype = CPU_LOONGSON2; |
| 1471 | __cpu_name[cpu] = "ICT Loongson-2"; |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 1472 | set_elf_platform(cpu, "loongson2f"); |
Huacai Chen | 7352c8b | 2014-11-04 14:13:23 +0800 | [diff] [blame] | 1473 | set_isa(c, MIPS_CPU_ISA_III); |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1474 | c->fpu_msk31 |= FPU_CSR_CONDX; |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 1475 | break; |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 1476 | case PRID_REV_LOONGSON3A_R1: |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1477 | c->cputype = CPU_LOONGSON3; |
| 1478 | __cpu_name[cpu] = "ICT Loongson-3"; |
| 1479 | set_elf_platform(cpu, "loongson3a"); |
Huacai Chen | 7352c8b | 2014-11-04 14:13:23 +0800 | [diff] [blame] | 1480 | set_isa(c, MIPS_CPU_ISA_M64R1); |
Huacai Chen | c579d31 | 2014-03-21 18:44:00 +0800 | [diff] [blame] | 1481 | break; |
Huacai Chen | e7841be | 2014-06-26 11:41:30 +0800 | [diff] [blame] | 1482 | case PRID_REV_LOONGSON3B_R1: |
| 1483 | case PRID_REV_LOONGSON3B_R2: |
| 1484 | c->cputype = CPU_LOONGSON3; |
| 1485 | __cpu_name[cpu] = "ICT Loongson-3"; |
| 1486 | set_elf_platform(cpu, "loongson3b"); |
Huacai Chen | 7352c8b | 2014-11-04 14:13:23 +0800 | [diff] [blame] | 1487 | set_isa(c, MIPS_CPU_ISA_M64R1); |
Huacai Chen | e7841be | 2014-06-26 11:41:30 +0800 | [diff] [blame] | 1488 | break; |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 1489 | } |
| 1490 | |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1491 | c->options = R4K_OPTS | |
| 1492 | MIPS_CPU_FPU | MIPS_CPU_LLSC | |
| 1493 | MIPS_CPU_32FPR; |
| 1494 | c->tlbsize = 64; |
Huacai Chen | cc94ea3 | 2014-11-04 14:13:22 +0800 | [diff] [blame] | 1495 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 1496 | break; |
Huacai Chen | 2685919 | 2014-02-16 16:01:18 +0800 | [diff] [blame] | 1497 | case PRID_IMP_LOONGSON_32: /* Loongson-1 */ |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 1498 | decode_configs(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1499 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 1500 | c->cputype = CPU_LOONGSON1; |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 1501 | |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 1502 | switch (c->processor_id & PRID_REV_MASK) { |
| 1503 | case PRID_REV_LOONGSON1B: |
| 1504 | __cpu_name[cpu] = "Loongson 1B"; |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 1505 | break; |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 1506 | } |
Kelvin Cheung | 2fa3639 | 2012-06-20 20:05:32 +0100 | [diff] [blame] | 1507 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1508 | break; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1509 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1510 | } |
| 1511 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1512 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1513 | { |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1514 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1515 | switch (c->processor_id & PRID_IMP_MASK) { |
Leonid Yegoshin | b2498af | 2014-11-24 12:59:44 +0000 | [diff] [blame] | 1516 | case PRID_IMP_QEMU_GENERIC: |
| 1517 | c->writecombine = _CACHE_UNCACHED; |
| 1518 | c->cputype = CPU_QEMU_GENERIC; |
| 1519 | __cpu_name[cpu] = "MIPS GENERIC QEMU"; |
| 1520 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1521 | case PRID_IMP_4KC: |
| 1522 | c->cputype = CPU_4KC; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1523 | c->writecombine = _CACHE_UNCACHED; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1524 | __cpu_name[cpu] = "MIPS 4Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1525 | break; |
| 1526 | case PRID_IMP_4KEC: |
Ralf Baechle | 2b07bd0 | 2005-04-08 20:36:05 +0000 | [diff] [blame] | 1527 | case PRID_IMP_4KECR2: |
| 1528 | c->cputype = CPU_4KEC; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1529 | c->writecombine = _CACHE_UNCACHED; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1530 | __cpu_name[cpu] = "MIPS 4KEc"; |
Ralf Baechle | 2b07bd0 | 2005-04-08 20:36:05 +0000 | [diff] [blame] | 1531 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1532 | case PRID_IMP_4KSC: |
Ralf Baechle | 8afcb5d | 2005-10-04 15:01:26 +0100 | [diff] [blame] | 1533 | case PRID_IMP_4KSD: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1534 | c->cputype = CPU_4KSC; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1535 | c->writecombine = _CACHE_UNCACHED; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1536 | __cpu_name[cpu] = "MIPS 4KSc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1537 | break; |
| 1538 | case PRID_IMP_5KC: |
| 1539 | c->cputype = CPU_5KC; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1540 | c->writecombine = _CACHE_UNCACHED; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1541 | __cpu_name[cpu] = "MIPS 5Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1542 | break; |
Leonid Yegoshin | 78d4803 | 2012-07-06 21:56:01 +0200 | [diff] [blame] | 1543 | case PRID_IMP_5KE: |
| 1544 | c->cputype = CPU_5KE; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1545 | c->writecombine = _CACHE_UNCACHED; |
Leonid Yegoshin | 78d4803 | 2012-07-06 21:56:01 +0200 | [diff] [blame] | 1546 | __cpu_name[cpu] = "MIPS 5KE"; |
| 1547 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1548 | case PRID_IMP_20KC: |
| 1549 | c->cputype = CPU_20KC; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1550 | c->writecombine = _CACHE_UNCACHED; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1551 | __cpu_name[cpu] = "MIPS 20Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1552 | break; |
| 1553 | case PRID_IMP_24K: |
| 1554 | c->cputype = CPU_24K; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1555 | c->writecombine = _CACHE_UNCACHED; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1556 | __cpu_name[cpu] = "MIPS 24Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1557 | break; |
John Crispin | 42f3cae | 2013-01-11 22:44:10 +0100 | [diff] [blame] | 1558 | case PRID_IMP_24KE: |
| 1559 | c->cputype = CPU_24K; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1560 | c->writecombine = _CACHE_UNCACHED; |
John Crispin | 42f3cae | 2013-01-11 22:44:10 +0100 | [diff] [blame] | 1561 | __cpu_name[cpu] = "MIPS 24KEc"; |
| 1562 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1563 | case PRID_IMP_25KF: |
| 1564 | c->cputype = CPU_25KF; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1565 | c->writecombine = _CACHE_UNCACHED; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1566 | __cpu_name[cpu] = "MIPS 25Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1567 | break; |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 1568 | case PRID_IMP_34K: |
| 1569 | c->cputype = CPU_34K; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1570 | c->writecombine = _CACHE_UNCACHED; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1571 | __cpu_name[cpu] = "MIPS 34Kc"; |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 1572 | break; |
Chris Dearman | c620953 | 2006-05-02 14:08:46 +0100 | [diff] [blame] | 1573 | case PRID_IMP_74K: |
| 1574 | c->cputype = CPU_74K; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1575 | c->writecombine = _CACHE_UNCACHED; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1576 | __cpu_name[cpu] = "MIPS 74Kc"; |
Chris Dearman | c620953 | 2006-05-02 14:08:46 +0100 | [diff] [blame] | 1577 | break; |
Steven J. Hill | 113c62d | 2012-07-06 23:56:00 +0200 | [diff] [blame] | 1578 | case PRID_IMP_M14KC: |
| 1579 | c->cputype = CPU_M14KC; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1580 | c->writecombine = _CACHE_UNCACHED; |
Steven J. Hill | 113c62d | 2012-07-06 23:56:00 +0200 | [diff] [blame] | 1581 | __cpu_name[cpu] = "MIPS M14Kc"; |
| 1582 | break; |
Steven J. Hill | f8fa481 | 2012-12-07 03:51:35 +0000 | [diff] [blame] | 1583 | case PRID_IMP_M14KEC: |
| 1584 | c->cputype = CPU_M14KEC; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1585 | c->writecombine = _CACHE_UNCACHED; |
Steven J. Hill | f8fa481 | 2012-12-07 03:51:35 +0000 | [diff] [blame] | 1586 | __cpu_name[cpu] = "MIPS M14KEc"; |
| 1587 | break; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 1588 | case PRID_IMP_1004K: |
| 1589 | c->cputype = CPU_1004K; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1590 | c->writecombine = _CACHE_UNCACHED; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1591 | __cpu_name[cpu] = "MIPS 1004Kc"; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 1592 | break; |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 1593 | case PRID_IMP_1074K: |
Steven J. Hill | 442e14a | 2014-01-17 15:03:50 -0600 | [diff] [blame] | 1594 | c->cputype = CPU_1074K; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1595 | c->writecombine = _CACHE_UNCACHED; |
Steven J. Hill | 006a851 | 2012-06-26 04:11:03 +0000 | [diff] [blame] | 1596 | __cpu_name[cpu] = "MIPS 1074Kc"; |
| 1597 | break; |
Leonid Yegoshin | b5f065e | 2013-11-20 10:46:02 +0000 | [diff] [blame] | 1598 | case PRID_IMP_INTERAPTIV_UP: |
| 1599 | c->cputype = CPU_INTERAPTIV; |
| 1600 | __cpu_name[cpu] = "MIPS interAptiv"; |
| 1601 | break; |
| 1602 | case PRID_IMP_INTERAPTIV_MP: |
| 1603 | c->cputype = CPU_INTERAPTIV; |
| 1604 | __cpu_name[cpu] = "MIPS interAptiv (multi)"; |
| 1605 | break; |
Leonid Yegoshin | b0d4d30 | 2013-11-14 16:12:28 +0000 | [diff] [blame] | 1606 | case PRID_IMP_PROAPTIV_UP: |
| 1607 | c->cputype = CPU_PROAPTIV; |
| 1608 | __cpu_name[cpu] = "MIPS proAptiv"; |
| 1609 | break; |
| 1610 | case PRID_IMP_PROAPTIV_MP: |
| 1611 | c->cputype = CPU_PROAPTIV; |
| 1612 | __cpu_name[cpu] = "MIPS proAptiv (multi)"; |
| 1613 | break; |
James Hogan | 829dcc0 | 2014-01-22 16:19:39 +0000 | [diff] [blame] | 1614 | case PRID_IMP_P5600: |
| 1615 | c->cputype = CPU_P5600; |
| 1616 | __cpu_name[cpu] = "MIPS P5600"; |
| 1617 | break; |
Paul Burton | eba20a3a | 2016-02-03 03:26:39 +0000 | [diff] [blame] | 1618 | case PRID_IMP_P6600: |
| 1619 | c->cputype = CPU_P6600; |
| 1620 | __cpu_name[cpu] = "MIPS P6600"; |
| 1621 | break; |
Markos Chandras | e57f9a2 | 2015-07-09 10:40:37 +0100 | [diff] [blame] | 1622 | case PRID_IMP_I6400: |
| 1623 | c->cputype = CPU_I6400; |
| 1624 | __cpu_name[cpu] = "MIPS I6400"; |
| 1625 | break; |
Paul Burton | 859aeb1 | 2017-06-02 12:39:04 -0700 | [diff] [blame] | 1626 | case PRID_IMP_I6500: |
| 1627 | c->cputype = CPU_I6500; |
| 1628 | __cpu_name[cpu] = "MIPS I6500"; |
| 1629 | break; |
Leonid Yegoshin | 9943ed9 | 2014-03-04 13:34:44 +0000 | [diff] [blame] | 1630 | case PRID_IMP_M5150: |
| 1631 | c->cputype = CPU_M5150; |
| 1632 | __cpu_name[cpu] = "MIPS M5150"; |
| 1633 | break; |
Paul Burton | 43aff74 | 2016-02-03 16:17:30 +0000 | [diff] [blame] | 1634 | case PRID_IMP_M6250: |
| 1635 | c->cputype = CPU_M6250; |
| 1636 | __cpu_name[cpu] = "MIPS M6250"; |
| 1637 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1638 | } |
Chris Dearman | 0b6d497 | 2007-09-13 12:32:02 +0100 | [diff] [blame] | 1639 | |
Leonid Yegoshin | 75b5b5e | 2013-11-14 16:12:31 +0000 | [diff] [blame] | 1640 | decode_configs(c); |
| 1641 | |
Chris Dearman | 0b6d497 | 2007-09-13 12:32:02 +0100 | [diff] [blame] | 1642 | spram_config(); |
Paul Burton | e7bc855 | 2017-06-02 15:38:01 -0700 | [diff] [blame] | 1643 | |
| 1644 | switch (__get_cpu_type(c->cputype)) { |
| 1645 | case CPU_I6500: |
| 1646 | c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; |
| 1647 | /* fall-through */ |
| 1648 | case CPU_I6400: |
| 1649 | c->options |= MIPS_CPU_SHARED_FTLB_RAM; |
| 1650 | /* fall-through */ |
| 1651 | default: |
| 1652 | break; |
| 1653 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1654 | } |
| 1655 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1656 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1657 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1658 | decode_configs(c); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1659 | switch (c->processor_id & PRID_IMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1660 | case PRID_IMP_AU1_REV1: |
| 1661 | case PRID_IMP_AU1_REV2: |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 1662 | c->cputype = CPU_ALCHEMY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1663 | switch ((c->processor_id >> 24) & 0xff) { |
| 1664 | case 0: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1665 | __cpu_name[cpu] = "Au1000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1666 | break; |
| 1667 | case 1: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1668 | __cpu_name[cpu] = "Au1500"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1669 | break; |
| 1670 | case 2: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1671 | __cpu_name[cpu] = "Au1100"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1672 | break; |
| 1673 | case 3: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1674 | __cpu_name[cpu] = "Au1550"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1675 | break; |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 1676 | case 4: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1677 | __cpu_name[cpu] = "Au1200"; |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1678 | if ((c->processor_id & PRID_REV_MASK) == 2) |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1679 | __cpu_name[cpu] = "Au1250"; |
Manuel Lauss | 237cfee | 2007-12-06 09:07:55 +0100 | [diff] [blame] | 1680 | break; |
| 1681 | case 5: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1682 | __cpu_name[cpu] = "Au1210"; |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 1683 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1684 | default: |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 1685 | __cpu_name[cpu] = "Au1xxx"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1686 | break; |
| 1687 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1688 | break; |
| 1689 | } |
| 1690 | } |
| 1691 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1692 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1693 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1694 | decode_configs(c); |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 1695 | |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1696 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1697 | switch (c->processor_id & PRID_IMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1698 | case PRID_IMP_SB1: |
| 1699 | c->cputype = CPU_SB1; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1700 | __cpu_name[cpu] = "SiByte SB1"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1701 | /* FPU in pass1 is known to have issues. */ |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1702 | if ((c->processor_id & PRID_REV_MASK) < 0x02) |
Ralf Baechle | 010b853 | 2006-01-29 18:42:08 +0000 | [diff] [blame] | 1703 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1704 | break; |
Andrew Isaacson | 93ce2f52 | 2005-10-19 23:56:20 -0700 | [diff] [blame] | 1705 | case PRID_IMP_SB1A: |
| 1706 | c->cputype = CPU_SB1A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1707 | __cpu_name[cpu] = "SiByte SB1A"; |
Andrew Isaacson | 93ce2f52 | 2005-10-19 23:56:20 -0700 | [diff] [blame] | 1708 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1709 | } |
| 1710 | } |
| 1711 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1712 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1713 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1714 | decode_configs(c); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1715 | switch (c->processor_id & PRID_IMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1716 | case PRID_IMP_SR71000: |
| 1717 | c->cputype = CPU_SR71000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1718 | __cpu_name[cpu] = "Sandcraft SR71000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1719 | c->scache.ways = 8; |
| 1720 | c->tlbsize = 64; |
| 1721 | break; |
| 1722 | } |
| 1723 | } |
| 1724 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1725 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 1726 | { |
| 1727 | decode_configs(c); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1728 | switch (c->processor_id & PRID_IMP_MASK) { |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 1729 | case PRID_IMP_PR4450: |
| 1730 | c->cputype = CPU_PR4450; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1731 | __cpu_name[cpu] = "Philips PR4450"; |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1732 | set_isa(c, MIPS_CPU_ISA_M32R1); |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 1733 | break; |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 1734 | } |
| 1735 | } |
| 1736 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1737 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1738 | { |
| 1739 | decode_configs(c); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1740 | switch (c->processor_id & PRID_IMP_MASK) { |
Kevin Cernekee | 190fca3 | 2010-11-23 10:26:45 -0800 | [diff] [blame] | 1741 | case PRID_IMP_BMIPS32_REV4: |
| 1742 | case PRID_IMP_BMIPS32_REV8: |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 1743 | c->cputype = CPU_BMIPS32; |
| 1744 | __cpu_name[cpu] = "Broadcom BMIPS32"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 1745 | set_elf_platform(cpu, "bmips32"); |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1746 | break; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 1747 | case PRID_IMP_BMIPS3300: |
| 1748 | case PRID_IMP_BMIPS3300_ALT: |
| 1749 | case PRID_IMP_BMIPS3300_BUG: |
| 1750 | c->cputype = CPU_BMIPS3300; |
| 1751 | __cpu_name[cpu] = "Broadcom BMIPS3300"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 1752 | set_elf_platform(cpu, "bmips3300"); |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1753 | break; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 1754 | case PRID_IMP_BMIPS43XX: { |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1755 | int rev = c->processor_id & PRID_REV_MASK; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 1756 | |
| 1757 | if (rev >= PRID_REV_BMIPS4380_LO && |
| 1758 | rev <= PRID_REV_BMIPS4380_HI) { |
| 1759 | c->cputype = CPU_BMIPS4380; |
| 1760 | __cpu_name[cpu] = "Broadcom BMIPS4380"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 1761 | set_elf_platform(cpu, "bmips4380"); |
Florian Fainelli | b472080 | 2016-02-09 12:55:53 -0800 | [diff] [blame] | 1762 | c->options |= MIPS_CPU_RIXI; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 1763 | } else { |
| 1764 | c->cputype = CPU_BMIPS4350; |
| 1765 | __cpu_name[cpu] = "Broadcom BMIPS4350"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 1766 | set_elf_platform(cpu, "bmips4350"); |
Maxime Bizon | 0de663e | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 1767 | } |
| 1768 | break; |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1769 | } |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 1770 | case PRID_IMP_BMIPS5000: |
Kevin Cernekee | 68e6a78 | 2014-10-20 21:28:01 -0700 | [diff] [blame] | 1771 | case PRID_IMP_BMIPS5200: |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 1772 | c->cputype = CPU_BMIPS5000; |
Florian Fainelli | 37808d6 | 2016-04-04 10:55:38 -0700 | [diff] [blame] | 1773 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) |
| 1774 | __cpu_name[cpu] = "Broadcom BMIPS5200"; |
| 1775 | else |
| 1776 | __cpu_name[cpu] = "Broadcom BMIPS5000"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 1777 | set_elf_platform(cpu, "bmips5000"); |
Florian Fainelli | b472080 | 2016-02-09 12:55:53 -0800 | [diff] [blame] | 1778 | c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 1779 | break; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 1780 | } |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1781 | } |
| 1782 | |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 1783 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
| 1784 | { |
| 1785 | decode_configs(c); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1786 | switch (c->processor_id & PRID_IMP_MASK) { |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 1787 | case PRID_IMP_CAVIUM_CN38XX: |
| 1788 | case PRID_IMP_CAVIUM_CN31XX: |
| 1789 | case PRID_IMP_CAVIUM_CN30XX: |
David Daney | 6f32946 | 2010-02-10 15:12:48 -0800 | [diff] [blame] | 1790 | c->cputype = CPU_CAVIUM_OCTEON; |
| 1791 | __cpu_name[cpu] = "Cavium Octeon"; |
| 1792 | goto platform; |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 1793 | case PRID_IMP_CAVIUM_CN58XX: |
| 1794 | case PRID_IMP_CAVIUM_CN56XX: |
| 1795 | case PRID_IMP_CAVIUM_CN50XX: |
| 1796 | case PRID_IMP_CAVIUM_CN52XX: |
David Daney | 6f32946 | 2010-02-10 15:12:48 -0800 | [diff] [blame] | 1797 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; |
| 1798 | __cpu_name[cpu] = "Cavium Octeon+"; |
| 1799 | platform: |
Robert Millan | c094c99 | 2011-04-18 11:37:55 -0700 | [diff] [blame] | 1800 | set_elf_platform(cpu, "octeon"); |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 1801 | break; |
David Daney | a1431b6 | 2011-09-24 02:29:54 +0200 | [diff] [blame] | 1802 | case PRID_IMP_CAVIUM_CN61XX: |
David Daney | 0e56b38 | 2010-10-07 16:03:45 -0700 | [diff] [blame] | 1803 | case PRID_IMP_CAVIUM_CN63XX: |
David Daney | a1431b6 | 2011-09-24 02:29:54 +0200 | [diff] [blame] | 1804 | case PRID_IMP_CAVIUM_CN66XX: |
| 1805 | case PRID_IMP_CAVIUM_CN68XX: |
David Daney | af04bb8 | 2013-07-29 15:07:01 -0700 | [diff] [blame] | 1806 | case PRID_IMP_CAVIUM_CNF71XX: |
David Daney | 0e56b38 | 2010-10-07 16:03:45 -0700 | [diff] [blame] | 1807 | c->cputype = CPU_CAVIUM_OCTEON2; |
| 1808 | __cpu_name[cpu] = "Cavium Octeon II"; |
Robert Millan | c094c99 | 2011-04-18 11:37:55 -0700 | [diff] [blame] | 1809 | set_elf_platform(cpu, "octeon2"); |
David Daney | 0e56b38 | 2010-10-07 16:03:45 -0700 | [diff] [blame] | 1810 | break; |
David Daney | af04bb8 | 2013-07-29 15:07:01 -0700 | [diff] [blame] | 1811 | case PRID_IMP_CAVIUM_CN70XX: |
David Daney | b8c8f66 | 2016-02-01 14:43:41 -0800 | [diff] [blame] | 1812 | case PRID_IMP_CAVIUM_CN73XX: |
| 1813 | case PRID_IMP_CAVIUM_CNF75XX: |
David Daney | af04bb8 | 2013-07-29 15:07:01 -0700 | [diff] [blame] | 1814 | case PRID_IMP_CAVIUM_CN78XX: |
| 1815 | c->cputype = CPU_CAVIUM_OCTEON3; |
| 1816 | __cpu_name[cpu] = "Cavium Octeon III"; |
| 1817 | set_elf_platform(cpu, "octeon3"); |
| 1818 | break; |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 1819 | default: |
| 1820 | printk(KERN_INFO "Unknown Octeon chip!\n"); |
| 1821 | c->cputype = CPU_UNKNOWN; |
| 1822 | break; |
| 1823 | } |
| 1824 | } |
| 1825 | |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 1826 | static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) |
| 1827 | { |
| 1828 | switch (c->processor_id & PRID_IMP_MASK) { |
| 1829 | case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ |
| 1830 | switch (c->processor_id & PRID_REV_MASK) { |
| 1831 | case PRID_REV_LOONGSON3A_R2: |
| 1832 | c->cputype = CPU_LOONGSON3; |
| 1833 | __cpu_name[cpu] = "ICT Loongson-3"; |
| 1834 | set_elf_platform(cpu, "loongson3a"); |
| 1835 | set_isa(c, MIPS_CPU_ISA_M64R2); |
| 1836 | break; |
Huacai Chen | 0a00024 | 2017-06-22 23:06:48 +0800 | [diff] [blame] | 1837 | case PRID_REV_LOONGSON3A_R3: |
| 1838 | c->cputype = CPU_LOONGSON3; |
| 1839 | __cpu_name[cpu] = "ICT Loongson-3"; |
| 1840 | set_elf_platform(cpu, "loongson3a"); |
| 1841 | set_isa(c, MIPS_CPU_ISA_M64R2); |
| 1842 | break; |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 1843 | } |
| 1844 | |
| 1845 | decode_configs(c); |
Huacai Chen | 033cffee | 2017-03-16 21:00:25 +0800 | [diff] [blame] | 1846 | c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 1847 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
| 1848 | break; |
| 1849 | default: |
| 1850 | panic("Unknown Loongson Processor ID!"); |
| 1851 | break; |
| 1852 | } |
| 1853 | } |
| 1854 | |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 1855 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) |
| 1856 | { |
| 1857 | decode_configs(c); |
| 1858 | /* JZRISC does not implement the CP0 counter. */ |
| 1859 | c->options &= ~MIPS_CPU_COUNTER; |
Maciej W. Rozycki | 06947aa | 2014-04-06 21:31:29 +0100 | [diff] [blame] | 1860 | BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1861 | switch (c->processor_id & PRID_IMP_MASK) { |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 1862 | case PRID_IMP_JZRISC: |
| 1863 | c->cputype = CPU_JZRISC; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1864 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 1865 | __cpu_name[cpu] = "Ingenic JZRISC"; |
| 1866 | break; |
| 1867 | default: |
| 1868 | panic("Unknown Ingenic Processor ID!"); |
| 1869 | break; |
| 1870 | } |
| 1871 | } |
| 1872 | |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1873 | static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) |
| 1874 | { |
| 1875 | decode_configs(c); |
| 1876 | |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1877 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { |
Manuel Lauss | 809f36c | 2011-11-01 20:03:30 +0100 | [diff] [blame] | 1878 | c->cputype = CPU_ALCHEMY; |
| 1879 | __cpu_name[cpu] = "Au1300"; |
| 1880 | /* following stuff is not for Alchemy */ |
| 1881 | return; |
| 1882 | } |
| 1883 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1884 | c->options = (MIPS_CPU_TLB | |
| 1885 | MIPS_CPU_4KEX | |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1886 | MIPS_CPU_COUNTER | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1887 | MIPS_CPU_DIVEC | |
| 1888 | MIPS_CPU_WATCH | |
| 1889 | MIPS_CPU_EJTAG | |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1890 | MIPS_CPU_LLSC); |
| 1891 | |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1892 | switch (c->processor_id & PRID_IMP_MASK) { |
Jayachandran C | 4ca86a2 | 2013-08-11 14:43:54 +0530 | [diff] [blame] | 1893 | case PRID_IMP_NETLOGIC_XLP2XX: |
Jayachandran C | 8907c55 | 2013-12-21 16:52:20 +0530 | [diff] [blame] | 1894 | case PRID_IMP_NETLOGIC_XLP9XX: |
Yonghong Song | 1c98398 | 2014-04-29 20:07:53 +0530 | [diff] [blame] | 1895 | case PRID_IMP_NETLOGIC_XLP5XX: |
Jayachandran C | 4ca86a2 | 2013-08-11 14:43:54 +0530 | [diff] [blame] | 1896 | c->cputype = CPU_XLP; |
| 1897 | __cpu_name[cpu] = "Broadcom XLPII"; |
| 1898 | break; |
| 1899 | |
Jayachandran C | 2aa54b2 | 2011-11-16 00:21:29 +0000 | [diff] [blame] | 1900 | case PRID_IMP_NETLOGIC_XLP8XX: |
| 1901 | case PRID_IMP_NETLOGIC_XLP3XX: |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1902 | c->cputype = CPU_XLP; |
| 1903 | __cpu_name[cpu] = "Netlogic XLP"; |
| 1904 | break; |
| 1905 | |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1906 | case PRID_IMP_NETLOGIC_XLR732: |
| 1907 | case PRID_IMP_NETLOGIC_XLR716: |
| 1908 | case PRID_IMP_NETLOGIC_XLR532: |
| 1909 | case PRID_IMP_NETLOGIC_XLR308: |
| 1910 | case PRID_IMP_NETLOGIC_XLR532C: |
| 1911 | case PRID_IMP_NETLOGIC_XLR516C: |
| 1912 | case PRID_IMP_NETLOGIC_XLR508C: |
| 1913 | case PRID_IMP_NETLOGIC_XLR308C: |
| 1914 | c->cputype = CPU_XLR; |
| 1915 | __cpu_name[cpu] = "Netlogic XLR"; |
| 1916 | break; |
| 1917 | |
| 1918 | case PRID_IMP_NETLOGIC_XLS608: |
| 1919 | case PRID_IMP_NETLOGIC_XLS408: |
| 1920 | case PRID_IMP_NETLOGIC_XLS404: |
| 1921 | case PRID_IMP_NETLOGIC_XLS208: |
| 1922 | case PRID_IMP_NETLOGIC_XLS204: |
| 1923 | case PRID_IMP_NETLOGIC_XLS108: |
| 1924 | case PRID_IMP_NETLOGIC_XLS104: |
| 1925 | case PRID_IMP_NETLOGIC_XLS616B: |
| 1926 | case PRID_IMP_NETLOGIC_XLS608B: |
| 1927 | case PRID_IMP_NETLOGIC_XLS416B: |
| 1928 | case PRID_IMP_NETLOGIC_XLS412B: |
| 1929 | case PRID_IMP_NETLOGIC_XLS408B: |
| 1930 | case PRID_IMP_NETLOGIC_XLS404B: |
| 1931 | c->cputype = CPU_XLR; |
| 1932 | __cpu_name[cpu] = "Netlogic XLS"; |
| 1933 | break; |
| 1934 | |
| 1935 | default: |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1936 | pr_info("Unknown Netlogic chip id [%02x]!\n", |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1937 | c->processor_id); |
| 1938 | c->cputype = CPU_XLR; |
| 1939 | break; |
| 1940 | } |
| 1941 | |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1942 | if (c->cputype == CPU_XLP) { |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1943 | set_isa(c, MIPS_CPU_ISA_M64R2); |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1944 | c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); |
| 1945 | /* This will be updated again after all threads are woken up */ |
| 1946 | c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; |
| 1947 | } else { |
Steven J. Hill | a96102b | 2012-12-07 04:31:36 +0000 | [diff] [blame] | 1948 | set_isa(c, MIPS_CPU_ISA_M64R1); |
Jayachandran C | a3d4fb2 | 2011-11-16 00:21:20 +0000 | [diff] [blame] | 1949 | c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; |
| 1950 | } |
Jayachandran C | 7777b93 | 2013-06-11 14:41:35 +0000 | [diff] [blame] | 1951 | c->kscratch_mask = 0xf; |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1952 | } |
| 1953 | |
David Daney | 949e51b | 2010-10-14 11:32:33 -0700 | [diff] [blame] | 1954 | #ifdef CONFIG_64BIT |
| 1955 | /* For use by uaccess.h */ |
| 1956 | u64 __ua_limit; |
| 1957 | EXPORT_SYMBOL(__ua_limit); |
| 1958 | #endif |
| 1959 | |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1960 | const char *__cpu_name[NR_CPUS]; |
David Daney | 874fd3b | 2010-01-28 16:52:12 -0800 | [diff] [blame] | 1961 | const char *__elf_platform; |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1962 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 1963 | void cpu_probe(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1964 | { |
| 1965 | struct cpuinfo_mips *c = ¤t_cpu_data; |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1966 | unsigned int cpu = smp_processor_id(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1967 | |
Marcin Nowakowski | 05510f2 | 2017-03-07 14:19:56 +0100 | [diff] [blame] | 1968 | /* |
| 1969 | * Set a default elf platform, cpu probe may later |
| 1970 | * overwrite it with a more precise value |
| 1971 | */ |
| 1972 | set_elf_platform(cpu, "mips"); |
| 1973 | |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 1974 | c->processor_id = PRID_IMP_UNKNOWN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1975 | c->fpu_id = FPIR_IMP_NONE; |
| 1976 | c->cputype = CPU_UNKNOWN; |
Markos Chandras | 4f12b91 | 2014-07-18 10:51:32 +0100 | [diff] [blame] | 1977 | c->writecombine = _CACHE_UNCACHED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1978 | |
Maciej W. Rozycki | 9b26616 | 2015-04-03 23:27:48 +0100 | [diff] [blame] | 1979 | c->fpu_csr31 = FPU_CSR_RN; |
| 1980 | c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; |
| 1981 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1982 | c->processor_id = read_c0_prid(); |
Maciej W. Rozycki | 8ff374b | 2013-09-17 16:58:10 +0100 | [diff] [blame] | 1983 | switch (c->processor_id & PRID_COMP_MASK) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1984 | case PRID_COMP_LEGACY: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1985 | cpu_probe_legacy(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1986 | break; |
| 1987 | case PRID_COMP_MIPS: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1988 | cpu_probe_mips(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1989 | break; |
| 1990 | case PRID_COMP_ALCHEMY: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1991 | cpu_probe_alchemy(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1992 | break; |
| 1993 | case PRID_COMP_SIBYTE: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1994 | cpu_probe_sibyte(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1995 | break; |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1996 | case PRID_COMP_BROADCOM: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1997 | cpu_probe_broadcom(c, cpu); |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1998 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1999 | case PRID_COMP_SANDCRAFT: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 2000 | cpu_probe_sandcraft(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2001 | break; |
Daniel Laird | a92b058 | 2008-03-06 09:07:18 +0000 | [diff] [blame] | 2002 | case PRID_COMP_NXP: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 2003 | cpu_probe_nxp(c, cpu); |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 2004 | break; |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 2005 | case PRID_COMP_CAVIUM: |
| 2006 | cpu_probe_cavium(c, cpu); |
| 2007 | break; |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 2008 | case PRID_COMP_LOONGSON: |
| 2009 | cpu_probe_loongson(c, cpu); |
| 2010 | break; |
Paul Burton | 252617a | 2015-05-24 16:11:14 +0100 | [diff] [blame] | 2011 | case PRID_COMP_INGENIC_D0: |
| 2012 | case PRID_COMP_INGENIC_D1: |
| 2013 | case PRID_COMP_INGENIC_E1: |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 2014 | cpu_probe_ingenic(c, cpu); |
| 2015 | break; |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 2016 | case PRID_COMP_NETLOGIC: |
| 2017 | cpu_probe_netlogic(c, cpu); |
| 2018 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2019 | } |
Franck Bui-Huu | dec8b1c | 2007-10-08 16:11:51 +0200 | [diff] [blame] | 2020 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 2021 | BUG_ON(!__cpu_name[cpu]); |
| 2022 | BUG_ON(c->cputype == CPU_UNKNOWN); |
| 2023 | |
Franck Bui-Huu | dec8b1c | 2007-10-08 16:11:51 +0200 | [diff] [blame] | 2024 | /* |
| 2025 | * Platform code can force the cpu type to optimize code |
| 2026 | * generation. In that case be sure the cpu type is correctly |
| 2027 | * manually setup otherwise it could trigger some nasty bugs. |
| 2028 | */ |
| 2029 | BUG_ON(current_cpu_type() != c->cputype); |
| 2030 | |
Florian Fainelli | 2e27476 | 2016-02-09 12:55:52 -0800 | [diff] [blame] | 2031 | if (cpu_has_rixi) { |
| 2032 | /* Enable the RIXI exceptions */ |
| 2033 | set_c0_pagegrain(PG_IEC); |
| 2034 | back_to_back_c0_hazard(); |
| 2035 | /* Verify the IEC bit is set */ |
| 2036 | if (read_c0_pagegrain() & PG_IEC) |
| 2037 | c->options |= MIPS_CPU_RIXIEX; |
| 2038 | } |
| 2039 | |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 2040 | if (mips_fpu_disabled) |
| 2041 | c->options &= ~MIPS_CPU_FPU; |
| 2042 | |
| 2043 | if (mips_dsp_disabled) |
Steven J. Hill | ee80f7c7 | 2012-08-03 10:26:04 -0500 | [diff] [blame] | 2044 | c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 2045 | |
Markos Chandras | 3d528b3 | 2014-07-14 12:46:13 +0100 | [diff] [blame] | 2046 | if (mips_htw_disabled) { |
| 2047 | c->options &= ~MIPS_CPU_HTW; |
| 2048 | write_c0_pwctl(read_c0_pwctl() & |
| 2049 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); |
| 2050 | } |
| 2051 | |
Maciej W. Rozycki | 7aecd5c | 2015-04-03 23:27:54 +0100 | [diff] [blame] | 2052 | if (c->options & MIPS_CPU_FPU) |
| 2053 | cpu_set_fpu_opts(c); |
| 2054 | else |
| 2055 | cpu_set_nofpu_opts(c); |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 2056 | |
Joshua Kinard | 8d5ded1 | 2015-06-02 18:21:33 -0400 | [diff] [blame] | 2057 | if (cpu_has_bp_ghist) |
| 2058 | write_c0_r10k_diag(read_c0_r10k_diag() | |
| 2059 | R10K_DIAG_E_GHIST); |
| 2060 | |
Leonid Yegoshin | 8b8aa63 | 2014-11-13 13:51:51 +0000 | [diff] [blame] | 2061 | if (cpu_has_mips_r2_r6) { |
Ralf Baechle | f6771db | 2007-11-08 18:02:29 +0000 | [diff] [blame] | 2062 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
Al Cooper | da4b62c | 2012-07-13 16:44:51 -0400 | [diff] [blame] | 2063 | /* R2 has Performance Counter Interrupt indicator */ |
| 2064 | c->options |= MIPS_CPU_PCI; |
| 2065 | } |
Ralf Baechle | f6771db | 2007-11-08 18:02:29 +0000 | [diff] [blame] | 2066 | else |
| 2067 | c->srsets = 1; |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 2068 | |
Paul Burton | 4c06303 | 2015-07-27 12:58:24 -0700 | [diff] [blame] | 2069 | if (cpu_has_mips_r6) |
| 2070 | elf_hwcap |= HWCAP_MIPS_R6; |
| 2071 | |
Paul Burton | a8ad136 | 2014-01-28 14:28:43 +0000 | [diff] [blame] | 2072 | if (cpu_has_msa) { |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 2073 | c->msa_id = cpu_get_msa_id(); |
Paul Burton | a8ad136 | 2014-01-28 14:28:43 +0000 | [diff] [blame] | 2074 | WARN(c->msa_id & MSA_IR_WRPF, |
| 2075 | "Vector register partitioning unimplemented!"); |
Paul Burton | 3cc9fa7 | 2015-07-27 12:58:25 -0700 | [diff] [blame] | 2076 | elf_hwcap |= HWCAP_MIPS_MSA; |
Paul Burton | a8ad136 | 2014-01-28 14:28:43 +0000 | [diff] [blame] | 2077 | } |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 2078 | |
James Hogan | 6ad816e | 2016-05-11 15:50:30 +0100 | [diff] [blame] | 2079 | if (cpu_has_vz) |
| 2080 | cpu_probe_vz(c); |
| 2081 | |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 2082 | cpu_probe_vmbits(c); |
David Daney | 949e51b | 2010-10-14 11:32:33 -0700 | [diff] [blame] | 2083 | |
| 2084 | #ifdef CONFIG_64BIT |
| 2085 | if (cpu == 0) |
| 2086 | __ua_limit = ~((1ull << cpu_vmbits) - 1); |
| 2087 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2088 | } |
| 2089 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 2090 | void cpu_report(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2091 | { |
| 2092 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 2093 | |
Leonid Yegoshin | d9f897c | 2013-10-07 10:43:32 +0100 | [diff] [blame] | 2094 | pr_info("CPU%d revision is: %08x (%s)\n", |
| 2095 | smp_processor_id(), c->processor_id, cpu_name_string()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2096 | if (c->options & MIPS_CPU_FPU) |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 2097 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
Paul Burton | a5e9a69 | 2014-01-27 15:23:10 +0000 | [diff] [blame] | 2098 | if (cpu_has_msa) |
| 2099 | pr_info("MSA revision is: %08x\n", c->msa_id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2100 | } |
Paul Burton | 856fbce | 2017-08-12 19:49:36 -0700 | [diff] [blame] | 2101 | |
Paul Burton | 5616897 | 2017-08-12 19:49:38 -0700 | [diff] [blame] | 2102 | void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster) |
| 2103 | { |
| 2104 | /* Ensure the core number fits in the field */ |
| 2105 | WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >> |
| 2106 | MIPS_GLOBALNUMBER_CLUSTER_SHF)); |
| 2107 | |
| 2108 | cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; |
| 2109 | cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; |
| 2110 | } |
| 2111 | |
Paul Burton | 856fbce | 2017-08-12 19:49:36 -0700 | [diff] [blame] | 2112 | void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core) |
| 2113 | { |
| 2114 | /* Ensure the core number fits in the field */ |
| 2115 | WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF)); |
| 2116 | |
| 2117 | cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; |
| 2118 | cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; |
| 2119 | } |
| 2120 | |
| 2121 | void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe) |
| 2122 | { |
| 2123 | /* Ensure the VP(E) ID fits in the field */ |
| 2124 | WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF)); |
| 2125 | |
| 2126 | /* Ensure we're not using VP(E)s without support */ |
| 2127 | WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) && |
| 2128 | !IS_ENABLED(CONFIG_CPU_MIPSR6)); |
| 2129 | |
| 2130 | cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; |
| 2131 | cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; |
| 2132 | } |