commit 9267a30d1dc7dcd7cadb5eb6a5bbfed703feeefa
author Marc St-Jean <stjeanma@pmc-sierra.com> Thu Jun 14 15:55:31 2007 -0600
committer Ralf Baechle <ralf@linux-mips.org> Tue Jul 10 17:33:03 2007 +0100
tree 91fa5a1a4605cdf0a1f1db21e22073b87735ce7a
parent 35832e26f95ba14a6b6f0519441c5cb64cca6bf9

[MIPS] PMC MSP71xx mips common

Patch to add mips common support for the PMC-Sierra MSP71xx devices.

Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/kernel/cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 23d8a3b..c6b8b07 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -186,9 +186,29 @@
 	}
 }
 
+static inline void check_errata(void)
+{
+	struct cpuinfo_mips *c = &current_cpu_data;
+
+	switch (c->cputype) {
+	case CPU_34K:
+		/*
+		 * Erratum "RPS May Cause Incorrect Instruction Execution"
+		 * This code only handles VPE0, any SMP/SMTC/RTOS code
+		 * making use of VPE1 will be responsable for that VPE.
+		 */
+		if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
+			write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
+		break;
+	default:
+		break;
+	}
+}
+
 void __init check_bugs32(void)
 {
 	check_wait();
+	check_errata();
 }
 
 /*