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LeafOS / LeafOS-Project / android_art / 8b858e16563ebf8e522df026a6ab409f1bd9b3de / . / compiler / dex / mir_dataflow.cc
blob: 64895d8ed66a1141e3c6dd4aaf6bdf8cc4e898b4 [file] [log] [blame]
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "compiler_internals.h"
18#include "local_value_numbering.h"
Ian Rogers8d3a1172013-06-04 01:13:28 -0700[diff] [blame]19#include "dataflow_iterator-inl.h"
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]20
21namespace art {
22
23/*
24 * Main table containing data flow attributes for each bytecode. The
25 * first kNumPackedOpcodes entries are for Dalvik bytecode
26 * instructions, where extended opcode at the MIR level are appended
27 * afterwards.
28 *
29 * TODO - many optimization flags are incomplete - they will only limit the
30 * scope of optimizations but will not cause mis-optimizations.
31 */
buzbee1da1e2f2013-11-15 13:37:01 -0800[diff] [blame]32const uint64_t MIRGraph::oat_data_flow_attributes_[kMirOpLast] = {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]33 // 00 NOP
34 DF_NOP,
35
36 // 01 MOVE vA, vB
37 DF_DA | DF_UB | DF_IS_MOVE,
38
39 // 02 MOVE_FROM16 vAA, vBBBB
40 DF_DA | DF_UB | DF_IS_MOVE,
41
42 // 03 MOVE_16 vAAAA, vBBBB
43 DF_DA | DF_UB | DF_IS_MOVE,
44
45 // 04 MOVE_WIDE vA, vB
46 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
47
48 // 05 MOVE_WIDE_FROM16 vAA, vBBBB
49 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
50
51 // 06 MOVE_WIDE_16 vAAAA, vBBBB
52 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
53
54 // 07 MOVE_OBJECT vA, vB
55 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
56
57 // 08 MOVE_OBJECT_FROM16 vAA, vBBBB
58 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
59
60 // 09 MOVE_OBJECT_16 vAAAA, vBBBB
61 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
62
63 // 0A MOVE_RESULT vAA
64 DF_DA,
65
66 // 0B MOVE_RESULT_WIDE vAA
67 DF_DA | DF_A_WIDE,
68
69 // 0C MOVE_RESULT_OBJECT vAA
70 DF_DA | DF_REF_A,
71
72 // 0D MOVE_EXCEPTION vAA
Ian Rogersfa7809f2013-06-13 11:15:15 -0700[diff] [blame]73 DF_DA | DF_REF_A | DF_NON_NULL_DST,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]74
75 // 0E RETURN_VOID
76 DF_NOP,
77
78 // 0F RETURN vAA
79 DF_UA,
80
81 // 10 RETURN_WIDE vAA
82 DF_UA | DF_A_WIDE,
83
84 // 11 RETURN_OBJECT vAA
85 DF_UA | DF_REF_A,
86
87 // 12 CONST_4 vA, #+B
88 DF_DA | DF_SETS_CONST,
89
90 // 13 CONST_16 vAA, #+BBBB
91 DF_DA | DF_SETS_CONST,
92
93 // 14 CONST vAA, #+BBBBBBBB
94 DF_DA | DF_SETS_CONST,
95
96 // 15 CONST_HIGH16 VAA, #+BBBB0000
97 DF_DA | DF_SETS_CONST,
98
99 // 16 CONST_WIDE_16 vAA, #+BBBB
100 DF_DA | DF_A_WIDE | DF_SETS_CONST,
101
102 // 17 CONST_WIDE_32 vAA, #+BBBBBBBB
103 DF_DA | DF_A_WIDE | DF_SETS_CONST,
104
105 // 18 CONST_WIDE vAA, #+BBBBBBBBBBBBBBBB
106 DF_DA | DF_A_WIDE | DF_SETS_CONST,
107
108 // 19 CONST_WIDE_HIGH16 vAA, #+BBBB000000000000
109 DF_DA | DF_A_WIDE | DF_SETS_CONST,
110
111 // 1A CONST_STRING vAA, string@BBBB
Ian Rogersfa7809f2013-06-13 11:15:15 -0700[diff] [blame]112 DF_DA | DF_REF_A | DF_NON_NULL_DST,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]113
114 // 1B CONST_STRING_JUMBO vAA, string@BBBBBBBB
Ian Rogersfa7809f2013-06-13 11:15:15 -0700[diff] [blame]115 DF_DA | DF_REF_A | DF_NON_NULL_DST,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]116
117 // 1C CONST_CLASS vAA, type@BBBB
Ian Rogersfa7809f2013-06-13 11:15:15 -0700[diff] [blame]118 DF_DA | DF_REF_A | DF_NON_NULL_DST,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]119
120 // 1D MONITOR_ENTER vAA
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]121 DF_UA | DF_NULL_CHK_A | DF_REF_A,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]122
123 // 1E MONITOR_EXIT vAA
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]124 DF_UA | DF_NULL_CHK_A | DF_REF_A,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]125
126 // 1F CHK_CAST vAA, type@BBBB
127 DF_UA | DF_REF_A | DF_UMS,
128
129 // 20 INSTANCE_OF vA, vB, type@CCCC
130 DF_DA | DF_UB | DF_CORE_A | DF_REF_B | DF_UMS,
131
132 // 21 ARRAY_LENGTH vA, vB
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]133 DF_DA | DF_UB | DF_NULL_CHK_B | DF_CORE_A | DF_REF_B,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]134
135 // 22 NEW_INSTANCE vAA, type@BBBB
136 DF_DA | DF_NON_NULL_DST | DF_REF_A | DF_UMS,
137
138 // 23 NEW_ARRAY vA, vB, type@CCCC
139 DF_DA | DF_UB | DF_NON_NULL_DST | DF_REF_A | DF_CORE_B | DF_UMS,
140
141 // 24 FILLED_NEW_ARRAY {vD, vE, vF, vG, vA}
142 DF_FORMAT_35C | DF_NON_NULL_RET | DF_UMS,
143
144 // 25 FILLED_NEW_ARRAY_RANGE {vCCCC .. vNNNN}, type@BBBB
145 DF_FORMAT_3RC | DF_NON_NULL_RET | DF_UMS,
146
147 // 26 FILL_ARRAY_DATA vAA, +BBBBBBBB
148 DF_UA | DF_REF_A | DF_UMS,
149
150 // 27 THROW vAA
151 DF_UA | DF_REF_A | DF_UMS,
152
153 // 28 GOTO
154 DF_NOP,
155
156 // 29 GOTO_16
157 DF_NOP,
158
159 // 2A GOTO_32
160 DF_NOP,
161
162 // 2B PACKED_SWITCH vAA, +BBBBBBBB
163 DF_UA,
164
165 // 2C SPARSE_SWITCH vAA, +BBBBBBBB
166 DF_UA,
167
168 // 2D CMPL_FLOAT vAA, vBB, vCC
169 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
170
171 // 2E CMPG_FLOAT vAA, vBB, vCC
172 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
173
174 // 2F CMPL_DOUBLE vAA, vBB, vCC
175 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
176
177 // 30 CMPG_DOUBLE vAA, vBB, vCC
178 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
179
180 // 31 CMP_LONG vAA, vBB, vCC
181 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
182
183 // 32 IF_EQ vA, vB, +CCCC
184 DF_UA | DF_UB,
185
186 // 33 IF_NE vA, vB, +CCCC
187 DF_UA | DF_UB,
188
189 // 34 IF_LT vA, vB, +CCCC
190 DF_UA | DF_UB,
191
192 // 35 IF_GE vA, vB, +CCCC
193 DF_UA | DF_UB,
194
195 // 36 IF_GT vA, vB, +CCCC
196 DF_UA | DF_UB,
197
198 // 37 IF_LE vA, vB, +CCCC
199 DF_UA | DF_UB,
200
201 // 38 IF_EQZ vAA, +BBBB
202 DF_UA,
203
204 // 39 IF_NEZ vAA, +BBBB
205 DF_UA,
206
207 // 3A IF_LTZ vAA, +BBBB
208 DF_UA,
209
210 // 3B IF_GEZ vAA, +BBBB
211 DF_UA,
212
213 // 3C IF_GTZ vAA, +BBBB
214 DF_UA,
215
216 // 3D IF_LEZ vAA, +BBBB
217 DF_UA,
218
219 // 3E UNUSED_3E
220 DF_NOP,
221
222 // 3F UNUSED_3F
223 DF_NOP,
224
225 // 40 UNUSED_40
226 DF_NOP,
227
228 // 41 UNUSED_41
229 DF_NOP,
230
231 // 42 UNUSED_42
232 DF_NOP,
233
234 // 43 UNUSED_43
235 DF_NOP,
236
237 // 44 AGET vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]238 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]239
240 // 45 AGET_WIDE vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]241 DF_DA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]242
243 // 46 AGET_OBJECT vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]244 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_A | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]245
246 // 47 AGET_BOOLEAN vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]247 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]248
249 // 48 AGET_BYTE vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]250 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]251
252 // 49 AGET_CHAR vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]253 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]254
255 // 4A AGET_SHORT vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]256 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]257
258 // 4B APUT vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]259 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]260
261 // 4C APUT_WIDE vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]262 DF_UA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]263
264 // 4D APUT_OBJECT vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]265 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_A | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]266
267 // 4E APUT_BOOLEAN vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]268 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]269
270 // 4F APUT_BYTE vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]271 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]272
273 // 50 APUT_CHAR vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]274 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]275
276 // 51 APUT_SHORT vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]277 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]278
279 // 52 IGET vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]280 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]281
282 // 53 IGET_WIDE vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]283 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]284
285 // 54 IGET_OBJECT vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]286 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_A | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]287
288 // 55 IGET_BOOLEAN vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]289 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]290
291 // 56 IGET_BYTE vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]292 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]293
294 // 57 IGET_CHAR vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]295 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]296
297 // 58 IGET_SHORT vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]298 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]299
300 // 59 IPUT vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]301 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]302
303 // 5A IPUT_WIDE vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]304 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]305
306 // 5B IPUT_OBJECT vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]307 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_A | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]308
309 // 5C IPUT_BOOLEAN vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]310 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]311
312 // 5D IPUT_BYTE vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]313 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]314
315 // 5E IPUT_CHAR vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]316 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]317
318 // 5F IPUT_SHORT vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]319 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]320
321 // 60 SGET vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]322 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]323
324 // 61 SGET_WIDE vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]325 DF_DA | DF_A_WIDE | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]326
327 // 62 SGET_OBJECT vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]328 DF_DA | DF_REF_A | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]329
330 // 63 SGET_BOOLEAN vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]331 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]332
333 // 64 SGET_BYTE vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]334 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]335
336 // 65 SGET_CHAR vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]337 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]338
339 // 66 SGET_SHORT vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]340 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]341
342 // 67 SPUT vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]343 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]344
345 // 68 SPUT_WIDE vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]346 DF_UA | DF_A_WIDE | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]347
348 // 69 SPUT_OBJECT vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]349 DF_UA | DF_REF_A | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]350
351 // 6A SPUT_BOOLEAN vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]352 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]353
354 // 6B SPUT_BYTE vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]355 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]356
357 // 6C SPUT_CHAR vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]358 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]359
360 // 6D SPUT_SHORT vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]361 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]362
363 // 6E INVOKE_VIRTUAL {vD, vE, vF, vG, vA}
364 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
365
366 // 6F INVOKE_SUPER {vD, vE, vF, vG, vA}
367 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
368
369 // 70 INVOKE_DIRECT {vD, vE, vF, vG, vA}
370 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
371
372 // 71 INVOKE_STATIC {vD, vE, vF, vG, vA}
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]373 DF_FORMAT_35C | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]374
375 // 72 INVOKE_INTERFACE {vD, vE, vF, vG, vA}
Sebastien Hertz67ce9b02013-07-11 14:31:18 +0200[diff] [blame]376 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]377
378 // 73 UNUSED_73
379 DF_NOP,
380
381 // 74 INVOKE_VIRTUAL_RANGE {vCCCC .. vNNNN}
382 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
383
384 // 75 INVOKE_SUPER_RANGE {vCCCC .. vNNNN}
385 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
386
387 // 76 INVOKE_DIRECT_RANGE {vCCCC .. vNNNN}
388 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
389
390 // 77 INVOKE_STATIC_RANGE {vCCCC .. vNNNN}
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]391 DF_FORMAT_3RC | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]392
393 // 78 INVOKE_INTERFACE_RANGE {vCCCC .. vNNNN}
Sebastien Hertz67ce9b02013-07-11 14:31:18 +0200[diff] [blame]394 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]395
396 // 79 UNUSED_79
397 DF_NOP,
398
399 // 7A UNUSED_7A
400 DF_NOP,
401
402 // 7B NEG_INT vA, vB
403 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
404
405 // 7C NOT_INT vA, vB
406 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
407
408 // 7D NEG_LONG vA, vB
409 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
410
411 // 7E NOT_LONG vA, vB
412 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
413
414 // 7F NEG_FLOAT vA, vB
415 DF_DA | DF_UB | DF_FP_A | DF_FP_B,
416
417 // 80 NEG_DOUBLE vA, vB
418 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
419
420 // 81 INT_TO_LONG vA, vB
421 DF_DA | DF_A_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
422
423 // 82 INT_TO_FLOAT vA, vB
424 DF_DA | DF_UB | DF_FP_A | DF_CORE_B,
425
426 // 83 INT_TO_DOUBLE vA, vB
427 DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_CORE_B,
428
429 // 84 LONG_TO_INT vA, vB
430 DF_DA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
431
432 // 85 LONG_TO_FLOAT vA, vB
433 DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B,
434
435 // 86 LONG_TO_DOUBLE vA, vB
436 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B,
437
438 // 87 FLOAT_TO_INT vA, vB
439 DF_DA | DF_UB | DF_FP_B | DF_CORE_A,
440
441 // 88 FLOAT_TO_LONG vA, vB
442 DF_DA | DF_A_WIDE | DF_UB | DF_FP_B | DF_CORE_A,
443
444 // 89 FLOAT_TO_DOUBLE vA, vB
445 DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_FP_B,
446
447 // 8A DOUBLE_TO_INT vA, vB
448 DF_DA | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A,
449
450 // 8B DOUBLE_TO_LONG vA, vB
451 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A,
452
453 // 8C DOUBLE_TO_FLOAT vA, vB
454 DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
455
456 // 8D INT_TO_BYTE vA, vB
457 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
458
459 // 8E INT_TO_CHAR vA, vB
460 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
461
462 // 8F INT_TO_SHORT vA, vB
463 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
464
465 // 90 ADD_INT vAA, vBB, vCC
466 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
467
468 // 91 SUB_INT vAA, vBB, vCC
469 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
470
471 // 92 MUL_INT vAA, vBB, vCC
472 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
473
474 // 93 DIV_INT vAA, vBB, vCC
475 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
476
477 // 94 REM_INT vAA, vBB, vCC
478 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
479
480 // 95 AND_INT vAA, vBB, vCC
481 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
482
483 // 96 OR_INT vAA, vBB, vCC
484 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
485
486 // 97 XOR_INT vAA, vBB, vCC
487 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
488
489 // 98 SHL_INT vAA, vBB, vCC
490 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
491
492 // 99 SHR_INT vAA, vBB, vCC
493 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
494
495 // 9A USHR_INT vAA, vBB, vCC
496 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
497
498 // 9B ADD_LONG vAA, vBB, vCC
499 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
500
501 // 9C SUB_LONG vAA, vBB, vCC
502 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
503
504 // 9D MUL_LONG vAA, vBB, vCC
505 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
506
507 // 9E DIV_LONG vAA, vBB, vCC
508 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
509
510 // 9F REM_LONG vAA, vBB, vCC
511 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
512
513 // A0 AND_LONG vAA, vBB, vCC
514 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
515
516 // A1 OR_LONG vAA, vBB, vCC
517 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
518
519 // A2 XOR_LONG vAA, vBB, vCC
520 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
521
522 // A3 SHL_LONG vAA, vBB, vCC
523 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
524
525 // A4 SHR_LONG vAA, vBB, vCC
526 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
527
528 // A5 USHR_LONG vAA, vBB, vCC
529 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
530
531 // A6 ADD_FLOAT vAA, vBB, vCC
532 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
533
534 // A7 SUB_FLOAT vAA, vBB, vCC
535 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
536
537 // A8 MUL_FLOAT vAA, vBB, vCC
538 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
539
540 // A9 DIV_FLOAT vAA, vBB, vCC
541 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
542
543 // AA REM_FLOAT vAA, vBB, vCC
544 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
545
546 // AB ADD_DOUBLE vAA, vBB, vCC
547 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
548
549 // AC SUB_DOUBLE vAA, vBB, vCC
550 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
551
552 // AD MUL_DOUBLE vAA, vBB, vCC
553 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
554
555 // AE DIV_DOUBLE vAA, vBB, vCC
556 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
557
558 // AF REM_DOUBLE vAA, vBB, vCC
559 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
560
561 // B0 ADD_INT_2ADDR vA, vB
562 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
563
564 // B1 SUB_INT_2ADDR vA, vB
565 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
566
567 // B2 MUL_INT_2ADDR vA, vB
568 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
569
570 // B3 DIV_INT_2ADDR vA, vB
571 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
572
573 // B4 REM_INT_2ADDR vA, vB
574 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
575
576 // B5 AND_INT_2ADDR vA, vB
577 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
578
579 // B6 OR_INT_2ADDR vA, vB
580 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
581
582 // B7 XOR_INT_2ADDR vA, vB
583 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
584
585 // B8 SHL_INT_2ADDR vA, vB
586 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
587
588 // B9 SHR_INT_2ADDR vA, vB
589 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
590
591 // BA USHR_INT_2ADDR vA, vB
592 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
593
594 // BB ADD_LONG_2ADDR vA, vB
595 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
596
597 // BC SUB_LONG_2ADDR vA, vB
598 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
599
600 // BD MUL_LONG_2ADDR vA, vB
601 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
602
603 // BE DIV_LONG_2ADDR vA, vB
604 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
605
606 // BF REM_LONG_2ADDR vA, vB
607 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
608
609 // C0 AND_LONG_2ADDR vA, vB
610 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
611
612 // C1 OR_LONG_2ADDR vA, vB
613 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
614
615 // C2 XOR_LONG_2ADDR vA, vB
616 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
617
618 // C3 SHL_LONG_2ADDR vA, vB
619 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
620
621 // C4 SHR_LONG_2ADDR vA, vB
622 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
623
624 // C5 USHR_LONG_2ADDR vA, vB
625 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
626
627 // C6 ADD_FLOAT_2ADDR vA, vB
628 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
629
630 // C7 SUB_FLOAT_2ADDR vA, vB
631 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
632
633 // C8 MUL_FLOAT_2ADDR vA, vB
634 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
635
636 // C9 DIV_FLOAT_2ADDR vA, vB
637 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
638
639 // CA REM_FLOAT_2ADDR vA, vB
640 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
641
642 // CB ADD_DOUBLE_2ADDR vA, vB
643 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
644
645 // CC SUB_DOUBLE_2ADDR vA, vB
646 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
647
648 // CD MUL_DOUBLE_2ADDR vA, vB
649 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
650
651 // CE DIV_DOUBLE_2ADDR vA, vB
652 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
653
654 // CF REM_DOUBLE_2ADDR vA, vB
655 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
656
657 // D0 ADD_INT_LIT16 vA, vB, #+CCCC
658 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
659
660 // D1 RSUB_INT vA, vB, #+CCCC
661 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
662
663 // D2 MUL_INT_LIT16 vA, vB, #+CCCC
664 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
665
666 // D3 DIV_INT_LIT16 vA, vB, #+CCCC
667 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
668
669 // D4 REM_INT_LIT16 vA, vB, #+CCCC
670 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
671
672 // D5 AND_INT_LIT16 vA, vB, #+CCCC
673 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
674
675 // D6 OR_INT_LIT16 vA, vB, #+CCCC
676 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
677
678 // D7 XOR_INT_LIT16 vA, vB, #+CCCC
679 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
680
681 // D8 ADD_INT_LIT8 vAA, vBB, #+CC
682 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
683
684 // D9 RSUB_INT_LIT8 vAA, vBB, #+CC
685 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
686
687 // DA MUL_INT_LIT8 vAA, vBB, #+CC
688 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
689
690 // DB DIV_INT_LIT8 vAA, vBB, #+CC
691 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
692
693 // DC REM_INT_LIT8 vAA, vBB, #+CC
694 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
695
696 // DD AND_INT_LIT8 vAA, vBB, #+CC
697 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
698
699 // DE OR_INT_LIT8 vAA, vBB, #+CC
700 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
701
702 // DF XOR_INT_LIT8 vAA, vBB, #+CC
703 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
704
705 // E0 SHL_INT_LIT8 vAA, vBB, #+CC
706 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
707
708 // E1 SHR_INT_LIT8 vAA, vBB, #+CC
709 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
710
711 // E2 USHR_INT_LIT8 vAA, vBB, #+CC
712 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
713
714 // E3 IGET_VOLATILE
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]715 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]716
717 // E4 IPUT_VOLATILE
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]718 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]719
720 // E5 SGET_VOLATILE
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]721 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]722
723 // E6 SPUT_VOLATILE
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]724 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]725
726 // E7 IGET_OBJECT_VOLATILE
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]727 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_A | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]728
729 // E8 IGET_WIDE_VOLATILE
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]730 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]731
732 // E9 IPUT_WIDE_VOLATILE
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]733 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]734
735 // EA SGET_WIDE_VOLATILE
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]736 DF_DA | DF_A_WIDE | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]737
738 // EB SPUT_WIDE_VOLATILE
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]739 DF_UA | DF_A_WIDE | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]740
741 // EC BREAKPOINT
742 DF_NOP,
743
744 // ED THROW_VERIFICATION_ERROR
745 DF_NOP | DF_UMS,
746
747 // EE EXECUTE_INLINE
748 DF_FORMAT_35C,
749
750 // EF EXECUTE_INLINE_RANGE
751 DF_FORMAT_3RC,
752
753 // F0 INVOKE_OBJECT_INIT_RANGE
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]754 DF_NOP,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]755
756 // F1 RETURN_VOID_BARRIER
757 DF_NOP,
758
759 // F2 IGET_QUICK
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]760 DF_DA | DF_UB | DF_NULL_CHK_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]761
762 // F3 IGET_WIDE_QUICK
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]763 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]764
765 // F4 IGET_OBJECT_QUICK
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]766 DF_DA | DF_UB | DF_NULL_CHK_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]767
768 // F5 IPUT_QUICK
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]769 DF_UA | DF_UB | DF_NULL_CHK_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]770
771 // F6 IPUT_WIDE_QUICK
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]772 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]773
774 // F7 IPUT_OBJECT_QUICK
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]775 DF_UA | DF_UB | DF_NULL_CHK_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]776
777 // F8 INVOKE_VIRTUAL_QUICK
778 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
779
780 // F9 INVOKE_VIRTUAL_QUICK_RANGE
781 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
782
783 // FA INVOKE_SUPER_QUICK
784 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
785
786 // FB INVOKE_SUPER_QUICK_RANGE
787 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
788
789 // FC IPUT_OBJECT_VOLATILE
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]790 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_A | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]791
792 // FD SGET_OBJECT_VOLATILE
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]793 DF_DA | DF_REF_A | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]794
795 // FE SPUT_OBJECT_VOLATILE
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]796 DF_UA | DF_REF_A | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]797
798 // FF UNUSED_FF
799 DF_NOP,
800
801 // Beginning of extended MIR opcodes
802 // 100 MIR_PHI
803 DF_DA | DF_NULL_TRANSFER_N,
804
805 // 101 MIR_COPY
806 DF_DA | DF_UB | DF_IS_MOVE,
807
808 // 102 MIR_FUSED_CMPL_FLOAT
809 DF_UA | DF_UB | DF_FP_A | DF_FP_B,
810
811 // 103 MIR_FUSED_CMPG_FLOAT
812 DF_UA | DF_UB | DF_FP_A | DF_FP_B,
813
814 // 104 MIR_FUSED_CMPL_DOUBLE
815 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
816
817 // 105 MIR_FUSED_CMPG_DOUBLE
818 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
819
820 // 106 MIR_FUSED_CMP_LONG
821 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
822
823 // 107 MIR_NOP
824 DF_NOP,
825
826 // 108 MIR_NULL_CHECK
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]827 DF_UA | DF_REF_A | DF_NULL_CHK_A | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]828
829 // 109 MIR_RANGE_CHECK
830 0,
831
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]832 // 10A MIR_DIV_ZERO_CHECK
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]833 0,
834
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]835 // 10B MIR_CHECK
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]836 0,
837
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]838 // 10C MIR_CHECKPART2
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]839 0,
840
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]841 // 10D MIR_SELECT
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]842 DF_DA | DF_UB,
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]843
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]844 // 10E MirOpConstVector
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]845 0,
846
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]847 // 10F MirOpMoveVector
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]848 0,
849
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]850 // 110 MirOpPackedMultiply
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]851 0,
852
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]853 // 111 MirOpPackedAddition
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]854 0,
855
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]856 // 112 MirOpPackedSubtract
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]857 0,
858
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]859 // 113 MirOpPackedShiftLeft
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]860 0,
861
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]862 // 114 MirOpPackedSignedShiftRight
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]863 0,
864
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]865 // 115 MirOpPackedUnsignedShiftRight
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]866 0,
867
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]868 // 116 MirOpPackedAnd
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]869 0,
870
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]871 // 117 MirOpPackedOr
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]872 0,
873
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]874 // 118 MirOpPackedXor
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]875 0,
876
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]877 // 119 MirOpPackedAddReduce
878 DF_FORMAT_EXTENDED,
879
880 // 11A MirOpPackedReduce
881 DF_FORMAT_EXTENDED,
882
883 // 11B MirOpPackedSet
884 DF_FORMAT_EXTENDED,
885
886 // 11C MirOpReserveVectorRegisters
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]887 0,
Jean Christophe Beylerb5bce7c2014-07-25 12:32:18 -0700[diff] [blame]888
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]889 // 11D MirOpReturnVectorRegisters
Jean Christophe Beylerb5bce7c2014-07-25 12:32:18 -0700[diff] [blame]890 0,
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]891
892 // 11E MirOpMemBarrier
893 0,
894
895 // 11F MirOpPackedArrayGet
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]896 DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]897
898 // 120 MirOpPackedArrayPut
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]899 DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]900};
901
902/* Return the base virtual register for a SSA name */
Ian Rogers71fe2672013-03-19 20:45:02 -0700[diff] [blame]903int MIRGraph::SRegToVReg(int ssa_reg) const {
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]904 return ssa_base_vregs_[ssa_reg];
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]905}
906
907/* Any register that is used before being defined is considered live-in */
908void MIRGraph::HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v,
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]909 ArenaBitVector* live_in_v, int dalvik_reg_id) {
buzbee862a7602013-04-05 10:58:54 -0700[diff] [blame]910 use_v->SetBit(dalvik_reg_id);
911 if (!def_v->IsBitSet(dalvik_reg_id)) {
912 live_in_v->SetBit(dalvik_reg_id);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]913 }
914}
915
916/* Mark a reg as being defined */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]917void MIRGraph::HandleDef(ArenaBitVector* def_v, int dalvik_reg_id) {
buzbee862a7602013-04-05 10:58:54 -0700[diff] [blame]918 def_v->SetBit(dalvik_reg_id);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]919}
920
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]921void MIRGraph::HandleExtended(ArenaBitVector* use_v, ArenaBitVector* def_v,
922 ArenaBitVector* live_in_v,
923 const MIR::DecodedInstruction& d_insn) {
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]924 // For vector MIRs, vC contains type information
925 bool is_vector_type_wide = false;
926 int type_size = d_insn.vC >> 16;
927 if (type_size == k64 || type_size == kDouble) {
928 is_vector_type_wide = true;
929 }
930
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]931 switch (static_cast<int>(d_insn.opcode)) {
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]932 case kMirOpPackedAddReduce:
933 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vA);
934 if (is_vector_type_wide == true) {
935 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vA + 1);
936 }
937 HandleDef(def_v, d_insn.vA);
938 if (is_vector_type_wide == true) {
939 HandleDef(def_v, d_insn.vA + 1);
940 }
941 break;
942 case kMirOpPackedReduce:
943 HandleDef(def_v, d_insn.vA);
944 if (is_vector_type_wide == true) {
945 HandleDef(def_v, d_insn.vA + 1);
946 }
947 break;
948 case kMirOpPackedSet:
949 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vB);
950 if (is_vector_type_wide == true) {
951 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vB + 1);
952 }
953 break;
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]954 default:
955 LOG(ERROR) << "Unexpected Extended Opcode " << d_insn.opcode;
956 break;
957 }
958}
959
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]960/*
961 * Find out live-in variables for natural loops. Variables that are live-in in
962 * the main loop body are considered to be defined in the entry block.
963 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]964bool MIRGraph::FindLocalLiveIn(BasicBlock* bb) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]965 MIR* mir;
966 ArenaBitVector *use_v, *def_v, *live_in_v;
967
968 if (bb->data_flow_info == NULL) return false;
969
970 use_v = bb->data_flow_info->use_v =
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]971 new (arena_) ArenaBitVector(arena_, GetNumOfCodeAndTempVRs(), false, kBitMapUse);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]972 def_v = bb->data_flow_info->def_v =
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]973 new (arena_) ArenaBitVector(arena_, GetNumOfCodeAndTempVRs(), false, kBitMapDef);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]974 live_in_v = bb->data_flow_info->live_in_v =
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]975 new (arena_) ArenaBitVector(arena_, GetNumOfCodeAndTempVRs(), false, kBitMapLiveIn);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]976
977 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
Jean Christophe Beylercc794c32014-05-02 09:34:13 -0700[diff] [blame]978 uint64_t df_attributes = GetDataFlowAttributes(mir);
Ian Rogers29a26482014-05-02 15:27:29 -0700[diff] [blame]979 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]980
981 if (df_attributes & DF_HAS_USES) {
982 if (df_attributes & DF_UA) {
983 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vA);
984 if (df_attributes & DF_A_WIDE) {
985 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vA+1);
986 }
987 }
988 if (df_attributes & DF_UB) {
989 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vB);
990 if (df_attributes & DF_B_WIDE) {
991 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vB+1);
992 }
993 }
994 if (df_attributes & DF_UC) {
995 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC);
996 if (df_attributes & DF_C_WIDE) {
997 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC+1);
998 }
999 }
1000 }
1001 if (df_attributes & DF_FORMAT_35C) {
1002 for (unsigned int i = 0; i < d_insn->vA; i++) {
1003 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->arg[i]);
1004 }
1005 }
1006 if (df_attributes & DF_FORMAT_3RC) {
1007 for (unsigned int i = 0; i < d_insn->vA; i++) {
1008 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC+i);
1009 }
1010 }
1011 if (df_attributes & DF_HAS_DEFS) {
1012 HandleDef(def_v, d_insn->vA);
1013 if (df_attributes & DF_A_WIDE) {
1014 HandleDef(def_v, d_insn->vA+1);
1015 }
1016 }
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]1017 if (df_attributes & DF_FORMAT_EXTENDED) {
1018 HandleExtended(use_v, def_v, live_in_v, mir->dalvikInsn);
1019 }
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1020 }
1021 return true;
1022}
1023
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1024int MIRGraph::AddNewSReg(int v_reg) {
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1025 int subscript = ++ssa_last_defs_[v_reg];
Mark Mendell0add77a2014-05-05 22:28:55 -0400[diff] [blame]1026 uint32_t ssa_reg = GetNumSSARegs();
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1027 SetNumSSARegs(ssa_reg + 1);
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1028 ssa_base_vregs_.push_back(v_reg);
1029 ssa_subscripts_.push_back(subscript);
1030 DCHECK_EQ(ssa_base_vregs_.size(), ssa_subscripts_.size());
Mark Mendell0add77a2014-05-05 22:28:55 -0400[diff] [blame]1031 // If we are expanding very late, update use counts too.
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1032 if (ssa_reg > 0 && use_counts_.size() == ssa_reg) {
Mark Mendell0add77a2014-05-05 22:28:55 -0400[diff] [blame]1033 // Need to expand the counts.
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1034 use_counts_.push_back(0);
1035 raw_use_counts_.push_back(0);
Mark Mendell0add77a2014-05-05 22:28:55 -0400[diff] [blame]1036 }
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1037 return ssa_reg;
1038}
1039
1040/* Find out the latest SSA register for a given Dalvik register */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1041void MIRGraph::HandleSSAUse(int* uses, int dalvik_reg, int reg_index) {
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1042 DCHECK((dalvik_reg >= 0) && (dalvik_reg < static_cast<int>(GetNumOfCodeAndTempVRs())));
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1043 uses[reg_index] = vreg_to_ssa_map_[dalvik_reg];
1044}
1045
1046/* Setup a new SSA register for a given Dalvik register */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1047void MIRGraph::HandleSSADef(int* defs, int dalvik_reg, int reg_index) {
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1048 DCHECK((dalvik_reg >= 0) && (dalvik_reg < static_cast<int>(GetNumOfCodeAndTempVRs())));
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1049 int ssa_reg = AddNewSReg(dalvik_reg);
1050 vreg_to_ssa_map_[dalvik_reg] = ssa_reg;
1051 defs[reg_index] = ssa_reg;
1052}
1053
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1054void MIRGraph::AllocateSSAUseData(MIR *mir, int num_uses) {
1055 mir->ssa_rep->num_uses = num_uses;
1056
1057 if (mir->ssa_rep->num_uses_allocated < num_uses) {
1058 mir->ssa_rep->uses = static_cast<int*>(arena_->Alloc(sizeof(int) * num_uses, kArenaAllocDFInfo));
1059 // NOTE: will be filled in during type & size inference pass
1060 mir->ssa_rep->fp_use = static_cast<bool*>(arena_->Alloc(sizeof(bool) * num_uses, kArenaAllocDFInfo));
1061 }
1062}
1063
1064void MIRGraph::AllocateSSADefData(MIR *mir, int num_defs) {
1065 mir->ssa_rep->num_defs = num_defs;
1066
1067 if (mir->ssa_rep->num_defs_allocated < num_defs) {
1068 mir->ssa_rep->defs = static_cast<int*>(arena_->Alloc(sizeof(int) * num_defs,
1069 kArenaAllocDFInfo));
1070 mir->ssa_rep->fp_def = static_cast<bool*>(arena_->Alloc(sizeof(bool) * num_defs,
1071 kArenaAllocDFInfo));
1072 }
1073}
1074
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1075/* Look up new SSA names for format_35c instructions */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1076void MIRGraph::DataFlowSSAFormat35C(MIR* mir) {
Ian Rogers29a26482014-05-02 15:27:29 -0700[diff] [blame]1077 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1078 int num_uses = d_insn->vA;
1079 int i;
1080
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1081 AllocateSSAUseData(mir, num_uses);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1082
1083 for (i = 0; i < num_uses; i++) {
1084 HandleSSAUse(mir->ssa_rep->uses, d_insn->arg[i], i);
1085 }
1086}
1087
1088/* Look up new SSA names for format_3rc instructions */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1089void MIRGraph::DataFlowSSAFormat3RC(MIR* mir) {
Ian Rogers29a26482014-05-02 15:27:29 -0700[diff] [blame]1090 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1091 int num_uses = d_insn->vA;
1092 int i;
1093
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1094 AllocateSSAUseData(mir, num_uses);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1095
1096 for (i = 0; i < num_uses; i++) {
1097 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC+i, i);
1098 }
1099}
1100
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]1101void MIRGraph::DataFlowSSAFormatExtended(MIR* mir) {
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]1102 const MIR::DecodedInstruction& d_insn = mir->dalvikInsn;
1103 // For vector MIRs, vC contains type information
1104 bool is_vector_type_wide = false;
1105 int type_size = d_insn.vC >> 16;
1106 if (type_size == k64 || type_size == kDouble) {
1107 is_vector_type_wide = true;
1108 }
1109
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]1110 switch (static_cast<int>(mir->dalvikInsn.opcode)) {
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]1111 case kMirOpPackedAddReduce:
1112 // We have one use, plus one more for wide
1113 AllocateSSAUseData(mir, is_vector_type_wide ? 2 : 1);
1114 HandleSSAUse(mir->ssa_rep->uses, d_insn.vA, 0);
1115 if (is_vector_type_wide == true) {
1116 HandleSSAUse(mir->ssa_rep->uses, d_insn.vA + 1, 1);
1117 }
1118
1119 // We have a def, plus one more for wide
1120 AllocateSSADefData(mir, is_vector_type_wide ? 2 : 1);
1121 HandleSSADef(mir->ssa_rep->defs, d_insn.vA, 0);
1122 if (is_vector_type_wide == true) {
1123 HandleSSADef(mir->ssa_rep->defs, d_insn.vA + 1, 1);
1124 }
1125 break;
1126 case kMirOpPackedReduce:
1127 // We have a def, plus one more for wide
1128 AllocateSSADefData(mir, is_vector_type_wide ? 2 : 1);
1129 HandleSSADef(mir->ssa_rep->defs, d_insn.vA, 0);
1130 if (is_vector_type_wide == true) {
1131 HandleSSADef(mir->ssa_rep->defs, d_insn.vA + 1, 1);
1132 }
1133 break;
1134 case kMirOpPackedSet:
1135 // We have one use, plus one more for wide
1136 AllocateSSAUseData(mir, is_vector_type_wide ? 2 : 1);
1137 HandleSSAUse(mir->ssa_rep->uses, d_insn.vB, 0);
1138 if (is_vector_type_wide == true) {
1139 HandleSSAUse(mir->ssa_rep->uses, d_insn.vB + 1, 1);
1140 }
1141 break;
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]1142 default:
1143 LOG(ERROR) << "Missing case for extended MIR: " << mir->dalvikInsn.opcode;
1144 break;
1145 }
1146}
1147
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1148/* Entry function to convert a block into SSA representation */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1149bool MIRGraph::DoSSAConversion(BasicBlock* bb) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1150 MIR* mir;
1151
1152 if (bb->data_flow_info == NULL) return false;
1153
1154 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
buzbee862a7602013-04-05 10:58:54 -0700[diff] [blame]1155 mir->ssa_rep =
Mathieu Chartierf6c4b3b2013-08-24 16:11:37 -0700[diff] [blame]1156 static_cast<struct SSARepresentation *>(arena_->Alloc(sizeof(SSARepresentation),
Vladimir Marko83cc7ae2014-02-12 18:02:05 +0000[diff] [blame]1157 kArenaAllocDFInfo));
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1158 memset(mir->ssa_rep, 0, sizeof(*mir->ssa_rep));
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1159
Jean Christophe Beylercc794c32014-05-02 09:34:13 -0700[diff] [blame]1160 uint64_t df_attributes = GetDataFlowAttributes(mir);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1161
1162 // If not a pseudo-op, note non-leaf or can throw
Jean Christophe Beyler2ab40eb2014-06-02 09:03:14 -0700[diff] [blame]1163 if (!MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) {
Jean Christophe Beylerfb0ea2d2014-07-29 13:20:42 -0700[diff] [blame]1164 int flags = mir->dalvikInsn.FlagsOf();
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1165
Vladimir Markoff0ac472014-10-02 17:24:53 +0100[diff] [blame]1166 if ((flags & Instruction::kInvoke) != 0) {
buzbee1fd33462013-03-25 13:40:45 -0700[diff] [blame]1167 attributes_ &= ~METHOD_IS_LEAF;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1168 }
1169 }
1170
1171 int num_uses = 0;
1172
1173 if (df_attributes & DF_FORMAT_35C) {
1174 DataFlowSSAFormat35C(mir);
1175 continue;
1176 }
1177
1178 if (df_attributes & DF_FORMAT_3RC) {
1179 DataFlowSSAFormat3RC(mir);
1180 continue;
1181 }
1182
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]1183 if (df_attributes & DF_FORMAT_EXTENDED) {
1184 DataFlowSSAFormatExtended(mir);
1185 continue;
1186 }
1187
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1188 if (df_attributes & DF_HAS_USES) {
1189 if (df_attributes & DF_UA) {
1190 num_uses++;
1191 if (df_attributes & DF_A_WIDE) {
Brian Carlstrom38f85e42013-07-18 14:45:22 -0700[diff] [blame]1192 num_uses++;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1193 }
1194 }
1195 if (df_attributes & DF_UB) {
1196 num_uses++;
1197 if (df_attributes & DF_B_WIDE) {
Brian Carlstrom38f85e42013-07-18 14:45:22 -0700[diff] [blame]1198 num_uses++;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1199 }
1200 }
1201 if (df_attributes & DF_UC) {
1202 num_uses++;
1203 if (df_attributes & DF_C_WIDE) {
Brian Carlstrom38f85e42013-07-18 14:45:22 -0700[diff] [blame]1204 num_uses++;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1205 }
1206 }
1207 }
1208
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1209 AllocateSSAUseData(mir, num_uses);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1210
1211 int num_defs = 0;
1212
1213 if (df_attributes & DF_HAS_DEFS) {
1214 num_defs++;
1215 if (df_attributes & DF_A_WIDE) {
1216 num_defs++;
1217 }
1218 }
1219
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1220 AllocateSSADefData(mir, num_defs);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1221
Ian Rogers29a26482014-05-02 15:27:29 -0700[diff] [blame]1222 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1223
1224 if (df_attributes & DF_HAS_USES) {
1225 num_uses = 0;
1226 if (df_attributes & DF_UA) {
1227 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_A;
1228 HandleSSAUse(mir->ssa_rep->uses, d_insn->vA, num_uses++);
1229 if (df_attributes & DF_A_WIDE) {
1230 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_A;
1231 HandleSSAUse(mir->ssa_rep->uses, d_insn->vA+1, num_uses++);
1232 }
1233 }
1234 if (df_attributes & DF_UB) {
1235 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_B;
1236 HandleSSAUse(mir->ssa_rep->uses, d_insn->vB, num_uses++);
1237 if (df_attributes & DF_B_WIDE) {
1238 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_B;
1239 HandleSSAUse(mir->ssa_rep->uses, d_insn->vB+1, num_uses++);
1240 }
1241 }
1242 if (df_attributes & DF_UC) {
1243 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_C;
1244 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC, num_uses++);
1245 if (df_attributes & DF_C_WIDE) {
1246 mir->ssa_rep->fp_use[num_uses] = df_attributes & DF_FP_C;
1247 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC+1, num_uses++);
1248 }
1249 }
1250 }
1251 if (df_attributes & DF_HAS_DEFS) {
1252 mir->ssa_rep->fp_def[0] = df_attributes & DF_FP_A;
1253 HandleSSADef(mir->ssa_rep->defs, d_insn->vA, 0);
1254 if (df_attributes & DF_A_WIDE) {
1255 mir->ssa_rep->fp_def[1] = df_attributes & DF_FP_A;
1256 HandleSSADef(mir->ssa_rep->defs, d_insn->vA+1, 1);
1257 }
1258 }
1259 }
1260
buzbee1fd33462013-03-25 13:40:45 -0700[diff] [blame]1261 /*
1262 * Take a snapshot of Dalvik->SSA mapping at the end of each block. The
1263 * input to PHI nodes can be derived from the snapshot of all
1264 * predecessor blocks.
1265 */
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1266 bb->data_flow_info->vreg_to_ssa_map_exit =
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1267 static_cast<int*>(arena_->Alloc(sizeof(int) * GetNumOfCodeAndTempVRs(),
Vladimir Marko83cc7ae2014-02-12 18:02:05 +0000[diff] [blame]1268 kArenaAllocDFInfo));
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1269
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1270 memcpy(bb->data_flow_info->vreg_to_ssa_map_exit, vreg_to_ssa_map_,
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1271 sizeof(int) * GetNumOfCodeAndTempVRs());
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1272 return true;
1273}
1274
Razvan A Lupusoru6f4dcae2014-09-29 11:59:12 -0700[diff] [blame]1275void MIRGraph::InitializeBasicBlockDataFlow() {
1276 /*
1277 * Allocate the BasicBlockDataFlow structure for the entry and code blocks.
1278 */
1279 for (BasicBlock* bb : block_list_) {
1280 if (bb->hidden == true) continue;
1281 if (bb->block_type == kDalvikByteCode ||
1282 bb->block_type == kEntryBlock ||
1283 bb->block_type == kExitBlock) {
1284 bb->data_flow_info =
1285 static_cast<BasicBlockDataFlow*>(arena_->Alloc(sizeof(BasicBlockDataFlow),
1286 kArenaAllocDFInfo));
1287 }
1288 }
1289}
1290
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1291/* Setup the basic data structures for SSA conversion */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1292void MIRGraph::CompilerInitializeSSAConversion() {
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1293 size_t num_reg = GetNumOfCodeAndTempVRs();
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1294
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1295 ssa_base_vregs_.clear();
1296 ssa_base_vregs_.reserve(num_reg + GetDefCount() + 128);
1297 ssa_subscripts_.clear();
1298 ssa_subscripts_.reserve(num_reg + GetDefCount() + 128);
1299
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1300 /*
1301 * Initial number of SSA registers is equal to the number of Dalvik
1302 * registers.
1303 */
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1304 SetNumSSARegs(num_reg);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1305
1306 /*
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1307 * Initialize the SSA2Dalvik map list. For the first num_reg elements,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1308 * the subscript is 0 so we use the ENCODE_REG_SUB macro to encode the value
1309 * into "(0 << 16) | i"
1310 */
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1311 for (unsigned int i = 0; i < num_reg; i++) {
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1312 ssa_base_vregs_.push_back(i);
1313 ssa_subscripts_.push_back(0);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1314 }
1315
1316 /*
1317 * Initialize the DalvikToSSAMap map. There is one entry for each
1318 * Dalvik register, and the SSA names for those are the same.
1319 */
1320 vreg_to_ssa_map_ =
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1321 static_cast<int*>(arena_->Alloc(sizeof(int) * num_reg,
Vladimir Marko83cc7ae2014-02-12 18:02:05 +0000[diff] [blame]1322 kArenaAllocDFInfo));
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1323 /* Keep track of the higest def for each dalvik reg */
1324 ssa_last_defs_ =
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1325 static_cast<int*>(arena_->Alloc(sizeof(int) * num_reg,
Vladimir Marko83cc7ae2014-02-12 18:02:05 +0000[diff] [blame]1326 kArenaAllocDFInfo));
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1327
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1328 for (unsigned int i = 0; i < num_reg; i++) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1329 vreg_to_ssa_map_[i] = i;
1330 ssa_last_defs_[i] = 0;
1331 }
1332
Razvan A Lupusoruda7a69b2014-01-08 15:09:50 -0800[diff] [blame]1333 // Create a compiler temporary for Method*. This is done after SSA initialization.
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1334 CompilerTemp* method_temp = GetNewCompilerTemp(kCompilerTempSpecialMethodPtr, false);
1335 // The MIR graph keeps track of the sreg for method pointer specially, so record that now.
1336 method_sreg_ = method_temp->s_reg_low;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1337
Razvan A Lupusoru6f4dcae2014-09-29 11:59:12 -0700[diff] [blame]1338 InitializeBasicBlockDataFlow();
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1339}
1340
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1341/*
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1342 * Count uses, weighting by loop nesting depth. This code only
1343 * counts explicitly used s_regs. A later phase will add implicit
1344 * counts for things such as Method*, null-checked references, etc.
1345 */
Vladimir Marko8b858e12014-11-27 14:52:37 +0000[diff] [blame^]1346void MIRGraph::CountUses(BasicBlock* bb) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1347 if (bb->block_type != kDalvikByteCode) {
Jean Christophe Beyler4e97c532014-01-07 10:07:18 -0800[diff] [blame]1348 return;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1349 }
buzbee1da1e2f2013-11-15 13:37:01 -0800[diff] [blame]1350 // Each level of nesting adds *100 to count, up to 3 levels deep.
1351 uint32_t depth = std::min(3U, static_cast<uint32_t>(bb->nesting_depth));
1352 uint32_t weight = std::max(1U, depth * 100);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1353 for (MIR* mir = bb->first_mir_insn; (mir != NULL); mir = mir->next) {
1354 if (mir->ssa_rep == NULL) {
1355 continue;
1356 }
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1357 for (int i = 0; i < mir->ssa_rep->num_uses; i++) {
1358 int s_reg = mir->ssa_rep->uses[i];
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1359 raw_use_counts_[s_reg] += 1u;
1360 use_counts_[s_reg] += weight;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1361 }
1362 if (!(cu_->disable_opt & (1 << kPromoteCompilerTemps))) {
Jean Christophe Beylercc794c32014-05-02 09:34:13 -0700[diff] [blame]1363 uint64_t df_attributes = GetDataFlowAttributes(mir);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1364 // Implicit use of Method* ? */
1365 if (df_attributes & DF_UMS) {
1366 /*
1367 * Some invokes will not use Method* - need to perform test similar
1368 * to that found in GenInvoke() to decide whether to count refs
buzbee1da1e2f2013-11-15 13:37:01 -0800[diff] [blame]1369 * for Method* on invoke-class opcodes. This is a relatively expensive
1370 * operation, so should only be done once.
1371 * TODO: refactor InvokeUsesMethodStar() to perform check at parse time,
1372 * and save results for both here and GenInvoke. For now, go ahead
1373 * and assume all invokes use method*.
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1374 */
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1375 raw_use_counts_[method_sreg_] += 1u;
1376 use_counts_[method_sreg_] += weight;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1377 }
1378 }
1379 }
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1380}
1381
1382/* Verify if all the successor is connected with all the claimed predecessors */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1383bool MIRGraph::VerifyPredInfo(BasicBlock* bb) {
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1384 for (BasicBlockId pred_id : bb->predecessors) {
1385 BasicBlock* pred_bb = GetBasicBlock(pred_id);
1386 DCHECK(pred_bb != nullptr);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1387 bool found = false;
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1388 if (pred_bb->taken == bb->id) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1389 found = true;
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1390 } else if (pred_bb->fall_through == bb->id) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1391 found = true;
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1392 } else if (pred_bb->successor_block_list_type != kNotUsed) {
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1393 for (SuccessorBlockInfo* successor_block_info : pred_bb->successor_blocks) {
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1394 BasicBlockId succ_bb = successor_block_info->block;
1395 if (succ_bb == bb->id) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1396 found = true;
1397 break;
1398 }
1399 }
1400 }
1401 if (found == false) {
1402 char block_name1[BLOCK_NAME_LEN], block_name2[BLOCK_NAME_LEN];
1403 GetBlockName(bb, block_name1);
1404 GetBlockName(pred_bb, block_name2);
1405 DumpCFG("/sdcard/cfg/", false);
Vladimir Marko312eb252014-10-07 15:01:57 +0100[diff] [blame]1406 LOG(FATAL) << "Successor " << block_name1 << " not found from "
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1407 << block_name2;
1408 }
1409 }
1410 return true;
1411}
1412
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1413void MIRGraph::VerifyDataflow() {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1414 /* Verify if all blocks are connected as claimed */
buzbee56c71782013-09-05 17:13:19 -0700[diff] [blame]1415 AllNodesIterator iter(this);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1416 for (BasicBlock* bb = iter.Next(); bb != NULL; bb = iter.Next()) {
1417 VerifyPredInfo(bb);
1418 }
1419}
1420
1421} // namespace art