commit df62950e7a32031b82360c407d46a37b94188fbb
author Brian Carlstrom <bdc@google.com> Wed Jul 17 22:39:56 2013 -0700
committer Brian Carlstrom <bdc@google.com> Thu Jul 18 00:13:18 2013 -0700
tree 038bf95a2ce296ae3e0c30a131ac22c0986f0f52
parent 0cd7ec2dcd8d7ba30bf3ca420b40dac52849876c

Fix cpplint whitespace/parens issues

Change-Id: Ifc678d59a8bed24ffddde5a0e543620b17b0aba9

compiler/dex/quick/mips/utility_mips.cc

diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc
index 8510006..127d191 100644
--- a/compiler/dex/quick/mips/utility_mips.cc
+++ b/compiler/dex/quick/mips/utility_mips.cc
@@ -107,7 +107,7 @@
 }
 
 LIR* MipsMir2Lir::OpUnconditionalBranch(LIR* target) {
-  LIR* res = NewLIR1(kMipsB, 0 /* offset to be patched during assembly*/ );
+  LIR* res = NewLIR1(kMipsB, 0 /* offset to be patched during assembly*/);
   res->target = target;
   return res;
 }
@@ -642,8 +642,8 @@
   return NULL;
 }
 
-LIR* MipsMir2Lir::StoreBaseIndexedDisp( int rBase, int r_index, int scale, int displacement,
-                                        int r_src, int r_src_hi, OpSize size, int s_reg) {
+LIR* MipsMir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
+                                       int r_src, int r_src_hi, OpSize size, int s_reg) {
   LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for MIPS";
   return NULL;
 }