Fix cpplint whitespace/parens issues
Change-Id: Ifc678d59a8bed24ffddde5a0e543620b17b0aba9
diff --git a/compiler/dex/arena_bit_vector.h b/compiler/dex/arena_bit_vector.h
index de30859..2a05b77 100644
--- a/compiler/dex/arena_bit_vector.h
+++ b/compiler/dex/arena_bit_vector.h
@@ -83,7 +83,7 @@
OatBitMapKind kind = kBitMapMisc);
~ArenaBitVector() {};
- static void* operator new( size_t size, ArenaAllocator* arena) {
+ static void* operator new(size_t size, ArenaAllocator* arena) {
return arena->NewMem(sizeof(ArenaBitVector), true, ArenaAllocator::kAllocGrowableBitMap);
}
static void operator delete(void* p) {}; // Nop.
diff --git a/compiler/dex/dataflow_iterator.h b/compiler/dex/dataflow_iterator.h
index e427862..847a614 100644
--- a/compiler/dex/dataflow_iterator.h
+++ b/compiler/dex/dataflow_iterator.h
@@ -137,7 +137,7 @@
AllNodesIterator(MIRGraph* mir_graph, bool is_iterative)
: DataflowIterator(mir_graph, is_iterative, 0, 0, false) {
all_nodes_iterator_ =
- new (mir_graph->GetArena()) GrowableArray<BasicBlock*>::Iterator (mir_graph->GetBlockList());
+ new (mir_graph->GetArena()) GrowableArray<BasicBlock*>::Iterator(mir_graph->GetBlockList());
}
void Reset() {
diff --git a/compiler/dex/frontend.cc b/compiler/dex/frontend.cc
index 0803914..ae160d6 100644
--- a/compiler/dex/frontend.cc
+++ b/compiler/dex/frontend.cc
@@ -53,7 +53,7 @@
llvm_module_ = new ::llvm::Module("art", *llvm_context_);
::llvm::StructType::create(*llvm_context_, "JavaObject");
art::llvm::makeLLVMModuleContents(llvm_module_);
- intrinsic_helper_.reset( new art::llvm::IntrinsicHelper(*llvm_context_, *llvm_module_));
+ intrinsic_helper_.reset(new art::llvm::IntrinsicHelper(*llvm_context_, *llvm_module_));
ir_builder_.reset(new art::llvm::IRBuilder(*llvm_context_, *llvm_module_, *intrinsic_helper_));
}
@@ -276,7 +276,7 @@
#if defined(ART_USE_PORTABLE_COMPILER)
, llvm_compilation_unit
#endif
- );
+ ); // NOLINT(whitespace/parens)
}
} // namespace art
diff --git a/compiler/dex/mir_dataflow.cc b/compiler/dex/mir_dataflow.cc
index 9632388..be19d5a 100644
--- a/compiler/dex/mir_dataflow.cc
+++ b/compiler/dex/mir_dataflow.cc
@@ -1122,9 +1122,9 @@
size_t num_dalvik_reg = cu_->num_dalvik_registers;
ssa_base_vregs_ = new (arena_) GrowableArray<int>(arena_, num_dalvik_reg + GetDefCount() + 128,
- kGrowableArraySSAtoDalvikMap);
+ kGrowableArraySSAtoDalvikMap);
ssa_subscripts_ = new (arena_) GrowableArray<int>(arena_, num_dalvik_reg + GetDefCount() + 128,
- kGrowableArraySSAtoDalvikMap);
+ kGrowableArraySSAtoDalvikMap);
/*
* Initial number of SSA registers is equal to the number of Dalvik
* registers.
diff --git a/compiler/dex/mir_graph.cc b/compiler/dex/mir_graph.cc
index 0b3fa46..634c576 100644
--- a/compiler/dex/mir_graph.cc
+++ b/compiler/dex/mir_graph.cc
@@ -410,7 +410,7 @@
(insn->dalvikInsn.opcode == Instruction::PACKED_SWITCH) ?
kPackedSwitch : kSparseSwitch;
cur_block->successor_block_list.blocks =
- new (arena_)GrowableArray<SuccessorBlockInfo*>(arena_, size, kGrowableArraySuccessorBlocks);
+ new (arena_) GrowableArray<SuccessorBlockInfo*>(arena_, size, kGrowableArraySuccessorBlocks);
for (i = 0; i < size; i++) {
BasicBlock *case_block = FindBlock(cur_offset + target_table[i], /* split */ true,
@@ -427,8 +427,8 @@
}
/* Fall-through case */
- BasicBlock* fallthrough_block = FindBlock( cur_offset + width, /* split */ false,
- /* create */ true, /* immed_pred_block_p */ NULL);
+ BasicBlock* fallthrough_block = FindBlock(cur_offset + width, /* split */ false,
+ /* create */ true, /* immed_pred_block_p */ NULL);
cur_block->fall_through = fallthrough_block;
fallthrough_block->predecessors->Insert(cur_block);
}
@@ -1146,8 +1146,9 @@
bb->block_type = block_type;
bb->id = block_id;
// TUNING: better estimate of the exit block predecessors?
- bb->predecessors = new (arena_)
- GrowableArray<BasicBlock*>(arena_, (block_type == kExitBlock) ? 2048 : 2, kGrowableArrayPredecessors);
+ bb->predecessors = new (arena_) GrowableArray<BasicBlock*>(arena_,
+ (block_type == kExitBlock) ? 2048 : 2,
+ kGrowableArrayPredecessors);
bb->successor_block_list.block_list_type = kNotUsed;
block_id_map_.Put(block_id, block_id);
return bb;
diff --git a/compiler/dex/mir_optimization.cc b/compiler/dex/mir_optimization.cc
index 882b81a..f83bbb2 100644
--- a/compiler/dex/mir_optimization.cc
+++ b/compiler/dex/mir_optimization.cc
@@ -228,7 +228,7 @@
MIR* mir_next = mir->next;
Instruction::Code br_opcode = mir_next->dalvikInsn.opcode;
ConditionCode ccode = kCondNv;
- switch(br_opcode) {
+ switch (br_opcode) {
case Instruction::IF_EQZ:
ccode = kCondEq;
break;
@@ -255,7 +255,7 @@
(mir->ssa_rep->defs[0] == mir_next->ssa_rep->uses[0]) &&
(GetSSAUseCount(mir->ssa_rep->defs[0]) == 1)) {
mir_next->dalvikInsn.arg[0] = ccode;
- switch(opcode) {
+ switch (opcode) {
case Instruction::CMPL_FLOAT:
mir_next->dalvikInsn.opcode =
static_cast<Instruction::Code>(kMirOpFusedCmplFloat);
diff --git a/compiler/dex/portable/mir_to_gbc.cc b/compiler/dex/portable/mir_to_gbc.cc
index cfd3daf..85ffec5 100644
--- a/compiler/dex/portable/mir_to_gbc.cc
+++ b/compiler/dex/portable/mir_to_gbc.cc
@@ -297,7 +297,7 @@
::llvm::Value* src1, ::llvm::Value* src2) {
::llvm::Value* res = NULL;
DCHECK_EQ(src1->getType(), src2->getType());
- switch(cc) {
+ switch (cc) {
case kCondEq: res = irb_->CreateICmpEQ(src1, src2); break;
case kCondNe: res = irb_->CreateICmpNE(src1, src2); break;
case kCondLt: res = irb_->CreateICmpSLT(src1, src2); break;
@@ -369,7 +369,7 @@
::llvm::Value* MirConverter::GenArithOp(OpKind op, bool is_long,
::llvm::Value* src1, ::llvm::Value* src2) {
::llvm::Value* res = NULL;
- switch(op) {
+ switch (op) {
case kOpAdd: res = irb_->CreateAdd(src1, src2); break;
case kOpSub: res = irb_->CreateSub(src1, src2); break;
case kOpRsub: res = irb_->CreateSub(src2, src1); break;
@@ -393,7 +393,7 @@
::llvm::Value* src1 = GetLLVMValue(rl_src1.orig_sreg);
::llvm::Value* src2 = GetLLVMValue(rl_src2.orig_sreg);
::llvm::Value* res = NULL;
- switch(op) {
+ switch (op) {
case kOpAdd: res = irb_->CreateFAdd(src1, src2); break;
case kOpSub: res = irb_->CreateFSub(src1, src2); break;
case kOpMul: res = irb_->CreateFMul(src1, src2); break;
@@ -1781,7 +1781,7 @@
* types (which is valid so long as we always do a real expansion of passed
* arguments and field loads).
*/
- switch(shorty_type) {
+ switch (shorty_type) {
case 'Z' : shorty_type = 'I'; break;
case 'B' : shorty_type = 'I'; break;
case 'S' : shorty_type = 'I'; break;
diff --git a/compiler/dex/quick/arm/fp_arm.cc b/compiler/dex/quick/arm/fp_arm.cc
index 2c626a0..8f73f0c 100644
--- a/compiler/dex/quick/arm/fp_arm.cc
+++ b/compiler/dex/quick/arm/fp_arm.cc
@@ -193,7 +193,7 @@
}
NewLIR0(kThumb2Fmstat);
ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]);
- switch(ccode) {
+ switch (ccode) {
case kCondEq:
case kCondNe:
break;
diff --git a/compiler/dex/quick/arm/int_arm.cc b/compiler/dex/quick/arm/int_arm.cc
index e12df6c..3a367c9 100644
--- a/compiler/dex/quick/arm/int_arm.cc
+++ b/compiler/dex/quick/arm/int_arm.cc
@@ -129,7 +129,7 @@
int32_t low_reg = rl_src1.low_reg;
int32_t high_reg = rl_src1.high_reg;
- switch(ccode) {
+ switch (ccode) {
case kCondEq:
case kCondNe:
LIR* target;
@@ -270,7 +270,7 @@
rl_src1 = LoadValueWide(rl_src1, kCoreReg);
rl_src2 = LoadValueWide(rl_src2, kCoreReg);
OpRegReg(kOpCmp, rl_src1.high_reg, rl_src2.high_reg);
- switch(ccode) {
+ switch (ccode) {
case kCondEq:
OpCondBranch(kCondNe, not_taken);
break;
@@ -436,7 +436,7 @@
int r_hi = AllocTemp();
int r_lo = AllocTemp();
NewLIR4(kThumb2Smull, r_lo, r_hi, r_magic, rl_src.low_reg);
- switch(pattern) {
+ switch (pattern) {
case Divide3:
OpRegRegRegShift(kOpSub, rl_result.low_reg, r_hi,
rl_src.low_reg, EncodeShift(kArmAsr, 31));
@@ -1002,7 +1002,7 @@
return;
}
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
- switch(opcode) {
+ switch (opcode) {
case Instruction::SHL_LONG:
case Instruction::SHL_LONG_2ADDR:
if (shift_amount == 1) {
@@ -1090,7 +1090,7 @@
int32_t mod_imm_hi = ModifiedImmediate(val_hi);
// Only a subset of add/sub immediate instructions set carry - so bail if we don't fit
- switch(opcode) {
+ switch (opcode) {
case Instruction::ADD_LONG:
case Instruction::ADD_LONG_2ADDR:
case Instruction::SUB_LONG:
diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc
index 80f597d..305a147 100644
--- a/compiler/dex/quick/arm/utility_arm.cc
+++ b/compiler/dex/quick/arm/utility_arm.cc
@@ -549,7 +549,7 @@
ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdd:
- if ( !neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */
+ if (!neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */
DCHECK_EQ((value & 0x3), 0);
return NewLIR1(kThumbAddSpI7, value >> 2);
} else if (short_form) {
diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc
index 8698b1f..7a59644 100644
--- a/compiler/dex/quick/codegen_util.cc
+++ b/compiler/dex/quick/codegen_util.cc
@@ -55,7 +55,7 @@
}
/* Convert an instruction to a NOP */
-void Mir2Lir::NopLIR( LIR* lir) {
+void Mir2Lir::NopLIR(LIR* lir) {
lir->flags.is_nop = true;
}
@@ -190,10 +190,10 @@
}
if (lir->use_mask && (!lir->flags.is_nop || dump_nop)) {
- DUMP_RESOURCE_MASK(DumpResourceMask((LIR* ) lir, lir->use_mask, "use"));
+ DUMP_RESOURCE_MASK(DumpResourceMask((LIR*) lir, lir->use_mask, "use"));
}
if (lir->def_mask && (!lir->flags.is_nop || dump_nop)) {
- DUMP_RESOURCE_MASK(DumpResourceMask((LIR* ) lir, lir->def_mask, "def"));
+ DUMP_RESOURCE_MASK(DumpResourceMask((LIR*) lir, lir->def_mask, "def"));
}
}
@@ -336,10 +336,10 @@
}
static void PushWord(std::vector<uint8_t>&buf, int data) {
- buf.push_back( data & 0xff);
- buf.push_back( (data >> 8) & 0xff);
- buf.push_back( (data >> 16) & 0xff);
- buf.push_back( (data >> 24) & 0xff);
+ buf.push_back(data & 0xff);
+ buf.push_back((data >> 8) & 0xff);
+ buf.push_back((data >> 16) & 0xff);
+ buf.push_back((data >> 24) & 0xff);
}
static void AlignBuffer(std::vector<uint8_t>&buf, size_t offset) {
@@ -454,8 +454,8 @@
if (tab_rec == NULL) break;
AlignBuffer(code_buffer_, tab_rec->offset);
for (int i = 0; i < (tab_rec->size + 1) / 2; i++) {
- code_buffer_.push_back( tab_rec->table[i] & 0xFF);
- code_buffer_.push_back( (tab_rec->table[i] >> 8) & 0xFF);
+ code_buffer_.push_back(tab_rec->table[i] & 0xFF);
+ code_buffer_.push_back((tab_rec->table[i] >> 8) & 0xFF);
}
}
}
diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc
index a34d2a9..d1bfd2d 100644
--- a/compiler/dex/quick/gen_common.cc
+++ b/compiler/dex/quick/gen_common.cc
@@ -279,7 +279,7 @@
int r_dst = AllocTemp();
int r_idx = AllocTemp();
int r_val = INVALID_REG;
- switch(cu_->instruction_set) {
+ switch (cu_->instruction_set) {
case kThumb2:
r_val = TargetReg(kLr);
break;
@@ -1311,7 +1311,7 @@
GenImmedCheck(kCondEq, TargetReg(kArg1), 0, kThrowDivZero);
}
// NOTE: callout here is not a safepoint
- CallHelper(r_tgt, func_offset, false /* not a safepoint */ );
+ CallHelper(r_tgt, func_offset, false /* not a safepoint */);
if (op == kOpDiv)
rl_result = GetReturn(false);
else
diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc
index 8510006..127d191 100644
--- a/compiler/dex/quick/mips/utility_mips.cc
+++ b/compiler/dex/quick/mips/utility_mips.cc
@@ -107,7 +107,7 @@
}
LIR* MipsMir2Lir::OpUnconditionalBranch(LIR* target) {
- LIR* res = NewLIR1(kMipsB, 0 /* offset to be patched during assembly*/ );
+ LIR* res = NewLIR1(kMipsB, 0 /* offset to be patched during assembly*/);
res->target = target;
return res;
}
@@ -642,8 +642,8 @@
return NULL;
}
-LIR* MipsMir2Lir::StoreBaseIndexedDisp( int rBase, int r_index, int scale, int displacement,
- int r_src, int r_src_hi, OpSize size, int s_reg) {
+LIR* MipsMir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
+ int r_src, int r_src_hi, OpSize size, int s_reg) {
LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for MIPS";
return NULL;
}
diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h
index 41e5a2d..7765eaa 100644
--- a/compiler/dex/quick/mir_to_lir.h
+++ b/compiler/dex/quick/mir_to_lir.h
@@ -233,7 +233,7 @@
RegisterClass oat_reg_class_by_size(OpSize size) {
return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte ||
- size == kSignedByte ) ? kCoreReg : kAnyReg;
+ size == kSignedByte) ? kCoreReg : kAnyReg;
}
size_t CodeBufferSizeInBytes() {
diff --git a/compiler/dex/quick/ralloc_util.cc b/compiler/dex/quick/ralloc_util.cc
index 4c91223..bc3740a 100644
--- a/compiler/dex/quick/ralloc_util.cc
+++ b/compiler/dex/quick/ralloc_util.cc
@@ -1021,8 +1021,7 @@
if (!(cu_->disable_opt & (1 << kPromoteRegs))) {
// Promote FpRegs
- for (int i = 0; (i < num_regs) &&
- (FpRegs[i].count >= promotion_threshold ); i++) {
+ for (int i = 0; (i < num_regs) && (FpRegs[i].count >= promotion_threshold); i++) {
int p_map_idx = SRegToPMap(FpRegs[i].s_reg);
if (promotion_map_[p_map_idx].fp_location != kLocPhysReg) {
int reg = AllocPreservedFPReg(FpRegs[i].s_reg,
diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc
index 6376e3b..75367a3 100644
--- a/compiler/dex/quick/x86/utility_x86.cc
+++ b/compiler/dex/quick/x86/utility_x86.cc
@@ -100,7 +100,7 @@
}
LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) {
- LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/ );
+ LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/);
res->target = target;
return res;
}
diff --git a/compiler/dex/ssa_transformation.cc b/compiler/dex/ssa_transformation.cc
index 3a0cbcc..7739e29 100644
--- a/compiler/dex/ssa_transformation.cc
+++ b/compiler/dex/ssa_transformation.cc
@@ -266,7 +266,7 @@
void MIRGraph::InitializeDominationInfo(BasicBlock* bb) {
int num_total_blocks = GetBasicBlockListCount();
- if (bb->dominators == NULL ) {
+ if (bb->dominators == NULL) {
bb->dominators = new (arena_) ArenaBitVector(arena_, num_total_blocks,
false /* expandable */, kBitMapDominators);
bb->i_dominated = new (arena_) ArenaBitVector(arena_, num_total_blocks,
diff --git a/compiler/dex/vreg_analysis.cc b/compiler/dex/vreg_analysis.cc
index 10bbd1f..f361dd7 100644
--- a/compiler/dex/vreg_analysis.cc
+++ b/compiler/dex/vreg_analysis.cc
@@ -160,7 +160,7 @@
if ((mir->dalvikInsn.opcode == Instruction::RETURN) ||
(mir->dalvikInsn.opcode == Instruction::RETURN_WIDE) ||
(mir->dalvikInsn.opcode == Instruction::RETURN_OBJECT)) {
- switch(cu_->shorty[0]) {
+ switch (cu_->shorty[0]) {
case 'I':
changed |= SetCore(ssa_rep->uses[0], true);
break;
diff --git a/compiler/llvm/llvm_compilation_unit.cc b/compiler/llvm/llvm_compilation_unit.cc
index 1f2b977..592059e 100644
--- a/compiler/llvm/llvm_compilation_unit.cc
+++ b/compiler/llvm/llvm_compilation_unit.cc
@@ -114,7 +114,7 @@
irb_.reset(new IRBuilder(*context_, *module_, *intrinsic_helper_));
// We always need a switch case, so just use a normal function.
- switch(GetInstructionSet()) {
+ switch (GetInstructionSet()) {
default:
runtime_support_.reset(new RuntimeSupportBuilder(*context_, *module_, *irb_));
break;
diff --git a/compiler/oat_writer.cc b/compiler/oat_writer.cc
index 4c32506..da05c49 100644
--- a/compiler/oat_writer.cc
+++ b/compiler/oat_writer.cc
@@ -399,8 +399,7 @@
fp_spill_mask,
mapping_table_offset,
vmap_table_offset,
- gc_map_offset
- );
+ gc_map_offset);
if (compiler_driver_->IsImage()) {
ClassLinker* linker = Runtime::Current()->GetClassLinker();