Fix cpplint whitespace/parens issues
Change-Id: Ifc678d59a8bed24ffddde5a0e543620b17b0aba9
diff --git a/compiler/dex/quick/arm/fp_arm.cc b/compiler/dex/quick/arm/fp_arm.cc
index 2c626a0..8f73f0c 100644
--- a/compiler/dex/quick/arm/fp_arm.cc
+++ b/compiler/dex/quick/arm/fp_arm.cc
@@ -193,7 +193,7 @@
}
NewLIR0(kThumb2Fmstat);
ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]);
- switch(ccode) {
+ switch (ccode) {
case kCondEq:
case kCondNe:
break;
diff --git a/compiler/dex/quick/arm/int_arm.cc b/compiler/dex/quick/arm/int_arm.cc
index e12df6c..3a367c9 100644
--- a/compiler/dex/quick/arm/int_arm.cc
+++ b/compiler/dex/quick/arm/int_arm.cc
@@ -129,7 +129,7 @@
int32_t low_reg = rl_src1.low_reg;
int32_t high_reg = rl_src1.high_reg;
- switch(ccode) {
+ switch (ccode) {
case kCondEq:
case kCondNe:
LIR* target;
@@ -270,7 +270,7 @@
rl_src1 = LoadValueWide(rl_src1, kCoreReg);
rl_src2 = LoadValueWide(rl_src2, kCoreReg);
OpRegReg(kOpCmp, rl_src1.high_reg, rl_src2.high_reg);
- switch(ccode) {
+ switch (ccode) {
case kCondEq:
OpCondBranch(kCondNe, not_taken);
break;
@@ -436,7 +436,7 @@
int r_hi = AllocTemp();
int r_lo = AllocTemp();
NewLIR4(kThumb2Smull, r_lo, r_hi, r_magic, rl_src.low_reg);
- switch(pattern) {
+ switch (pattern) {
case Divide3:
OpRegRegRegShift(kOpSub, rl_result.low_reg, r_hi,
rl_src.low_reg, EncodeShift(kArmAsr, 31));
@@ -1002,7 +1002,7 @@
return;
}
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
- switch(opcode) {
+ switch (opcode) {
case Instruction::SHL_LONG:
case Instruction::SHL_LONG_2ADDR:
if (shift_amount == 1) {
@@ -1090,7 +1090,7 @@
int32_t mod_imm_hi = ModifiedImmediate(val_hi);
// Only a subset of add/sub immediate instructions set carry - so bail if we don't fit
- switch(opcode) {
+ switch (opcode) {
case Instruction::ADD_LONG:
case Instruction::ADD_LONG_2ADDR:
case Instruction::SUB_LONG:
diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc
index 80f597d..305a147 100644
--- a/compiler/dex/quick/arm/utility_arm.cc
+++ b/compiler/dex/quick/arm/utility_arm.cc
@@ -549,7 +549,7 @@
ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdd:
- if ( !neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */
+ if (!neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */
DCHECK_EQ((value & 0x3), 0);
return NewLIR1(kThumbAddSpI7, value >> 2);
} else if (short_form) {
diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc
index 8698b1f..7a59644 100644
--- a/compiler/dex/quick/codegen_util.cc
+++ b/compiler/dex/quick/codegen_util.cc
@@ -55,7 +55,7 @@
}
/* Convert an instruction to a NOP */
-void Mir2Lir::NopLIR( LIR* lir) {
+void Mir2Lir::NopLIR(LIR* lir) {
lir->flags.is_nop = true;
}
@@ -190,10 +190,10 @@
}
if (lir->use_mask && (!lir->flags.is_nop || dump_nop)) {
- DUMP_RESOURCE_MASK(DumpResourceMask((LIR* ) lir, lir->use_mask, "use"));
+ DUMP_RESOURCE_MASK(DumpResourceMask((LIR*) lir, lir->use_mask, "use"));
}
if (lir->def_mask && (!lir->flags.is_nop || dump_nop)) {
- DUMP_RESOURCE_MASK(DumpResourceMask((LIR* ) lir, lir->def_mask, "def"));
+ DUMP_RESOURCE_MASK(DumpResourceMask((LIR*) lir, lir->def_mask, "def"));
}
}
@@ -336,10 +336,10 @@
}
static void PushWord(std::vector<uint8_t>&buf, int data) {
- buf.push_back( data & 0xff);
- buf.push_back( (data >> 8) & 0xff);
- buf.push_back( (data >> 16) & 0xff);
- buf.push_back( (data >> 24) & 0xff);
+ buf.push_back(data & 0xff);
+ buf.push_back((data >> 8) & 0xff);
+ buf.push_back((data >> 16) & 0xff);
+ buf.push_back((data >> 24) & 0xff);
}
static void AlignBuffer(std::vector<uint8_t>&buf, size_t offset) {
@@ -454,8 +454,8 @@
if (tab_rec == NULL) break;
AlignBuffer(code_buffer_, tab_rec->offset);
for (int i = 0; i < (tab_rec->size + 1) / 2; i++) {
- code_buffer_.push_back( tab_rec->table[i] & 0xFF);
- code_buffer_.push_back( (tab_rec->table[i] >> 8) & 0xFF);
+ code_buffer_.push_back(tab_rec->table[i] & 0xFF);
+ code_buffer_.push_back((tab_rec->table[i] >> 8) & 0xFF);
}
}
}
diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc
index a34d2a9..d1bfd2d 100644
--- a/compiler/dex/quick/gen_common.cc
+++ b/compiler/dex/quick/gen_common.cc
@@ -279,7 +279,7 @@
int r_dst = AllocTemp();
int r_idx = AllocTemp();
int r_val = INVALID_REG;
- switch(cu_->instruction_set) {
+ switch (cu_->instruction_set) {
case kThumb2:
r_val = TargetReg(kLr);
break;
@@ -1311,7 +1311,7 @@
GenImmedCheck(kCondEq, TargetReg(kArg1), 0, kThrowDivZero);
}
// NOTE: callout here is not a safepoint
- CallHelper(r_tgt, func_offset, false /* not a safepoint */ );
+ CallHelper(r_tgt, func_offset, false /* not a safepoint */);
if (op == kOpDiv)
rl_result = GetReturn(false);
else
diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc
index 8510006..127d191 100644
--- a/compiler/dex/quick/mips/utility_mips.cc
+++ b/compiler/dex/quick/mips/utility_mips.cc
@@ -107,7 +107,7 @@
}
LIR* MipsMir2Lir::OpUnconditionalBranch(LIR* target) {
- LIR* res = NewLIR1(kMipsB, 0 /* offset to be patched during assembly*/ );
+ LIR* res = NewLIR1(kMipsB, 0 /* offset to be patched during assembly*/);
res->target = target;
return res;
}
@@ -642,8 +642,8 @@
return NULL;
}
-LIR* MipsMir2Lir::StoreBaseIndexedDisp( int rBase, int r_index, int scale, int displacement,
- int r_src, int r_src_hi, OpSize size, int s_reg) {
+LIR* MipsMir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
+ int r_src, int r_src_hi, OpSize size, int s_reg) {
LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for MIPS";
return NULL;
}
diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h
index 41e5a2d..7765eaa 100644
--- a/compiler/dex/quick/mir_to_lir.h
+++ b/compiler/dex/quick/mir_to_lir.h
@@ -233,7 +233,7 @@
RegisterClass oat_reg_class_by_size(OpSize size) {
return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte ||
- size == kSignedByte ) ? kCoreReg : kAnyReg;
+ size == kSignedByte) ? kCoreReg : kAnyReg;
}
size_t CodeBufferSizeInBytes() {
diff --git a/compiler/dex/quick/ralloc_util.cc b/compiler/dex/quick/ralloc_util.cc
index 4c91223..bc3740a 100644
--- a/compiler/dex/quick/ralloc_util.cc
+++ b/compiler/dex/quick/ralloc_util.cc
@@ -1021,8 +1021,7 @@
if (!(cu_->disable_opt & (1 << kPromoteRegs))) {
// Promote FpRegs
- for (int i = 0; (i < num_regs) &&
- (FpRegs[i].count >= promotion_threshold ); i++) {
+ for (int i = 0; (i < num_regs) && (FpRegs[i].count >= promotion_threshold); i++) {
int p_map_idx = SRegToPMap(FpRegs[i].s_reg);
if (promotion_map_[p_map_idx].fp_location != kLocPhysReg) {
int reg = AllocPreservedFPReg(FpRegs[i].s_reg,
diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc
index 6376e3b..75367a3 100644
--- a/compiler/dex/quick/x86/utility_x86.cc
+++ b/compiler/dex/quick/x86/utility_x86.cc
@@ -100,7 +100,7 @@
}
LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) {
- LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/ );
+ LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/);
res->target = target;
return res;
}