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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
Kristen Accardi8cf4c192005-08-16 15:16:10 -070026 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 *
28 */
29
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
Tim Schmielaude259682006-01-08 01:02:05 -080033#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <linux/pci.h>
Andrew Morton5d1b8c92005-11-13 16:06:39 -080037#include <linux/interrupt.h>
Kristen Carlson Accardi34d03412007-01-09 13:02:36 -080038#include <linux/time.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090039#include <linux/slab.h>
Andrew Morton5d1b8c92005-11-13 16:06:39 -080040
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#include "../pci.h"
42#include "pciehp.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070043
Bjorn Helgaascd84d342013-05-09 11:26:16 -060044static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
Kenji Kaneshigea0f018d2006-12-21 17:01:06 -080045{
Bjorn Helgaascd84d342013-05-09 11:26:16 -060046 return ctrl->pcie->port;
Kenji Kaneshigea0f018d2006-12-21 17:01:06 -080047}
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080049static irqreturn_t pcie_isr(int irq, void *dev_id);
50static void start_int_poll_timer(struct controller *ctrl, int sec);
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
52/* This is the interrupt polling timeout function. */
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080053static void int_poll_timeout(unsigned long data)
Linus Torvalds1da177e2005-04-16 15:20:36 -070054{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080055 struct controller *ctrl = (struct controller *)data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
Linus Torvalds1da177e2005-04-16 15:20:36 -070057 /* Poll for interrupt events. regs == NULL => polling */
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080058 pcie_isr(0, ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080060 init_timer(&ctrl->poll_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 if (!pciehp_poll_time)
Kenji Kaneshige40730d12007-08-09 16:09:38 -070062 pciehp_poll_time = 2; /* default polling interval is 2 sec */
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080064 start_int_poll_timer(ctrl, pciehp_poll_time);
Linus Torvalds1da177e2005-04-16 15:20:36 -070065}
66
67/* This function starts the interrupt polling timer. */
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080068static void start_int_poll_timer(struct controller *ctrl, int sec)
Linus Torvalds1da177e2005-04-16 15:20:36 -070069{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080070 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
Bjorn Helgaasf7625982013-11-14 11:28:18 -070072 sec = 2;
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
Kenji Kaneshige48fe3912006-12-21 17:01:04 -080074 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070078}
79
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -070080static inline int pciehp_request_irq(struct controller *ctrl)
81{
Kenji Kaneshigef7a10e32008-08-22 17:16:48 +090082 int retval, irq = ctrl->pcie->irq;
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -070083
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
88 return 0;
89 }
90
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
93 if (retval)
Taku Izumi7f2feec2008-09-05 12:11:26 +090094 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
95 irq);
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -070096 return retval;
97}
98
99static inline void pciehp_free_irq(struct controller *ctrl)
100{
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
103 else
Kenji Kaneshigef7a10e32008-08-22 17:16:48 +0900104 free_irq(ctrl->pcie->irq, ctrl);
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700105}
106
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600107static int pcie_poll_cmd(struct controller *ctrl, int timeout)
Kenji Kaneshige6592e022008-05-27 19:05:26 +0900108{
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600109 struct pci_dev *pdev = ctrl_dev(ctrl);
Kenji Kaneshige6592e022008-05-27 19:05:26 +0900110 u16 slot_status;
Kenji Kaneshige6592e022008-05-27 19:05:26 +0900111
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700112 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
113 if (slot_status & PCI_EXP_SLTSTA_CC) {
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600114 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
115 PCI_EXP_SLTSTA_CC);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900116 return 1;
Kenji Kaneshige820943b2008-06-20 12:04:33 +0900117 }
Adrian Bunka5827f42008-08-28 01:05:26 +0300118 while (timeout > 0) {
Kenji Kaneshige66618ba2008-06-20 12:05:12 +0900119 msleep(10);
120 timeout -= 10;
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700121 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
122 if (slot_status & PCI_EXP_SLTSTA_CC) {
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600123 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
124 PCI_EXP_SLTSTA_CC);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900125 return 1;
Kenji Kaneshige820943b2008-06-20 12:04:33 +0900126 }
Kenji Kaneshige6592e022008-05-27 19:05:26 +0900127 }
128 return 0; /* timeout */
Kenji Kaneshige6592e022008-05-27 19:05:26 +0900129}
130
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600131static void pcie_wait_cmd(struct controller *ctrl)
Kenji Kaneshige44ef4ce2006-12-21 17:01:09 -0800132{
Kenji Kaneshige262303fe2006-12-21 17:01:10 -0800133 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600134 unsigned long duration = msecs_to_jiffies(msecs);
135 unsigned long cmd_timeout = ctrl->cmd_started + duration;
136 unsigned long now, timeout;
Kenji Kaneshige262303fe2006-12-21 17:01:10 -0800137 int rc;
Kenji Kaneshige44ef4ce2006-12-21 17:01:09 -0800138
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600139 /*
140 * If the controller does not generate notifications for command
141 * completions, we never need to wait between writes.
142 */
Rajat Jain6c1a32e2014-06-26 11:58:55 -0700143 if (NO_CMD_CMPL(ctrl))
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600144 return;
145
146 if (!ctrl->cmd_busy)
147 return;
148
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600149 /*
150 * Even if the command has already timed out, we want to call
151 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
152 */
153 now = jiffies;
154 if (time_before_eq(cmd_timeout, now))
155 timeout = 1;
156 else
157 timeout = cmd_timeout - now;
158
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600159 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
160 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
Kenji Kaneshiged737bdc2008-05-28 14:59:44 +0900161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600162 else
Yinghai Lu7cbeb9f2014-09-22 20:05:45 -0600163 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600164
165 /*
166 * Controllers with errata like Intel CF118 don't generate
167 * completion notifications unless the power/indicator/interlock
168 * control bits are changed. On such controllers, we'll emit this
169 * timeout message when we wait for completion of commands that
170 * don't change those bits, e.g., commands that merely enable
171 * interrupts.
172 */
Kenji Kaneshige262303fe2006-12-21 17:01:10 -0800173 if (!rc)
Bjorn Helgaasd537a3a2014-08-15 17:18:44 -0600174 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600175 ctrl->slot_ctrl,
Yinghai Lud4338892014-09-22 20:07:35 -0600176 jiffies_to_msecs(jiffies - ctrl->cmd_started));
Kenji Kaneshige44ef4ce2006-12-21 17:01:09 -0800177}
178
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700179/**
180 * pcie_write_cmd - Issue controller command
Kenji Kaneshigec27fb882008-04-25 14:39:05 -0700181 * @ctrl: controller to which the command is issued
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700182 * @cmd: command value written to slot control register
183 * @mask: bitmask of slot control register to be modified
184 */
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700185static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186{
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600187 struct pci_dev *pdev = ctrl_dev(ctrl);
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700188 u16 slot_ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189
Kenji Kaneshige44ef4ce2006-12-21 17:01:09 -0800190 mutex_lock(&ctrl->ctrl_lock);
191
Bjorn Helgaas3461a062014-06-13 15:06:40 -0600192 /* Wait for any previous command that might still be in progress */
193 pcie_wait_cmd(ctrl);
194
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700195 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700196 slot_ctrl &= ~mask;
Kenji Kaneshigeb7aa1f12008-04-25 14:39:14 -0700197 slot_ctrl |= (cmd & mask);
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700198 ctrl->cmd_busy = 1;
Kenji Kaneshige2d32a9a2008-04-25 14:39:02 -0700199 smp_mb();
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700200 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
Bjorn Helgaas40b96082014-06-14 09:55:49 -0600201 ctrl->cmd_started = jiffies;
Bjorn Helgaas4283c702014-06-13 13:58:35 -0600202 ctrl->slot_ctrl = slot_ctrl;
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700203
Kenji Kaneshige44ef4ce2006-12-21 17:01:09 -0800204 mutex_unlock(&ctrl->ctrl_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205}
206
Rajat Jain47033892014-02-04 18:28:43 -0800207bool pciehp_check_link_active(struct controller *ctrl)
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900208{
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600209 struct pci_dev *pdev = ctrl_dev(ctrl);
Yinghai Lu4e2ce402012-01-27 10:55:12 -0800210 u16 lnk_status;
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700211 bool ret;
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900212
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700213 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
Yinghai Lu4e2ce402012-01-27 10:55:12 -0800214 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
215
216 if (ret)
217 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
218
219 return ret;
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900220}
221
Yinghai Lubffe4f72012-01-27 10:55:13 -0800222static void __pcie_wait_link_active(struct controller *ctrl, bool active)
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900223{
224 int timeout = 1000;
225
Rajat Jain47033892014-02-04 18:28:43 -0800226 if (pciehp_check_link_active(ctrl) == active)
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900227 return;
228 while (timeout > 0) {
229 msleep(10);
230 timeout -= 10;
Rajat Jain47033892014-02-04 18:28:43 -0800231 if (pciehp_check_link_active(ctrl) == active)
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900232 return;
233 }
Yinghai Lubffe4f72012-01-27 10:55:13 -0800234 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
235 active ? "set" : "cleared");
236}
237
238static void pcie_wait_link_active(struct controller *ctrl)
239{
240 __pcie_wait_link_active(ctrl, true);
241}
242
Yinghai Lu2f5d8e42012-01-27 10:55:11 -0800243static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
244{
245 u32 l;
246 int count = 0;
247 int delay = 1000, step = 20;
248 bool found = false;
249
250 do {
251 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
252 count++;
253
254 if (found)
255 break;
256
257 msleep(step);
258 delay -= step;
259 } while (delay > 0);
260
261 if (count > 1 && pciehp_debug)
262 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
263 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
264 PCI_FUNC(devfn), count, step, l);
265
266 return found;
267}
268
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900269int pciehp_check_link_status(struct controller *ctrl)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270{
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600271 struct pci_dev *pdev = ctrl_dev(ctrl);
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700272 bool found;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273 u16 lnk_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400275 /*
276 * Data Link Layer Link Active Reporting must be capable for
277 * hot-plug capable downstream port. But old controller might
278 * not implement it. In this case, we wait for 1000 ms.
279 */
280 if (ctrl->link_active_reporting)
281 pcie_wait_link_active(ctrl);
282 else
283 msleep(1000);
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900284
Yinghai Lu2f5d8e42012-01-27 10:55:11 -0800285 /* wait 100ms before read pci conf, and try in 1s */
286 msleep(100);
287 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
288 PCI_DEVFN(0, 0));
Kenji Kaneshige0027cb32011-11-10 16:40:37 +0900289
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700290 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
Taku Izumi7f2feec2008-09-05 12:11:26 +0900291 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900292 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
293 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400294 ctrl_err(ctrl, "Link Training Error occurs\n");
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700295 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296 }
297
Yinghai Lufdbd3ce2011-11-07 07:53:23 -0800298 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
299
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700300 if (!found)
301 return -1;
Yinghai Lu2f5d8e42012-01-27 10:55:11 -0800302
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700303 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304}
305
Yinghai Lu7f822992012-01-27 10:55:14 -0800306static int __pciehp_link_set(struct controller *ctrl, bool enable)
307{
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600308 struct pci_dev *pdev = ctrl_dev(ctrl);
Yinghai Lu7f822992012-01-27 10:55:14 -0800309 u16 lnk_ctrl;
Yinghai Lu7f822992012-01-27 10:55:14 -0800310
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700311 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
Yinghai Lu7f822992012-01-27 10:55:14 -0800312
313 if (enable)
314 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
315 else
316 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
317
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700318 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
Yinghai Lu7f822992012-01-27 10:55:14 -0800319 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700320 return 0;
Yinghai Lu7f822992012-01-27 10:55:14 -0800321}
322
323static int pciehp_link_enable(struct controller *ctrl)
324{
325 return __pciehp_link_set(ctrl, true);
326}
327
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700328void pciehp_get_attention_status(struct slot *slot, u8 *status)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800330 struct controller *ctrl = slot->ctrl;
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600331 struct pci_dev *pdev = ctrl_dev(ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 u16 slot_ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700334 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900335 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
336 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700338 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
339 case PCI_EXP_SLTCTL_ATTN_IND_ON:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 *status = 1; /* On */
341 break;
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700342 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 *status = 2; /* Blink */
344 break;
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700345 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346 *status = 0; /* Off */
347 break;
348 default:
349 *status = 0xFF;
350 break;
351 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352}
353
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700354void pciehp_get_power_status(struct slot *slot, u8 *status)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800356 struct controller *ctrl = slot->ctrl;
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600357 struct pci_dev *pdev = ctrl_dev(ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 u16 slot_ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700360 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900361 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
362 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700364 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
365 case PCI_EXP_SLTCTL_PWR_ON:
366 *status = 1; /* On */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 break;
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700368 case PCI_EXP_SLTCTL_PWR_OFF:
369 *status = 0; /* Off */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 break;
371 default:
372 *status = 0xFF;
373 break;
374 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375}
376
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700377void pciehp_get_latch_status(struct slot *slot, u8 *status)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378{
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700379 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 u16 slot_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700382 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900383 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384}
385
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700386void pciehp_get_adapter_status(struct slot *slot, u8 *status)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387{
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700388 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389 u16 slot_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700391 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900392 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393}
394
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900395int pciehp_query_power_fault(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396{
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700397 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398 u16 slot_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700400 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900401 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402}
403
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700404void pciehp_set_attention_status(struct slot *slot, u8 value)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800406 struct controller *ctrl = slot->ctrl;
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700407 u16 slot_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408
Bjorn Helgaasaf9ab792013-12-15 17:23:54 -0700409 if (!ATTN_LED(ctrl))
410 return;
411
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 switch (value) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400413 case 0: /* turn off */
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700414 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
Kenji Kaneshige445f7982009-10-05 17:42:59 +0900415 break;
416 case 1: /* turn on */
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700417 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
Kenji Kaneshige445f7982009-10-05 17:42:59 +0900418 break;
419 case 2: /* turn blink */
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700420 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
Kenji Kaneshige445f7982009-10-05 17:42:59 +0900421 break;
422 default:
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700423 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 }
Yinghai Lucf8d7b52014-09-22 20:36:09 -0600425 pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900426 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
427 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428}
429
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900430void pciehp_green_led_on(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800432 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige71ad5562007-08-09 16:09:34 -0700433
Bjorn Helgaasaf9ab792013-12-15 17:23:54 -0700434 if (!PWR_LED(ctrl))
435 return;
436
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700437 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900438 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700439 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
440 PCI_EXP_SLTCTL_PWR_IND_ON);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441}
442
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900443void pciehp_green_led_off(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800445 struct controller *ctrl = slot->ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446
Bjorn Helgaasaf9ab792013-12-15 17:23:54 -0700447 if (!PWR_LED(ctrl))
448 return;
449
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700450 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900451 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700452 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
453 PCI_EXP_SLTCTL_PWR_IND_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454}
455
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900456void pciehp_green_led_blink(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800458 struct controller *ctrl = slot->ctrl;
Kenji Kaneshige71ad5562007-08-09 16:09:34 -0700459
Bjorn Helgaasaf9ab792013-12-15 17:23:54 -0700460 if (!PWR_LED(ctrl))
461 return;
462
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700463 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900464 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700465 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
466 PCI_EXP_SLTCTL_PWR_IND_BLINK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467}
468
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400469int pciehp_power_on_slot(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800471 struct controller *ctrl = slot->ctrl;
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600472 struct pci_dev *pdev = ctrl_dev(ctrl);
Kenji Kaneshigef4778362007-05-31 09:43:34 -0700473 u16 slot_status;
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700474 int retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475
Rajesh Shah5a49f202005-11-23 15:44:54 -0800476 /* Clear sticky power-fault bit from previous power failures */
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700477 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
Bjorn Helgaas2f2ed41c2013-12-14 13:06:40 -0700478 if (slot_status & PCI_EXP_SLTSTA_PFD)
479 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
480 PCI_EXP_SLTSTA_PFD);
Kenji Kaneshige5651c482009-11-13 15:14:10 +0900481 ctrl->power_fault_detected = 0;
Kenji Kaneshigea0f018d2006-12-21 17:01:06 -0800482
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700483 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900484 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700485 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
486 PCI_EXP_SLTCTL_PWR_ON);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487
Yinghai Lu2debd922012-01-27 10:55:15 -0800488 retval = pciehp_link_enable(ctrl);
489 if (retval)
490 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
491
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492 return retval;
493}
494
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400495void pciehp_power_off_slot(struct slot *slot)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800497 struct controller *ctrl = slot->ctrl;
Kenji Kaneshigef1050a32007-12-20 19:45:09 +0900498
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700499 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900500 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
Bjorn Helgaase7b4f0d72013-12-14 13:06:53 -0700501 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
502 PCI_EXP_SLTCTL_PWR_OFF);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503}
504
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800505static irqreturn_t pcie_isr(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506{
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800507 struct controller *ctrl = (struct controller *)dev_id;
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600508 struct pci_dev *pdev = ctrl_dev(ctrl);
Bjorn Helgaasb440bde2014-09-10 13:45:01 -0600509 struct pci_bus *subordinate = pdev->subordinate;
510 struct pci_dev *dev;
Kenji Kaneshige8720d272009-09-15 17:24:46 +0900511 struct slot *slot = ctrl->slot;
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700512 u16 detected, intr_loc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700514 /*
515 * In order to guarantee that all interrupt events are
516 * serviced, we need to re-inspect Slot Status register after
517 * clearing what is presumed to be the last pending interrupt.
518 */
519 intr_loc = 0;
520 do {
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700521 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900523 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
524 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
Rajat Jaine48f1b62014-02-04 18:29:10 -0800525 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
Kenji Kaneshige81b840c2009-02-03 15:06:13 +0900526 detected &= ~intr_loc;
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700527 intr_loc |= detected;
528 if (!intr_loc)
529 return IRQ_NONE;
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700530 if (detected)
531 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
532 intr_loc);
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700533 } while (detected);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534
Taku Izumi7f2feec2008-09-05 12:11:26 +0900535 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
Kenji Kaneshige71ad5562007-08-09 16:09:34 -0700536
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700537 /* Check Command Complete Interrupt Pending */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900538 if (intr_loc & PCI_EXP_SLTSTA_CC) {
Kenji Kaneshige262303fe2006-12-21 17:01:10 -0800539 ctrl->cmd_busy = 0;
Kenji Kaneshige2d32a9a2008-04-25 14:39:02 -0700540 smp_mb();
Kenji Kaneshiged737bdc2008-05-28 14:59:44 +0900541 wake_up(&ctrl->queue);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542 }
543
Bjorn Helgaasb440bde2014-09-10 13:45:01 -0600544 if (subordinate) {
545 list_for_each_entry(dev, &subordinate->devices, bus_list) {
546 if (dev->ignore_hotplug) {
547 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
548 intr_loc, pci_name(dev));
549 return IRQ_HANDLED;
550 }
551 }
552 }
553
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900554 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
Kenji Kaneshigedbd79ae2008-05-27 19:03:16 +0900555 return IRQ_HANDLED;
556
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700557 /* Check MRL Sensor Changed */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900558 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
Kenji Kaneshige8720d272009-09-15 17:24:46 +0900559 pciehp_handle_switch_change(slot);
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800560
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700561 /* Check Attention Button Pressed */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900562 if (intr_loc & PCI_EXP_SLTSTA_ABP)
Kenji Kaneshige8720d272009-09-15 17:24:46 +0900563 pciehp_handle_attention_button(slot);
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800564
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700565 /* Check Presence Detect Changed */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900566 if (intr_loc & PCI_EXP_SLTSTA_PDC)
Kenji Kaneshige8720d272009-09-15 17:24:46 +0900567 pciehp_handle_presence_change(slot);
Kenji Kaneshige48fe3912006-12-21 17:01:04 -0800568
Kenji Kaneshigec6b069e2008-04-25 14:38:57 -0700569 /* Check Power Fault Detected */
Kenji Kaneshige99f01692009-02-03 15:06:16 +0900570 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
571 ctrl->power_fault_detected = 1;
Kenji Kaneshige8720d272009-09-15 17:24:46 +0900572 pciehp_handle_power_fault(slot);
Kenji Kaneshige99f01692009-02-03 15:06:16 +0900573 }
Rajat Jaine48f1b62014-02-04 18:29:10 -0800574
575 if (intr_loc & PCI_EXP_SLTSTA_DLLSC)
576 pciehp_handle_linkstate_change(slot);
577
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578 return IRQ_HANDLED;
579}
580
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700581void pcie_enable_notification(struct controller *ctrl)
Mark Lordecdde932007-11-21 15:07:55 -0800582{
Kenji Kaneshigec27fb882008-04-25 14:39:05 -0700583 u16 cmd, mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584
Kenji Kaneshige5651c482009-11-13 15:14:10 +0900585 /*
586 * TBD: Power fault detected software notification support.
587 *
588 * Power fault detected software notification is not enabled
589 * now, because it caused power fault detected interrupt storm
590 * on some machines. On those machines, power fault detected
591 * bit in the slot status register was set again immediately
592 * when it is cleared in the interrupt service routine, and
593 * next power fault detected interrupt was notified again.
594 */
Rajat Jain4f854f22014-02-04 18:29:23 -0800595
596 /*
597 * Always enable link events: thus link-up and link-down shall
598 * always be treated as hotplug and unplug respectively. Enable
599 * presence detect only if Attention Button is not present.
600 */
601 cmd = PCI_EXP_SLTCTL_DLLSCE;
Kenji Kaneshigeae416e62008-04-25 14:39:06 -0700602 if (ATTN_BUTTN(ctrl))
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900603 cmd |= PCI_EXP_SLTCTL_ABPE;
Rajat Jain4f854f22014-02-04 18:29:23 -0800604 else
605 cmd |= PCI_EXP_SLTCTL_PDCE;
Kenji Kaneshigeae416e62008-04-25 14:39:06 -0700606 if (MRL_SENS(ctrl))
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900607 cmd |= PCI_EXP_SLTCTL_MRLSCE;
Kenji Kaneshigec27fb882008-04-25 14:39:05 -0700608 if (!pciehp_poll_mode)
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900609 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
Kenji Kaneshigec27fb882008-04-25 14:39:05 -0700610
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900611 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
612 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
Rajat Jain4f854f22014-02-04 18:29:23 -0800613 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
614 PCI_EXP_SLTCTL_DLLSCE);
Kenji Kaneshigec27fb882008-04-25 14:39:05 -0700615
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700616 pcie_write_cmd(ctrl, cmd, mask);
Yinghai Lucf8d7b52014-09-22 20:36:09 -0600617 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
618 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619}
Mark Lord08e7a7d2007-11-28 15:11:46 -0800620
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900621static void pcie_disable_notification(struct controller *ctrl)
622{
623 u16 mask;
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700624
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900625 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
626 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
Kenji Kaneshigef22daf12009-10-05 17:40:02 +0900627 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
628 PCI_EXP_SLTCTL_DLLSCE);
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700629 pcie_write_cmd(ctrl, 0, mask);
Yinghai Lucf8d7b52014-09-22 20:36:09 -0600630 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
631 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900632}
633
Alex Williamson2e35afa2013-08-08 14:09:37 -0600634/*
635 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
Rajat Jain2b3940b2014-02-18 18:53:19 -0800636 * bus reset of the bridge, but at the same time we want to ensure that it is
637 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
638 * disable link state notification and presence detection change notification
639 * momentarily, if we see that they could interfere. Also, clear any spurious
Alex Williamson2e35afa2013-08-08 14:09:37 -0600640 * events after.
641 */
642int pciehp_reset_slot(struct slot *slot, int probe)
643{
644 struct controller *ctrl = slot->ctrl;
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600645 struct pci_dev *pdev = ctrl_dev(ctrl);
Rajat Jain06a8d892014-02-04 18:30:40 -0800646 u16 stat_mask = 0, ctrl_mask = 0;
Alex Williamson2e35afa2013-08-08 14:09:37 -0600647
648 if (probe)
649 return 0;
650
Rajat Jain2b3940b2014-02-18 18:53:19 -0800651 if (!ATTN_BUTTN(ctrl)) {
Rajat Jain06a8d892014-02-04 18:30:40 -0800652 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
653 stat_mask |= PCI_EXP_SLTSTA_PDC;
Alex Williamson2e35afa2013-08-08 14:09:37 -0600654 }
Rajat Jain06a8d892014-02-04 18:30:40 -0800655 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
656 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
657
658 pcie_write_cmd(ctrl, 0, ctrl_mask);
Yinghai Lucf8d7b52014-09-22 20:36:09 -0600659 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
660 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
Rajat Jain06a8d892014-02-04 18:30:40 -0800661 if (pciehp_poll_mode)
662 del_timer_sync(&ctrl->poll_timer);
Alex Williamson2e35afa2013-08-08 14:09:37 -0600663
664 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
665
Rajat Jain06a8d892014-02-04 18:30:40 -0800666 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
667 pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask);
Yinghai Lucf8d7b52014-09-22 20:36:09 -0600668 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
669 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
Rajat Jain06a8d892014-02-04 18:30:40 -0800670 if (pciehp_poll_mode)
671 int_poll_timeout(ctrl->poll_timer.data);
Alex Williamson2e35afa2013-08-08 14:09:37 -0600672
673 return 0;
674}
675
Eric W. Biedermandbc7e1e2009-01-28 19:31:18 -0800676int pcie_init_notification(struct controller *ctrl)
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900677{
678 if (pciehp_request_irq(ctrl))
679 return -1;
Bjorn Helgaas6dae6202013-12-14 13:06:16 -0700680 pcie_enable_notification(ctrl);
Eric W. Biedermandbc7e1e2009-01-28 19:31:18 -0800681 ctrl->notification_enabled = 1;
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900682 return 0;
683}
684
685static void pcie_shutdown_notification(struct controller *ctrl)
686{
Eric W. Biedermandbc7e1e2009-01-28 19:31:18 -0800687 if (ctrl->notification_enabled) {
688 pcie_disable_notification(ctrl);
689 pciehp_free_irq(ctrl);
690 ctrl->notification_enabled = 0;
691 }
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900692}
693
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900694static int pcie_init_slot(struct controller *ctrl)
695{
696 struct slot *slot;
697
698 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
699 if (!slot)
700 return -ENOMEM;
701
Kees Cookd8537542013-07-03 15:04:57 -0700702 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
Yijing Wangc2be6f92013-01-11 10:15:54 +0800703 if (!slot->wq)
704 goto abort;
705
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900706 slot->ctrl = ctrl;
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900707 mutex_init(&slot->lock);
Rajat Jain50b52fd2014-02-04 18:31:11 -0800708 mutex_init(&slot->hotplug_lock);
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900709 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
Kenji Kaneshige8720d272009-09-15 17:24:46 +0900710 ctrl->slot = slot;
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900711 return 0;
Yijing Wangc2be6f92013-01-11 10:15:54 +0800712abort:
713 kfree(slot);
714 return -ENOMEM;
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900715}
716
717static void pcie_cleanup_slot(struct controller *ctrl)
718{
Kenji Kaneshige8720d272009-09-15 17:24:46 +0900719 struct slot *slot = ctrl->slot;
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900720 cancel_delayed_work(&slot->work);
Yijing Wangc2be6f92013-01-11 10:15:54 +0800721 destroy_workqueue(slot->wq);
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900722 kfree(slot);
723}
724
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700725static inline void dbg_ctrl(struct controller *ctrl)
726{
727 int i;
728 u16 reg16;
Kenji Kaneshige385e2492009-09-15 17:30:14 +0900729 struct pci_dev *pdev = ctrl->pcie->port;
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700730
731 if (!pciehp_debug)
732 return;
733
Taku Izumi7f2feec2008-09-05 12:11:26 +0900734 ctrl_info(ctrl, "Hotplug Controller:\n");
735 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
736 pci_name(pdev), pdev->irq);
737 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
738 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
739 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
740 pdev->subsystem_device);
741 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
742 pdev->subsystem_vendor);
Kenji Kaneshige1518c172009-11-11 14:34:52 +0900743 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
744 pci_pcie_cap(pdev));
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700745 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
746 if (!pci_resource_len(pdev, i))
747 continue;
Bjorn Helgaase1944c62010-03-16 15:53:08 -0600748 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
749 i, &pdev->resource[i]);
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700750 }
Taku Izumi7f2feec2008-09-05 12:11:26 +0900751 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
Kenji Kaneshiged54798f2009-09-15 17:28:53 +0900752 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
Taku Izumi7f2feec2008-09-05 12:11:26 +0900753 ctrl_info(ctrl, " Attention Button : %3s\n",
754 ATTN_BUTTN(ctrl) ? "yes" : "no");
755 ctrl_info(ctrl, " Power Controller : %3s\n",
756 POWER_CTRL(ctrl) ? "yes" : "no");
757 ctrl_info(ctrl, " MRL Sensor : %3s\n",
758 MRL_SENS(ctrl) ? "yes" : "no");
759 ctrl_info(ctrl, " Attention Indicator : %3s\n",
760 ATTN_LED(ctrl) ? "yes" : "no");
761 ctrl_info(ctrl, " Power Indicator : %3s\n",
762 PWR_LED(ctrl) ? "yes" : "no");
763 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
764 HP_SUPR_RM(ctrl) ? "yes" : "no");
765 ctrl_info(ctrl, " EMI Present : %3s\n",
766 EMI(ctrl) ? "yes" : "no");
767 ctrl_info(ctrl, " Command Completed : %3s\n",
768 NO_CMD_CMPL(ctrl) ? "no" : "yes");
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600769 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
Taku Izumi7f2feec2008-09-05 12:11:26 +0900770 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
Bjorn Helgaascd84d342013-05-09 11:26:16 -0600771 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
Taku Izumi7f2feec2008-09-05 12:11:26 +0900772 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700773}
774
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400775#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
Bjorn Helgaasafe24782013-12-14 13:06:36 -0700776
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900777struct controller *pcie_init(struct pcie_device *dev)
Mark Lord08e7a7d2007-11-28 15:11:46 -0800778{
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900779 struct controller *ctrl;
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900780 u32 slot_cap, link_cap;
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700781 struct pci_dev *pdev = dev->port;
Mark Lord08e7a7d2007-11-28 15:11:46 -0800782
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900783 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
784 if (!ctrl) {
Taku Izumi18b341b2008-10-23 11:47:32 +0900785 dev_err(&dev->device, "%s: Out of memory\n", __func__);
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900786 goto abort;
787 }
Kenji Kaneshigef7a10e32008-08-22 17:16:48 +0900788 ctrl->pcie = dev;
Bjorn Helgaas1a84b992013-12-14 13:06:07 -0700789 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700790 ctrl->slot_cap = slot_cap;
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700791 mutex_init(&ctrl->ctrl_lock);
792 init_waitqueue_head(&ctrl->queue);
793 dbg_ctrl(ctrl);
Bjorn Helgaas2cc56f32014-06-14 10:56:31 -0600794
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400795 /* Check if Data Link Layer Link Active Reporting is implemented */
796 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
797 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
798 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
799 ctrl->link_active_reporting = 1;
800 }
Kenji Kaneshigef18e9622008-10-22 14:31:44 +0900801
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900802 /* Clear all remaining event bits in Slot Status register */
Bjorn Helgaasdf726482013-12-14 13:06:47 -0700803 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
804 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
805 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
Myron Stowe0d25d352014-06-17 13:27:34 -0600806 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
Mark Lord08e7a7d2007-11-28 15:11:46 -0800807
Bjorn Helgaasafe24782013-12-14 13:06:36 -0700808 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
809 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
810 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
811 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
812 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
813 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
814 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
815 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
816 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
817 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700818
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900819 if (pcie_init_slot(ctrl))
820 goto abort_ctrl;
Kenji Kaneshige2aeeef12008-04-25 14:39:08 -0700821
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900822 return ctrl;
823
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900824abort_ctrl:
825 kfree(ctrl);
Mark Lord08e7a7d2007-11-28 15:11:46 -0800826abort:
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900827 return NULL;
828}
829
Kenji Kaneshige82a9e792009-09-15 17:30:48 +0900830void pciehp_release_ctrl(struct controller *ctrl)
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900831{
832 pcie_shutdown_notification(ctrl);
833 pcie_cleanup_slot(ctrl);
Kenji Kaneshigec4635eb2008-06-20 12:07:08 +0900834 kfree(ctrl);
Mark Lord08e7a7d2007-11-28 15:11:46 -0800835}