Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Sebastian Andrzej Siewior | 8348c25 | 2010-11-22 17:12:15 -0800 | [diff] [blame] | 2 | * pxa2xx_ssp.h |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003 Russell King, All Rights Reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This driver supports the following PXA CPU/SSP ports:- |
| 11 | * |
| 12 | * PXA250 SSP |
| 13 | * PXA255 SSP, NSSP |
| 14 | * PXA26x SSP, NSSP, ASSP |
| 15 | * PXA27x SSP1, SSP2, SSP3 |
eric miao | 8828645 | 2007-12-06 17:56:42 +0800 | [diff] [blame] | 16 | * PXA3xx SSP1, SSP2, SSP3, SSP4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | */ |
| 18 | |
Sebastian Andrzej Siewior | 8348c25 | 2010-11-22 17:12:15 -0800 | [diff] [blame] | 19 | #ifndef __LINUX_SSP_H |
| 20 | #define __LINUX_SSP_H |
eric miao | 8828645 | 2007-12-06 17:56:42 +0800 | [diff] [blame] | 21 | |
| 22 | #include <linux/list.h> |
Mark Brown | 63bef54 | 2008-08-26 18:40:57 +0100 | [diff] [blame] | 23 | #include <linux/io.h> |
Daniel Mack | 6446221 | 2013-08-12 10:37:18 +0200 | [diff] [blame] | 24 | #include <linux/of.h> |
| 25 | |
eric miao | 8828645 | 2007-12-06 17:56:42 +0800 | [diff] [blame] | 26 | |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 27 | /* |
| 28 | * SSP Serial Port Registers |
| 29 | * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. |
| 30 | * PXA255, PXA26x and PXA27x have extra ports, registers and bits. |
| 31 | */ |
| 32 | |
| 33 | #define SSCR0 (0x00) /* SSP Control Register 0 */ |
| 34 | #define SSCR1 (0x04) /* SSP Control Register 1 */ |
| 35 | #define SSSR (0x08) /* SSP Status Register */ |
| 36 | #define SSITR (0x0C) /* SSP Interrupt Test Register */ |
| 37 | #define SSDR (0x10) /* SSP Data Write/Data Read Register */ |
| 38 | |
| 39 | #define SSTO (0x28) /* SSP Time Out Register */ |
Jarkko Nikula | c4827bb | 2014-12-18 15:04:21 +0200 | [diff] [blame] | 40 | #define DDS_RATE (0x28) /* SSP DDS Clock Rate Register (Intel Quark) */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 41 | #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ |
| 42 | #define SSTSA (0x30) /* SSP Tx Timeslot Active */ |
| 43 | #define SSRSA (0x34) /* SSP Rx Timeslot Active */ |
| 44 | #define SSTSS (0x38) /* SSP Timeslot Status */ |
| 45 | #define SSACD (0x3C) /* SSP Audio Clock Divider */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 46 | #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 47 | |
| 48 | /* Common PXA2xx bits first */ |
| 49 | #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ |
| 50 | #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ |
| 51 | #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ |
| 52 | #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ |
| 53 | #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ |
| 54 | #define SSCR0_National (0x2 << 4) /* National Microwire */ |
| 55 | #define SSCR0_ECS (1 << 6) /* External clock select */ |
| 56 | #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ |
| 57 | #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ |
| 58 | |
Haojian Zhuang | 004690f | 2010-03-19 11:52:39 -0400 | [diff] [blame] | 59 | /* PXA27x, PXA3xx */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 60 | #define SSCR0_EDSS (1 << 20) /* Extended data size select */ |
| 61 | #define SSCR0_NCS (1 << 21) /* Network clock select */ |
| 62 | #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ |
| 63 | #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ |
| 64 | #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ |
| 65 | #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ |
Haojian Zhuang | 004690f | 2010-03-19 11:52:39 -0400 | [diff] [blame] | 66 | #define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 67 | #define SSCR0_ACS (1 << 30) /* Audio clock select */ |
| 68 | #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 69 | |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 70 | |
| 71 | #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ |
| 72 | #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ |
| 73 | #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ |
| 74 | #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ |
| 75 | #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ |
| 76 | #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 77 | |
Sebastian Andrzej Siewior | 2a8626a | 2010-11-22 17:12:17 -0800 | [diff] [blame] | 78 | #define SSSR_ALT_FRM_MASK 3 /* Masks the SFRM signal number */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 79 | #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ |
| 80 | #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ |
| 81 | #define SSSR_BSY (1 << 4) /* SSP Busy */ |
| 82 | #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ |
| 83 | #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ |
| 84 | #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ |
Sebastian Andrzej Siewior | d0777f2 | 2010-11-22 17:12:16 -0800 | [diff] [blame] | 85 | |
Sebastian Andrzej Siewior | d0777f2 | 2010-11-22 17:12:16 -0800 | [diff] [blame] | 86 | #define RX_THRESH_DFLT 8 |
| 87 | #define TX_THRESH_DFLT 8 |
| 88 | |
| 89 | #define SSSR_TFL_MASK (0xf << 8) /* Transmit FIFO Level mask */ |
| 90 | #define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */ |
| 91 | |
| 92 | #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ |
Andy Shevchenko | 63971c5 | 2017-01-02 13:44:29 +0200 | [diff] [blame] | 93 | #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ |
Sebastian Andrzej Siewior | d0777f2 | 2010-11-22 17:12:16 -0800 | [diff] [blame] | 94 | #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ |
Andy Shevchenko | 63971c5 | 2017-01-02 13:44:29 +0200 | [diff] [blame] | 95 | #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ |
Sebastian Andrzej Siewior | d0777f2 | 2010-11-22 17:12:16 -0800 | [diff] [blame] | 96 | |
Andy Shevchenko | 7c7289a | 2016-09-07 15:43:22 +0300 | [diff] [blame] | 97 | #define RX_THRESH_CE4100_DFLT 2 |
| 98 | #define TX_THRESH_CE4100_DFLT 2 |
Sebastian Andrzej Siewior | d0777f2 | 2010-11-22 17:12:16 -0800 | [diff] [blame] | 99 | |
Andy Shevchenko | 7c7289a | 2016-09-07 15:43:22 +0300 | [diff] [blame] | 100 | #define CE4100_SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */ |
| 101 | #define CE4100_SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */ |
Sebastian Andrzej Siewior | d0777f2 | 2010-11-22 17:12:16 -0800 | [diff] [blame] | 102 | |
Andy Shevchenko | 7c7289a | 2016-09-07 15:43:22 +0300 | [diff] [blame] | 103 | #define CE4100_SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */ |
| 104 | #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */ |
| 105 | #define CE4100_SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */ |
| 106 | #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 107 | |
Weike Chen | e5262d0 | 2014-11-26 02:35:10 -0800 | [diff] [blame] | 108 | /* QUARK_X1000 SSCR0 bit definition */ |
Andy Shevchenko | 63971c5 | 2017-01-02 13:44:29 +0200 | [diff] [blame] | 109 | #define QUARK_X1000_SSCR0_DSS (0x1F << 0) /* Data Size Select (mask) */ |
| 110 | #define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */ |
| 111 | #define QUARK_X1000_SSCR0_FRF (0x3 << 5) /* FRame Format (mask) */ |
Weike Chen | e5262d0 | 2014-11-26 02:35:10 -0800 | [diff] [blame] | 112 | #define QUARK_X1000_SSCR0_Motorola (0x0 << 5) /* Motorola's Serial Peripheral Interface (SPI) */ |
| 113 | |
| 114 | #define RX_THRESH_QUARK_X1000_DFLT 1 |
| 115 | #define TX_THRESH_QUARK_X1000_DFLT 16 |
| 116 | |
| 117 | #define QUARK_X1000_SSSR_TFL_MASK (0x1F << 8) /* Transmit FIFO Level mask */ |
| 118 | #define QUARK_X1000_SSSR_RFL_MASK (0x1F << 13) /* Receive FIFO Level mask */ |
| 119 | |
| 120 | #define QUARK_X1000_SSCR1_TFT (0x1F << 6) /* Transmit FIFO Threshold (mask) */ |
| 121 | #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */ |
| 122 | #define QUARK_X1000_SSCR1_RFT (0x1F << 11) /* Receive FIFO Threshold (mask) */ |
| 123 | #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */ |
Andy Shevchenko | 63971c5 | 2017-01-02 13:44:29 +0200 | [diff] [blame] | 124 | #define QUARK_X1000_SSCR1_STRF (1 << 17) /* Select FIFO or EFWR */ |
| 125 | #define QUARK_X1000_SSCR1_EFWR (1 << 16) /* Enable FIFO Write/Read */ |
Weike Chen | e5262d0 | 2014-11-26 02:35:10 -0800 | [diff] [blame] | 126 | |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 127 | /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ |
| 128 | #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ |
| 129 | #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ |
| 130 | #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ |
| 131 | #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ |
| 132 | #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ |
| 133 | #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ |
| 134 | #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ |
| 135 | #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ |
| 136 | #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ |
| 137 | #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ |
| 138 | #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ |
| 139 | #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ |
| 140 | #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ |
| 141 | #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ |
| 142 | #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 143 | #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interrupt Enable */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 144 | #define SSCR1_IFS (1 << 16) /* Invert Frame Signal */ |
| 145 | #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ |
| 146 | #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ |
| 147 | |
| 148 | #define SSSR_BCE (1 << 23) /* Bit Count Error */ |
| 149 | #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ |
| 150 | #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ |
| 151 | #define SSSR_EOC (1 << 20) /* End Of Chain */ |
| 152 | #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ |
| 153 | #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ |
| 154 | |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 155 | |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 156 | #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ |
Haojian Zhuang | 004690f | 2010-03-19 11:52:39 -0400 | [diff] [blame] | 157 | #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ |
| 158 | #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ |
| 159 | #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ |
| 160 | #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ |
| 161 | #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ |
| 162 | #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ |
| 163 | #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ |
| 164 | #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ |
| 165 | |
| 166 | /* PXA3xx */ |
| 167 | #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ |
| 168 | #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ |
| 169 | #define SSPSP_TIMING_MASK (0x7f8001f0) |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 170 | |
| 171 | #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ |
| 172 | #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ |
| 173 | #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 174 | #define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ |
Eric Miao | 83f2889 | 2010-03-16 17:03:20 +0800 | [diff] [blame] | 175 | |
Mika Westerberg | a0d2642 | 2013-01-22 12:26:32 +0200 | [diff] [blame] | 176 | /* LPSS SSP */ |
| 177 | #define SSITF 0x44 /* TX FIFO trigger level */ |
| 178 | #define SSITF_TxLoThresh(x) (((x) - 1) << 8) |
| 179 | #define SSITF_TxHiThresh(x) ((x) - 1) |
| 180 | |
| 181 | #define SSIRF 0x48 /* RX FIFO trigger level */ |
| 182 | #define SSIRF_RxThresh(x) ((x) - 1) |
| 183 | |
eric miao | 8828645 | 2007-12-06 17:56:42 +0800 | [diff] [blame] | 184 | enum pxa_ssp_type { |
| 185 | SSP_UNDEFINED = 0, |
| 186 | PXA25x_SSP, /* pxa 210, 250, 255, 26x */ |
| 187 | PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ |
| 188 | PXA27x_SSP, |
Qiao Zhou | 972a55b | 2012-06-04 10:41:04 +0800 | [diff] [blame] | 189 | PXA3xx_SSP, |
Haojian Zhuang | 7e49922 | 2010-03-19 11:53:17 -0400 | [diff] [blame] | 190 | PXA168_SSP, |
Qiao Zhou | 6017221 | 2012-06-04 10:41:03 +0800 | [diff] [blame] | 191 | PXA910_SSP, |
Sebastian Andrzej Siewior | 2a8626a | 2010-11-22 17:12:17 -0800 | [diff] [blame] | 192 | CE4100_SSP, |
Weike Chen | e5262d0 | 2014-11-26 02:35:10 -0800 | [diff] [blame] | 193 | QUARK_X1000_SSP, |
Jarkko Nikula | dccf736 | 2015-06-04 16:55:11 +0300 | [diff] [blame] | 194 | LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */ |
Jarkko Nikula | 03fbf48 | 2015-06-04 16:55:10 +0300 | [diff] [blame] | 195 | LPSS_BYT_SSP, |
Mika Westerberg | 30f3a6a | 2016-02-08 17:14:31 +0200 | [diff] [blame] | 196 | LPSS_BSW_SSP, |
Jarkko Nikula | 34cadd9 | 2015-07-30 16:30:07 +0300 | [diff] [blame] | 197 | LPSS_SPT_SSP, |
Jarkko Nikula | b7c08cf | 2015-10-28 15:13:42 +0200 | [diff] [blame] | 198 | LPSS_BXT_SSP, |
Jarkko Nikula | fc0b2ac | 2017-05-30 17:31:21 +0300 | [diff] [blame] | 199 | LPSS_CNL_SSP, |
eric miao | 8828645 | 2007-12-06 17:56:42 +0800 | [diff] [blame] | 200 | }; |
| 201 | |
| 202 | struct ssp_device { |
| 203 | struct platform_device *pdev; |
| 204 | struct list_head node; |
| 205 | |
| 206 | struct clk *clk; |
| 207 | void __iomem *mmio_base; |
| 208 | unsigned long phys_base; |
| 209 | |
| 210 | const char *label; |
| 211 | int port_id; |
| 212 | int type; |
| 213 | int use_count; |
| 214 | int irq; |
| 215 | int drcmr_rx; |
| 216 | int drcmr_tx; |
Daniel Mack | 6446221 | 2013-08-12 10:37:18 +0200 | [diff] [blame] | 217 | |
| 218 | struct device_node *of_node; |
eric miao | 8828645 | 2007-12-06 17:56:42 +0800 | [diff] [blame] | 219 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | |
Mark Brown | 63bef54 | 2008-08-26 18:40:57 +0100 | [diff] [blame] | 221 | /** |
Haojian Zhuang | baffe16 | 2010-05-05 10:11:15 -0400 | [diff] [blame] | 222 | * pxa_ssp_write_reg - Write to a SSP register |
Mark Brown | 63bef54 | 2008-08-26 18:40:57 +0100 | [diff] [blame] | 223 | * |
| 224 | * @dev: SSP device to access |
| 225 | * @reg: Register to write to |
| 226 | * @val: Value to be written. |
| 227 | */ |
Haojian Zhuang | baffe16 | 2010-05-05 10:11:15 -0400 | [diff] [blame] | 228 | static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) |
Mark Brown | 63bef54 | 2008-08-26 18:40:57 +0100 | [diff] [blame] | 229 | { |
| 230 | __raw_writel(val, dev->mmio_base + reg); |
| 231 | } |
| 232 | |
| 233 | /** |
Haojian Zhuang | baffe16 | 2010-05-05 10:11:15 -0400 | [diff] [blame] | 234 | * pxa_ssp_read_reg - Read from a SSP register |
Mark Brown | 63bef54 | 2008-08-26 18:40:57 +0100 | [diff] [blame] | 235 | * |
| 236 | * @dev: SSP device to access |
| 237 | * @reg: Register to read from |
| 238 | */ |
Haojian Zhuang | baffe16 | 2010-05-05 10:11:15 -0400 | [diff] [blame] | 239 | static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg) |
Mark Brown | 63bef54 | 2008-08-26 18:40:57 +0100 | [diff] [blame] | 240 | { |
| 241 | return __raw_readl(dev->mmio_base + reg); |
| 242 | } |
| 243 | |
Arnd Bergmann | 1ced9a5 | 2014-02-18 16:33:07 +0100 | [diff] [blame] | 244 | #if IS_ENABLED(CONFIG_PXA_SSP) |
Haojian Zhuang | baffe16 | 2010-05-05 10:11:15 -0400 | [diff] [blame] | 245 | struct ssp_device *pxa_ssp_request(int port, const char *label); |
| 246 | void pxa_ssp_free(struct ssp_device *); |
Daniel Mack | 6446221 | 2013-08-12 10:37:18 +0200 | [diff] [blame] | 247 | struct ssp_device *pxa_ssp_request_of(const struct device_node *of_node, |
| 248 | const char *label); |
Mika Westerberg | 851bacf | 2013-01-07 12:44:33 +0200 | [diff] [blame] | 249 | #else |
| 250 | static inline struct ssp_device *pxa_ssp_request(int port, const char *label) |
| 251 | { |
| 252 | return NULL; |
| 253 | } |
Daniel Mack | 6446221 | 2013-08-12 10:37:18 +0200 | [diff] [blame] | 254 | static inline struct ssp_device *pxa_ssp_request_of(const struct device_node *n, |
| 255 | const char *name) |
| 256 | { |
| 257 | return NULL; |
| 258 | } |
Mika Westerberg | 851bacf | 2013-01-07 12:44:33 +0200 | [diff] [blame] | 259 | static inline void pxa_ssp_free(struct ssp_device *ssp) {} |
| 260 | #endif |
| 261 | |
Sebastian Andrzej Siewior | 8348c25 | 2010-11-22 17:12:15 -0800 | [diff] [blame] | 262 | #endif |