| commit | fc0b2acc754a183aa79e2abb8bca8fd915832694 | [log] [tgz] |
|---|---|---|
| author | Jarkko Nikula <jarkko.nikula@linux.intel.com> | Tue May 30 17:31:21 2017 +0300 |
| committer | Mark Brown <broonie@kernel.org> | Tue Jun 06 20:01:15 2017 +0100 |
| tree | 9c9292e44d473ed9168d0d4b023b4fbcd08bc4bd | |
| parent | 2ea659a9ef488125eb46da6eb571de5eae5c43f6 [diff] |
spi: pxa2xx: Add support for Intel Cannonlake Intel Cannonlake LPSS SPI has up to four chip selects per port like in Broxton and is clocked like Sunrisepoint and Kaby Lake. Add a new type LPSS_CNL_SSP and configuration that enable runtime chip select detection and use the same FIFO thresholds than in Sunrisepoint. Patch adds support for both Cannonlake SoC and PCH. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>