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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090050#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
Tejun Heoa22e6442008-03-10 10:25:25 +090052static int ahci_skip_host_reset;
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
Kristen Carlson Accardi31556592007-10-25 01:33:26 -040056static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58static void ahci_disable_alpm(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
60enum {
61 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090062 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070063 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
Jens Axboebe5d8212007-05-22 09:45:39 +020065 AHCI_USE_CLUSTERING = 1,
Tejun Heo12fad3f2006-05-15 21:03:55 +090066 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090067 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090068 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070069 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040070 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090071 AHCI_CMD_TBL_HDR_SZ = 0x80,
72 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
73 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
74 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 AHCI_RX_FIS_SZ,
76 AHCI_IRQ_ON_SG = (1 << 31),
77 AHCI_CMD_ATAPI = (1 << 5),
78 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090079 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +090080 AHCI_CMD_RESET = (1 << 8),
81 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -070082
83 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +090084 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +090085 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -070086
87 board_ahci = 0,
Tejun Heo7a234af2007-09-03 12:44:57 +090088 board_ahci_vt8251 = 1,
89 board_ahci_ign_iferr = 2,
90 board_ahci_sb600 = 3,
91 board_ahci_mv = 4,
Shane Huange39fc8c2008-02-22 05:00:31 -080092 board_ahci_sb700 = 5,
Linus Torvalds1da177e2005-04-16 15:20:36 -070093
94 /* global controller registers */
95 HOST_CAP = 0x00, /* host capabilities */
96 HOST_CTL = 0x04, /* global host control */
97 HOST_IRQ_STAT = 0x08, /* interrupt status */
98 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
99 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
100
101 /* HOST_CTL bits */
102 HOST_RESET = (1 << 0), /* reset controller; self-clear */
103 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
104 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
105
106 /* HOST_CAP bits */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900107 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo7d50b602007-09-23 13:19:54 +0900108 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
Tejun Heo22b49982006-01-23 21:38:44 +0900109 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400110 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900111 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900112 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900113 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900114 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115
116 /* registers for each SATA port */
117 PORT_LST_ADDR = 0x00, /* command list DMA addr */
118 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
119 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
120 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
121 PORT_IRQ_STAT = 0x10, /* interrupt status */
122 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
123 PORT_CMD = 0x18, /* port command */
124 PORT_TFDATA = 0x20, /* taskfile data */
125 PORT_SIG = 0x24, /* device TF signature */
126 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
128 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
129 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
130 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900131 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
133 /* PORT_IRQ_{STAT,MASK} bits */
134 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
135 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
136 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
137 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
138 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
139 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
140 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
141 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
142
143 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
144 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
145 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
146 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
147 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
148 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
149 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
150 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
151 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
152
Tejun Heo78cd52d2006-05-15 20:58:29 +0900153 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
154 PORT_IRQ_IF_ERR |
155 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900156 PORT_IRQ_PHYRDY |
Tejun Heo7d50b602007-09-23 13:19:54 +0900157 PORT_IRQ_UNK_FIS |
158 PORT_IRQ_BAD_PMP,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900159 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
160 PORT_IRQ_TF_ERR |
161 PORT_IRQ_HBUS_DATA_ERR,
162 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
163 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
164 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165
166 /* PORT_CMD bits */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400167 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
168 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500169 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Tejun Heo7d50b602007-09-23 13:19:54 +0900170 PORT_CMD_PMP = (1 << 17), /* PMP attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
172 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
173 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900174 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
176 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
177 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
178
Tejun Heo0be0aa92006-07-26 15:59:26 +0900179 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
181 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
182 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400183
Tejun Heo417a1a62007-09-23 13:19:55 +0900184 /* hpriv->flags bits */
185 AHCI_HFLAG_NO_NCQ = (1 << 0),
186 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
187 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
188 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
189 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
190 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
Tejun Heo6949b912007-09-23 13:19:55 +0900191 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400192 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
Jeff Garzika8785392008-02-28 15:43:48 -0500193 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
Tejun Heo417a1a62007-09-23 13:19:55 +0900194
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200195 /* ap->flags bits */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900196
197 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
198 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400199 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
200 ATA_FLAG_IPM,
Tejun Heo0c887582007-08-06 18:36:23 +0900201 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
Tejun Heoc4f77922007-12-06 15:09:43 +0900202
203 ICH_MAP = 0x90, /* ICH MAP register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204};
205
206struct ahci_cmd_hdr {
Al Viro4ca4e432007-12-30 09:32:22 +0000207 __le32 opts;
208 __le32 status;
209 __le32 tbl_addr;
210 __le32 tbl_addr_hi;
211 __le32 reserved[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212};
213
214struct ahci_sg {
Al Viro4ca4e432007-12-30 09:32:22 +0000215 __le32 addr;
216 __le32 addr_hi;
217 __le32 reserved;
218 __le32 flags_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219};
220
221struct ahci_host_priv {
Tejun Heo417a1a62007-09-23 13:19:55 +0900222 unsigned int flags; /* AHCI_HFLAG_* */
Tejun Heod447df12007-03-18 22:15:33 +0900223 u32 cap; /* cap to use */
224 u32 port_map; /* port map to use */
225 u32 saved_cap; /* saved initial cap */
226 u32 saved_port_map; /* saved initial port_map */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227};
228
229struct ahci_port_priv {
Tejun Heo7d50b602007-09-23 13:19:54 +0900230 struct ata_link *active_link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 struct ahci_cmd_hdr *cmd_slot;
232 dma_addr_t cmd_slot_dma;
233 void *cmd_tbl;
234 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235 void *rx_fis;
236 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900237 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900238 unsigned int ncq_saw_d2h:1;
239 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900240 unsigned int ncq_saw_sdb:1;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -0700241 u32 intr_mask; /* interrupts to enable */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242};
243
Tejun Heoda3dbb12007-07-16 14:29:40 +0900244static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
245static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400246static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900247static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248static void ahci_irq_clear(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249static int ahci_port_start(struct ata_port *ap);
250static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
252static void ahci_qc_prep(struct ata_queued_cmd *qc);
253static u8 ahci_check_status(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900254static void ahci_freeze(struct ata_port *ap);
255static void ahci_thaw(struct ata_port *ap);
Tejun Heo7d50b602007-09-23 13:19:54 +0900256static void ahci_pmp_attach(struct ata_port *ap);
257static void ahci_pmp_detach(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900258static void ahci_error_handler(struct ata_port *ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900259static void ahci_vt8251_error_handler(struct ata_port *ap);
Tejun Heoedc93052007-10-25 14:59:16 +0900260static void ahci_p5wdh_error_handler(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900261static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400262static int ahci_port_resume(struct ata_port *ap);
Jeff Garzika8785392008-02-28 15:43:48 -0500263static void ahci_dev_config(struct ata_device *dev);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400264static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
265static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
266 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900267#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900268static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900269static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
270static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900271#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400273static struct class_device_attribute *ahci_shost_attrs[] = {
274 &class_device_attr_link_power_management_policy,
275 NULL
276};
277
Jeff Garzik193515d2005-11-07 00:59:37 -0500278static struct scsi_host_template ahci_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279 .module = THIS_MODULE,
280 .name = DRV_NAME,
281 .ioctl = ata_scsi_ioctl,
282 .queuecommand = ata_scsi_queuecmd,
Tejun Heo12fad3f2006-05-15 21:03:55 +0900283 .change_queue_depth = ata_scsi_change_queue_depth,
284 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 .this_id = ATA_SHT_THIS_ID,
286 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
288 .emulated = ATA_SHT_EMULATED,
289 .use_clustering = AHCI_USE_CLUSTERING,
290 .proc_name = DRV_NAME,
291 .dma_boundary = AHCI_DMA_BOUNDARY,
292 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900293 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 .bios_param = ata_std_bios_param,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400295 .shost_attrs = ahci_shost_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296};
297
Jeff Garzik057ace52005-10-22 14:27:05 -0400298static const struct ata_port_operations ahci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 .check_status = ahci_check_status,
300 .check_altstatus = ahci_check_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 .dev_select = ata_noop_dev_select,
302
Jeff Garzika8785392008-02-28 15:43:48 -0500303 .dev_config = ahci_dev_config,
304
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 .tf_read = ahci_tf_read,
306
Tejun Heo7d50b602007-09-23 13:19:54 +0900307 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 .qc_prep = ahci_qc_prep,
309 .qc_issue = ahci_qc_issue,
310
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311 .irq_clear = ahci_irq_clear,
312
313 .scr_read = ahci_scr_read,
314 .scr_write = ahci_scr_write,
315
Tejun Heo78cd52d2006-05-15 20:58:29 +0900316 .freeze = ahci_freeze,
317 .thaw = ahci_thaw,
318
319 .error_handler = ahci_error_handler,
320 .post_internal_cmd = ahci_post_internal_cmd,
321
Tejun Heo7d50b602007-09-23 13:19:54 +0900322 .pmp_attach = ahci_pmp_attach,
323 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900324
Tejun Heo438ac6d2007-03-02 17:31:26 +0900325#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900326 .port_suspend = ahci_port_suspend,
327 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900328#endif
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400329 .enable_pm = ahci_enable_alpm,
330 .disable_pm = ahci_disable_alpm,
Tejun Heoc1332872006-07-26 15:59:26 +0900331
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 .port_start = ahci_port_start,
333 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334};
335
Tejun Heoad616ff2006-11-01 18:00:24 +0900336static const struct ata_port_operations ahci_vt8251_ops = {
Tejun Heoad616ff2006-11-01 18:00:24 +0900337 .check_status = ahci_check_status,
338 .check_altstatus = ahci_check_status,
339 .dev_select = ata_noop_dev_select,
340
341 .tf_read = ahci_tf_read,
342
Tejun Heo7d50b602007-09-23 13:19:54 +0900343 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Tejun Heoad616ff2006-11-01 18:00:24 +0900344 .qc_prep = ahci_qc_prep,
345 .qc_issue = ahci_qc_issue,
346
Tejun Heoad616ff2006-11-01 18:00:24 +0900347 .irq_clear = ahci_irq_clear,
348
349 .scr_read = ahci_scr_read,
350 .scr_write = ahci_scr_write,
351
352 .freeze = ahci_freeze,
353 .thaw = ahci_thaw,
354
355 .error_handler = ahci_vt8251_error_handler,
356 .post_internal_cmd = ahci_post_internal_cmd,
357
Tejun Heo7d50b602007-09-23 13:19:54 +0900358 .pmp_attach = ahci_pmp_attach,
359 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900360
Tejun Heo438ac6d2007-03-02 17:31:26 +0900361#ifdef CONFIG_PM
Tejun Heoad616ff2006-11-01 18:00:24 +0900362 .port_suspend = ahci_port_suspend,
363 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900364#endif
Tejun Heoad616ff2006-11-01 18:00:24 +0900365
366 .port_start = ahci_port_start,
367 .port_stop = ahci_port_stop,
368};
369
Tejun Heoedc93052007-10-25 14:59:16 +0900370static const struct ata_port_operations ahci_p5wdh_ops = {
371 .check_status = ahci_check_status,
372 .check_altstatus = ahci_check_status,
373 .dev_select = ata_noop_dev_select,
374
375 .tf_read = ahci_tf_read,
376
377 .qc_defer = sata_pmp_qc_defer_cmd_switch,
378 .qc_prep = ahci_qc_prep,
379 .qc_issue = ahci_qc_issue,
380
381 .irq_clear = ahci_irq_clear,
382
383 .scr_read = ahci_scr_read,
384 .scr_write = ahci_scr_write,
385
386 .freeze = ahci_freeze,
387 .thaw = ahci_thaw,
388
389 .error_handler = ahci_p5wdh_error_handler,
390 .post_internal_cmd = ahci_post_internal_cmd,
391
392 .pmp_attach = ahci_pmp_attach,
393 .pmp_detach = ahci_pmp_detach,
394
395#ifdef CONFIG_PM
396 .port_suspend = ahci_port_suspend,
397 .port_resume = ahci_port_resume,
398#endif
399
400 .port_start = ahci_port_start,
401 .port_stop = ahci_port_stop,
402};
403
Tejun Heo417a1a62007-09-23 13:19:55 +0900404#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
405
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100406static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407 /* board_ahci */
408 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900409 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900410 .link_flags = AHCI_LFLAG_COMMON,
Brett Russ7da79312005-09-01 21:53:34 -0400411 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400412 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413 .port_ops = &ahci_ops,
414 },
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200415 /* board_ahci_vt8251 */
416 {
Tejun Heo6949b912007-09-23 13:19:55 +0900417 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900418 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900419 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200420 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400421 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900422 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200423 },
Tejun Heo41669552006-11-29 11:33:14 +0900424 /* board_ahci_ign_iferr */
425 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900426 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
427 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900428 .link_flags = AHCI_LFLAG_COMMON,
Tejun Heo41669552006-11-29 11:33:14 +0900429 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400430 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900431 .port_ops = &ahci_ops,
432 },
Conke Hu55a61602007-03-27 18:33:05 +0800433 /* board_ahci_sb600 */
434 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900435 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Jeff Garzika8785392008-02-28 15:43:48 -0500436 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900437 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900438 .link_flags = AHCI_LFLAG_COMMON,
Conke Hu55a61602007-03-27 18:33:05 +0800439 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400440 .udma_mask = ATA_UDMA6,
Conke Hu55a61602007-03-27 18:33:05 +0800441 .port_ops = &ahci_ops,
442 },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400443 /* board_ahci_mv */
444 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900445 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
446 AHCI_HFLAG_MV_PATA),
Jeff Garzikcd70c262007-07-08 02:29:42 -0400447 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo417a1a62007-09-23 13:19:55 +0900448 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
Tejun Heo0c887582007-08-06 18:36:23 +0900449 .link_flags = AHCI_LFLAG_COMMON,
Jeff Garzikcd70c262007-07-08 02:29:42 -0400450 .pio_mask = 0x1f, /* pio0-4 */
451 .udma_mask = ATA_UDMA6,
452 .port_ops = &ahci_ops,
453 },
Shane Huange39fc8c2008-02-22 05:00:31 -0800454 /* board_ahci_sb700 */
455 {
456 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
457 AHCI_HFLAG_NO_PMP),
458 .flags = AHCI_FLAG_COMMON,
459 .link_flags = AHCI_LFLAG_COMMON,
460 .pio_mask = 0x1f, /* pio0-4 */
461 .udma_mask = ATA_UDMA6,
462 .port_ops = &ahci_ops,
463 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464};
465
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500466static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400467 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400468 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
469 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
470 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
471 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
472 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900473 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400474 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
475 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
476 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
477 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900478 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
479 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
480 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
481 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
482 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
483 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
484 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
485 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
486 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
487 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
488 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
489 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
490 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
491 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
492 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
493 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
494 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400495 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
496 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800497 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
498 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400499
Tejun Heoe34bb372007-02-26 20:24:03 +0900500 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
501 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
502 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400503
504 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800505 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800506 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
507 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
508 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
509 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
510 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
511 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400512
513 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400514 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900515 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400516
517 /* NVIDIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400518 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
519 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
520 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
521 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
Peer Chen6fbf5ba2006-12-20 14:18:00 -0500522 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
523 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
524 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
525 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
526 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
Peer Chen895663c2006-11-02 17:59:46 -0500530 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
531 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
532 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
533 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
534 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
535 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
536 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
537 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
Peer Chen0522b282007-06-07 18:05:12 +0800538 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
543 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
544 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
545 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
546 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
547 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
548 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
549 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
555 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
556 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
557 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
558 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
559 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
560 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
561 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
peerchen6ba86952007-12-03 22:20:37 +0800562 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
Peer Chen71008192007-09-24 10:16:25 +0800566 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
567 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
568 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
569 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
570 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
571 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
572 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
573 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
peerchen70d562c2008-03-06 21:22:41 +0800574 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
578 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
579 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
580 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
581 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
582 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
583 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
584 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
585 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400586
Jeff Garzik95916ed2006-07-29 04:10:14 -0400587 /* SiS */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400588 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
589 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
590 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400591
Jeff Garzikcd70c262007-07-08 02:29:42 -0400592 /* Marvell */
593 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
594
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500595 /* Generic, PCI class code for AHCI */
596 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500597 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500598
Linus Torvalds1da177e2005-04-16 15:20:36 -0700599 { } /* terminate list */
600};
601
602
603static struct pci_driver ahci_pci_driver = {
604 .name = DRV_NAME,
605 .id_table = ahci_pci_tbl,
606 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900607 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900608#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900609 .suspend = ahci_pci_device_suspend,
610 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900611#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612};
613
614
Tejun Heo98fa4b62006-11-02 12:17:23 +0900615static inline int ahci_nr_ports(u32 cap)
616{
617 return (cap & 0x1f) + 1;
618}
619
Jeff Garzikdab632e2007-05-28 08:33:01 -0400620static inline void __iomem *__ahci_port_base(struct ata_host *host,
621 unsigned int port_no)
622{
623 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
624
625 return mmio + 0x100 + (port_no * 0x80);
626}
627
Tejun Heo4447d352007-04-17 23:44:08 +0900628static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400630 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631}
632
Tejun Heob710a1f2008-01-05 23:11:57 +0900633static void ahci_enable_ahci(void __iomem *mmio)
634{
635 u32 tmp;
636
637 /* turn on AHCI_EN */
638 tmp = readl(mmio + HOST_CTL);
639 if (!(tmp & HOST_AHCI_EN)) {
640 tmp |= HOST_AHCI_EN;
641 writel(tmp, mmio + HOST_CTL);
642 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
643 WARN_ON(!(tmp & HOST_AHCI_EN));
644 }
645}
646
Tejun Heod447df12007-03-18 22:15:33 +0900647/**
648 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900649 * @pdev: target PCI device
Tejun Heo4447d352007-04-17 23:44:08 +0900650 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900651 *
652 * Some registers containing configuration info might be setup by
653 * BIOS and might be cleared on reset. This function saves the
654 * initial values of those registers into @hpriv such that they
655 * can be restored after controller reset.
656 *
657 * If inconsistent, config values are fixed up by this function.
658 *
659 * LOCKING:
660 * None.
661 */
Tejun Heo4447d352007-04-17 23:44:08 +0900662static void ahci_save_initial_config(struct pci_dev *pdev,
Tejun Heo4447d352007-04-17 23:44:08 +0900663 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900664{
Tejun Heo4447d352007-04-17 23:44:08 +0900665 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900666 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900667 int i;
Tejun Heod447df12007-03-18 22:15:33 +0900668
Tejun Heob710a1f2008-01-05 23:11:57 +0900669 /* make sure AHCI mode is enabled before accessing CAP */
670 ahci_enable_ahci(mmio);
671
Tejun Heod447df12007-03-18 22:15:33 +0900672 /* Values prefixed with saved_ are written back to host after
673 * reset. Values without are used for driver operation.
674 */
675 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
676 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
677
Tejun Heo274c1fd2007-07-16 14:29:40 +0900678 /* some chips have errata preventing 64bit use */
Tejun Heo417a1a62007-09-23 13:19:55 +0900679 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
Tejun Heoc7a42152007-05-18 16:23:19 +0200680 dev_printk(KERN_INFO, &pdev->dev,
681 "controller can't do 64bit DMA, forcing 32bit\n");
682 cap &= ~HOST_CAP_64;
683 }
684
Tejun Heo417a1a62007-09-23 13:19:55 +0900685 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
Tejun Heo274c1fd2007-07-16 14:29:40 +0900686 dev_printk(KERN_INFO, &pdev->dev,
687 "controller can't do NCQ, turning off CAP_NCQ\n");
688 cap &= ~HOST_CAP_NCQ;
689 }
690
Roel Kluin258cd842008-03-09 21:42:40 +0100691 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
Tejun Heo6949b912007-09-23 13:19:55 +0900692 dev_printk(KERN_INFO, &pdev->dev,
693 "controller can't do PMP, turning off CAP_PMP\n");
694 cap &= ~HOST_CAP_PMP;
695 }
696
Jeff Garzikcd70c262007-07-08 02:29:42 -0400697 /*
698 * Temporary Marvell 6145 hack: PATA port presence
699 * is asserted through the standard AHCI port
700 * presence register, as bit 4 (counting from 0)
701 */
Tejun Heo417a1a62007-09-23 13:19:55 +0900702 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jeff Garzikcd70c262007-07-08 02:29:42 -0400703 dev_printk(KERN_ERR, &pdev->dev,
704 "MV_AHCI HACK: port_map %x -> %x\n",
705 hpriv->port_map,
706 hpriv->port_map & 0xf);
707
708 port_map &= 0xf;
709 }
710
Tejun Heo17199b12007-03-18 22:26:53 +0900711 /* cross check port_map and cap.n_ports */
Tejun Heo7a234af2007-09-03 12:44:57 +0900712 if (port_map) {
Tejun Heo837f5f82008-02-06 15:13:51 +0900713 int map_ports = 0;
Tejun Heo17199b12007-03-18 22:26:53 +0900714
Tejun Heo837f5f82008-02-06 15:13:51 +0900715 for (i = 0; i < AHCI_MAX_PORTS; i++)
716 if (port_map & (1 << i))
717 map_ports++;
Tejun Heo17199b12007-03-18 22:26:53 +0900718
Tejun Heo837f5f82008-02-06 15:13:51 +0900719 /* If PI has more ports than n_ports, whine, clear
720 * port_map and let it be generated from n_ports.
Tejun Heo17199b12007-03-18 22:26:53 +0900721 */
Tejun Heo837f5f82008-02-06 15:13:51 +0900722 if (map_ports > ahci_nr_ports(cap)) {
Tejun Heo4447d352007-04-17 23:44:08 +0900723 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo837f5f82008-02-06 15:13:51 +0900724 "implemented port map (0x%x) contains more "
725 "ports than nr_ports (%u), using nr_ports\n",
726 port_map, ahci_nr_ports(cap));
Tejun Heo7a234af2007-09-03 12:44:57 +0900727 port_map = 0;
728 }
729 }
730
731 /* fabricate port_map from cap.nr_ports */
732 if (!port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900733 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo7a234af2007-09-03 12:44:57 +0900734 dev_printk(KERN_WARNING, &pdev->dev,
735 "forcing PORTS_IMPL to 0x%x\n", port_map);
736
737 /* write the fixed up value to the PI register */
738 hpriv->saved_port_map = port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900739 }
740
Tejun Heod447df12007-03-18 22:15:33 +0900741 /* record values to use during operation */
742 hpriv->cap = cap;
743 hpriv->port_map = port_map;
744}
745
746/**
747 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900748 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900749 *
750 * Restore initial config stored by ahci_save_initial_config().
751 *
752 * LOCKING:
753 * None.
754 */
Tejun Heo4447d352007-04-17 23:44:08 +0900755static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900756{
Tejun Heo4447d352007-04-17 23:44:08 +0900757 struct ahci_host_priv *hpriv = host->private_data;
758 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
759
Tejun Heod447df12007-03-18 22:15:33 +0900760 writel(hpriv->saved_cap, mmio + HOST_CAP);
761 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
762 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
763}
764
Tejun Heo203ef6c2007-07-16 14:29:40 +0900765static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900767 static const int offset[] = {
768 [SCR_STATUS] = PORT_SCR_STAT,
769 [SCR_CONTROL] = PORT_SCR_CTL,
770 [SCR_ERROR] = PORT_SCR_ERR,
771 [SCR_ACTIVE] = PORT_SCR_ACT,
772 [SCR_NOTIFICATION] = PORT_SCR_NTF,
773 };
774 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775
Tejun Heo203ef6c2007-07-16 14:29:40 +0900776 if (sc_reg < ARRAY_SIZE(offset) &&
777 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
778 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900779 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780}
781
Tejun Heo203ef6c2007-07-16 14:29:40 +0900782static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900784 void __iomem *port_mmio = ahci_port_base(ap);
785 int offset = ahci_scr_offset(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786
Tejun Heo203ef6c2007-07-16 14:29:40 +0900787 if (offset) {
788 *val = readl(port_mmio + offset);
789 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900791 return -EINVAL;
792}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793
Tejun Heo203ef6c2007-07-16 14:29:40 +0900794static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
795{
796 void __iomem *port_mmio = ahci_port_base(ap);
797 int offset = ahci_scr_offset(ap, sc_reg);
798
799 if (offset) {
800 writel(val, port_mmio + offset);
801 return 0;
802 }
803 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804}
805
Tejun Heo4447d352007-04-17 23:44:08 +0900806static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900807{
Tejun Heo4447d352007-04-17 23:44:08 +0900808 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900809 u32 tmp;
810
Tejun Heod8fcd112006-07-26 15:59:25 +0900811 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900812 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900813 tmp |= PORT_CMD_START;
814 writel(tmp, port_mmio + PORT_CMD);
815 readl(port_mmio + PORT_CMD); /* flush */
816}
817
Tejun Heo4447d352007-04-17 23:44:08 +0900818static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900819{
Tejun Heo4447d352007-04-17 23:44:08 +0900820 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900821 u32 tmp;
822
823 tmp = readl(port_mmio + PORT_CMD);
824
Tejun Heod8fcd112006-07-26 15:59:25 +0900825 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900826 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
827 return 0;
828
Tejun Heod8fcd112006-07-26 15:59:25 +0900829 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900830 tmp &= ~PORT_CMD_START;
831 writel(tmp, port_mmio + PORT_CMD);
832
Tejun Heod8fcd112006-07-26 15:59:25 +0900833 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900834 tmp = ata_wait_register(port_mmio + PORT_CMD,
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400835 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900836 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900837 return -EIO;
838
839 return 0;
840}
841
Tejun Heo4447d352007-04-17 23:44:08 +0900842static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900843{
Tejun Heo4447d352007-04-17 23:44:08 +0900844 void __iomem *port_mmio = ahci_port_base(ap);
845 struct ahci_host_priv *hpriv = ap->host->private_data;
846 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900847 u32 tmp;
848
849 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900850 if (hpriv->cap & HOST_CAP_64)
851 writel((pp->cmd_slot_dma >> 16) >> 16,
852 port_mmio + PORT_LST_ADDR_HI);
853 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900854
Tejun Heo4447d352007-04-17 23:44:08 +0900855 if (hpriv->cap & HOST_CAP_64)
856 writel((pp->rx_fis_dma >> 16) >> 16,
857 port_mmio + PORT_FIS_ADDR_HI);
858 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900859
860 /* enable FIS reception */
861 tmp = readl(port_mmio + PORT_CMD);
862 tmp |= PORT_CMD_FIS_RX;
863 writel(tmp, port_mmio + PORT_CMD);
864
865 /* flush */
866 readl(port_mmio + PORT_CMD);
867}
868
Tejun Heo4447d352007-04-17 23:44:08 +0900869static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900870{
Tejun Heo4447d352007-04-17 23:44:08 +0900871 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900872 u32 tmp;
873
874 /* disable FIS reception */
875 tmp = readl(port_mmio + PORT_CMD);
876 tmp &= ~PORT_CMD_FIS_RX;
877 writel(tmp, port_mmio + PORT_CMD);
878
879 /* wait for completion, spec says 500ms, give it 1000 */
880 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
881 PORT_CMD_FIS_ON, 10, 1000);
882 if (tmp & PORT_CMD_FIS_ON)
883 return -EBUSY;
884
885 return 0;
886}
887
Tejun Heo4447d352007-04-17 23:44:08 +0900888static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900889{
Tejun Heo4447d352007-04-17 23:44:08 +0900890 struct ahci_host_priv *hpriv = ap->host->private_data;
891 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900892 u32 cmd;
893
894 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
895
896 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +0900897 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +0900898 cmd |= PORT_CMD_SPIN_UP;
899 writel(cmd, port_mmio + PORT_CMD);
900 }
901
902 /* wake up link */
903 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
904}
905
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400906static void ahci_disable_alpm(struct ata_port *ap)
907{
908 struct ahci_host_priv *hpriv = ap->host->private_data;
909 void __iomem *port_mmio = ahci_port_base(ap);
910 u32 cmd;
911 struct ahci_port_priv *pp = ap->private_data;
912
913 /* IPM bits should be disabled by libata-core */
914 /* get the existing command bits */
915 cmd = readl(port_mmio + PORT_CMD);
916
917 /* disable ALPM and ASP */
918 cmd &= ~PORT_CMD_ASP;
919 cmd &= ~PORT_CMD_ALPE;
920
921 /* force the interface back to active */
922 cmd |= PORT_CMD_ICC_ACTIVE;
923
924 /* write out new cmd value */
925 writel(cmd, port_mmio + PORT_CMD);
926 cmd = readl(port_mmio + PORT_CMD);
927
928 /* wait 10ms to be sure we've come out of any low power state */
929 msleep(10);
930
931 /* clear out any PhyRdy stuff from interrupt status */
932 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
933
934 /* go ahead and clean out PhyRdy Change from Serror too */
935 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
936
937 /*
938 * Clear flag to indicate that we should ignore all PhyRdy
939 * state changes
940 */
941 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
942
943 /*
944 * Enable interrupts on Phy Ready.
945 */
946 pp->intr_mask |= PORT_IRQ_PHYRDY;
947 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
948
949 /*
950 * don't change the link pm policy - we can be called
951 * just to turn of link pm temporarily
952 */
953}
954
955static int ahci_enable_alpm(struct ata_port *ap,
956 enum link_pm policy)
957{
958 struct ahci_host_priv *hpriv = ap->host->private_data;
959 void __iomem *port_mmio = ahci_port_base(ap);
960 u32 cmd;
961 struct ahci_port_priv *pp = ap->private_data;
962 u32 asp;
963
964 /* Make sure the host is capable of link power management */
965 if (!(hpriv->cap & HOST_CAP_ALPM))
966 return -EINVAL;
967
968 switch (policy) {
969 case MAX_PERFORMANCE:
970 case NOT_AVAILABLE:
971 /*
972 * if we came here with NOT_AVAILABLE,
973 * it just means this is the first time we
974 * have tried to enable - default to max performance,
975 * and let the user go to lower power modes on request.
976 */
977 ahci_disable_alpm(ap);
978 return 0;
979 case MIN_POWER:
980 /* configure HBA to enter SLUMBER */
981 asp = PORT_CMD_ASP;
982 break;
983 case MEDIUM_POWER:
984 /* configure HBA to enter PARTIAL */
985 asp = 0;
986 break;
987 default:
988 return -EINVAL;
989 }
990
991 /*
992 * Disable interrupts on Phy Ready. This keeps us from
993 * getting woken up due to spurious phy ready interrupts
994 * TBD - Hot plug should be done via polling now, is
995 * that even supported?
996 */
997 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
998 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
999
1000 /*
1001 * Set a flag to indicate that we should ignore all PhyRdy
1002 * state changes since these can happen now whenever we
1003 * change link state
1004 */
1005 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1006
1007 /* get the existing command bits */
1008 cmd = readl(port_mmio + PORT_CMD);
1009
1010 /*
1011 * Set ASP based on Policy
1012 */
1013 cmd |= asp;
1014
1015 /*
1016 * Setting this bit will instruct the HBA to aggressively
1017 * enter a lower power link state when it's appropriate and
1018 * based on the value set above for ASP
1019 */
1020 cmd |= PORT_CMD_ALPE;
1021
1022 /* write out new cmd value */
1023 writel(cmd, port_mmio + PORT_CMD);
1024 cmd = readl(port_mmio + PORT_CMD);
1025
1026 /* IPM bits should be set by libata-core */
1027 return 0;
1028}
1029
Tejun Heo438ac6d2007-03-02 17:31:26 +09001030#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +09001031static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001032{
Tejun Heo4447d352007-04-17 23:44:08 +09001033 struct ahci_host_priv *hpriv = ap->host->private_data;
1034 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001035 u32 cmd, scontrol;
1036
Tejun Heo4447d352007-04-17 23:44:08 +09001037 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +09001038 return;
1039
1040 /* put device into listen mode, first set PxSCTL.DET to 0 */
1041 scontrol = readl(port_mmio + PORT_SCR_CTL);
1042 scontrol &= ~0xf;
1043 writel(scontrol, port_mmio + PORT_SCR_CTL);
1044
1045 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +09001046 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +09001047 cmd &= ~PORT_CMD_SPIN_UP;
1048 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001049}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001050#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +09001051
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001052static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001053{
Tejun Heo0be0aa92006-07-26 15:59:26 +09001054 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001055 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001056
1057 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001058 ahci_start_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001059}
1060
Tejun Heo4447d352007-04-17 23:44:08 +09001061static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001062{
1063 int rc;
1064
1065 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001066 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001067 if (rc) {
1068 *emsg = "failed to stop engine";
1069 return rc;
1070 }
1071
1072 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001073 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001074 if (rc) {
1075 *emsg = "failed stop FIS RX";
1076 return rc;
1077 }
1078
Tejun Heo0be0aa92006-07-26 15:59:26 +09001079 return 0;
1080}
1081
Tejun Heo4447d352007-04-17 23:44:08 +09001082static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001083{
Tejun Heo4447d352007-04-17 23:44:08 +09001084 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heo49f29092007-11-19 16:03:44 +09001085 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001086 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +09001087 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +09001088
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001089 /* we must be in AHCI mode, before using anything
1090 * AHCI-specific, such as HOST_RESET.
1091 */
Tejun Heob710a1f2008-01-05 23:11:57 +09001092 ahci_enable_ahci(mmio);
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001093
1094 /* global controller reset */
Tejun Heoa22e6442008-03-10 10:25:25 +09001095 if (!ahci_skip_host_reset) {
1096 tmp = readl(mmio + HOST_CTL);
1097 if ((tmp & HOST_RESET) == 0) {
1098 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1099 readl(mmio + HOST_CTL); /* flush */
1100 }
Tejun Heod91542c2006-07-26 15:59:26 +09001101
Tejun Heoa22e6442008-03-10 10:25:25 +09001102 /* reset must complete within 1 second, or
1103 * the hardware should be considered fried.
1104 */
1105 ssleep(1);
Tejun Heod91542c2006-07-26 15:59:26 +09001106
Tejun Heoa22e6442008-03-10 10:25:25 +09001107 tmp = readl(mmio + HOST_CTL);
1108 if (tmp & HOST_RESET) {
1109 dev_printk(KERN_ERR, host->dev,
1110 "controller reset failed (0x%x)\n", tmp);
1111 return -EIO;
1112 }
Tejun Heod91542c2006-07-26 15:59:26 +09001113
Tejun Heoa22e6442008-03-10 10:25:25 +09001114 /* turn on AHCI mode */
1115 ahci_enable_ahci(mmio);
Tejun Heo98fa4b62006-11-02 12:17:23 +09001116
Tejun Heoa22e6442008-03-10 10:25:25 +09001117 /* Some registers might be cleared on reset. Restore
1118 * initial values.
1119 */
1120 ahci_restore_initial_config(host);
1121 } else
1122 dev_printk(KERN_INFO, host->dev,
1123 "skipping global host reset\n");
Tejun Heod91542c2006-07-26 15:59:26 +09001124
1125 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1126 u16 tmp16;
1127
1128 /* configure PCS */
1129 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +09001130 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1131 tmp16 |= hpriv->port_map;
1132 pci_write_config_word(pdev, 0x92, tmp16);
1133 }
Tejun Heod91542c2006-07-26 15:59:26 +09001134 }
1135
1136 return 0;
1137}
1138
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001139static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1140 int port_no, void __iomem *mmio,
1141 void __iomem *port_mmio)
1142{
1143 const char *emsg = NULL;
1144 int rc;
1145 u32 tmp;
1146
1147 /* make sure port is not active */
1148 rc = ahci_deinit_port(ap, &emsg);
1149 if (rc)
1150 dev_printk(KERN_WARNING, &pdev->dev,
1151 "%s (%d)\n", emsg, rc);
1152
1153 /* clear SError */
1154 tmp = readl(port_mmio + PORT_SCR_ERR);
1155 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1156 writel(tmp, port_mmio + PORT_SCR_ERR);
1157
1158 /* clear port IRQ */
1159 tmp = readl(port_mmio + PORT_IRQ_STAT);
1160 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1161 if (tmp)
1162 writel(tmp, port_mmio + PORT_IRQ_STAT);
1163
1164 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1165}
1166
Tejun Heo4447d352007-04-17 23:44:08 +09001167static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001168{
Tejun Heo417a1a62007-09-23 13:19:55 +09001169 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001170 struct pci_dev *pdev = to_pci_dev(host->dev);
1171 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001172 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -04001173 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +09001174 u32 tmp;
1175
Tejun Heo417a1a62007-09-23 13:19:55 +09001176 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jeff Garzikcd70c262007-07-08 02:29:42 -04001177 port_mmio = __ahci_port_base(host, 4);
1178
1179 writel(0, port_mmio + PORT_IRQ_MASK);
1180
1181 /* clear port IRQ */
1182 tmp = readl(port_mmio + PORT_IRQ_STAT);
1183 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1184 if (tmp)
1185 writel(tmp, port_mmio + PORT_IRQ_STAT);
1186 }
1187
Tejun Heo4447d352007-04-17 23:44:08 +09001188 for (i = 0; i < host->n_ports; i++) {
1189 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +09001190
Jeff Garzikcd70c262007-07-08 02:29:42 -04001191 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09001192 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +09001193 continue;
Tejun Heod91542c2006-07-26 15:59:26 +09001194
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001195 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +09001196 }
1197
1198 tmp = readl(mmio + HOST_CTL);
1199 VPRINTK("HOST_CTL 0x%x\n", tmp);
1200 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1201 tmp = readl(mmio + HOST_CTL);
1202 VPRINTK("HOST_CTL 0x%x\n", tmp);
1203}
1204
Jeff Garzika8785392008-02-28 15:43:48 -05001205static void ahci_dev_config(struct ata_device *dev)
1206{
1207 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1208
1209 if (hpriv->flags & AHCI_HFLAG_SECT255)
1210 dev->max_sectors = 255;
1211}
1212
Tejun Heo422b7592005-12-19 22:37:17 +09001213static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001214{
Tejun Heo4447d352007-04-17 23:44:08 +09001215 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +09001217 u32 tmp;
1218
1219 tmp = readl(port_mmio + PORT_SIG);
1220 tf.lbah = (tmp >> 24) & 0xff;
1221 tf.lbam = (tmp >> 16) & 0xff;
1222 tf.lbal = (tmp >> 8) & 0xff;
1223 tf.nsect = (tmp) & 0xff;
1224
1225 return ata_dev_classify(&tf);
1226}
1227
Tejun Heo12fad3f2006-05-15 21:03:55 +09001228static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1229 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +09001230{
Tejun Heo12fad3f2006-05-15 21:03:55 +09001231 dma_addr_t cmd_tbl_dma;
1232
1233 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1234
1235 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1236 pp->cmd_slot[tag].status = 0;
1237 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1238 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +09001239}
1240
Tejun Heod2e75df2007-07-16 14:29:39 +09001241static int ahci_kick_engine(struct ata_port *ap, int force_restart)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001242{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001243 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Jeff Garzikcca39742006-08-24 03:19:22 -04001244 struct ahci_host_priv *hpriv = ap->host->private_data;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001245 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +09001246 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001247
Tejun Heod2e75df2007-07-16 14:29:39 +09001248 /* do we need to kick the port? */
1249 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1250 if (!busy && !force_restart)
1251 return 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001252
Tejun Heod2e75df2007-07-16 14:29:39 +09001253 /* stop engine */
1254 rc = ahci_stop_engine(ap);
1255 if (rc)
1256 goto out_restart;
1257
1258 /* need to do CLO? */
1259 if (!busy) {
1260 rc = 0;
1261 goto out_restart;
1262 }
1263
1264 if (!(hpriv->cap & HOST_CAP_CLO)) {
1265 rc = -EOPNOTSUPP;
1266 goto out_restart;
1267 }
1268
1269 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001270 tmp = readl(port_mmio + PORT_CMD);
1271 tmp |= PORT_CMD_CLO;
1272 writel(tmp, port_mmio + PORT_CMD);
1273
Tejun Heod2e75df2007-07-16 14:29:39 +09001274 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001275 tmp = ata_wait_register(port_mmio + PORT_CMD,
1276 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1277 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001278 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001279
Tejun Heod2e75df2007-07-16 14:29:39 +09001280 /* restart engine */
1281 out_restart:
1282 ahci_start_engine(ap);
1283 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001284}
1285
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001286static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1287 struct ata_taskfile *tf, int is_cmd, u16 flags,
1288 unsigned long timeout_msec)
1289{
1290 const u32 cmd_fis_len = 5; /* five dwords */
1291 struct ahci_port_priv *pp = ap->private_data;
1292 void __iomem *port_mmio = ahci_port_base(ap);
1293 u8 *fis = pp->cmd_tbl;
1294 u32 tmp;
1295
1296 /* prep the command */
1297 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1298 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1299
1300 /* issue & wait */
1301 writel(1, port_mmio + PORT_CMD_ISSUE);
1302
1303 if (timeout_msec) {
1304 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1305 1, timeout_msec);
1306 if (tmp & 0x1) {
1307 ahci_kick_engine(ap, 1);
1308 return -EBUSY;
1309 }
1310 } else
1311 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1312
1313 return 0;
1314}
1315
Tejun Heocc0680a2007-08-06 18:36:23 +09001316static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001317 int pmp, unsigned long deadline)
Tejun Heo4658f792006-03-22 21:07:03 +09001318{
Tejun Heocc0680a2007-08-06 18:36:23 +09001319 struct ata_port *ap = link->ap;
Tejun Heo4658f792006-03-22 21:07:03 +09001320 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001321 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001322 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001323 int rc;
1324
1325 DPRINTK("ENTER\n");
1326
Tejun Heocc0680a2007-08-06 18:36:23 +09001327 if (ata_link_offline(link)) {
Tejun Heoc2a65852006-04-03 01:58:06 +09001328 DPRINTK("PHY reports no device\n");
1329 *class = ATA_DEV_NONE;
1330 return 0;
1331 }
1332
Tejun Heo4658f792006-03-22 21:07:03 +09001333 /* prepare for SRST (AHCI-1.1 10.4.1) */
Tejun Heod2e75df2007-07-16 14:29:39 +09001334 rc = ahci_kick_engine(ap, 1);
Tejun Heo994056d2007-12-06 15:02:48 +09001335 if (rc && rc != -EOPNOTSUPP)
Tejun Heocc0680a2007-08-06 18:36:23 +09001336 ata_link_printk(link, KERN_WARNING,
Tejun Heo994056d2007-12-06 15:02:48 +09001337 "failed to reset engine (errno=%d)\n", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001338
Tejun Heocc0680a2007-08-06 18:36:23 +09001339 ata_tf_init(link->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001340
1341 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001342 msecs = 0;
1343 now = jiffies;
1344 if (time_after(now, deadline))
1345 msecs = jiffies_to_msecs(deadline - now);
1346
Tejun Heo4658f792006-03-22 21:07:03 +09001347 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001348 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001349 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001350 rc = -EIO;
1351 reason = "1st FIS failed";
1352 goto fail;
1353 }
1354
1355 /* spec says at least 5us, but be generous and sleep for 1ms */
1356 msleep(1);
1357
1358 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001359 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001360 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001361
Tejun Heo88ff6ea2007-10-16 14:21:24 -07001362 /* wait a while before checking status */
1363 ata_wait_after_reset(ap, deadline);
Tejun Heo4658f792006-03-22 21:07:03 +09001364
Tejun Heo9b893912007-02-02 16:50:52 +09001365 rc = ata_wait_ready(ap, deadline);
1366 /* link occupied, -ENODEV too is an error */
1367 if (rc) {
1368 reason = "device not ready";
1369 goto fail;
Tejun Heo4658f792006-03-22 21:07:03 +09001370 }
Tejun Heo9b893912007-02-02 16:50:52 +09001371 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001372
1373 DPRINTK("EXIT, class=%u\n", *class);
1374 return 0;
1375
Tejun Heo4658f792006-03-22 21:07:03 +09001376 fail:
Tejun Heocc0680a2007-08-06 18:36:23 +09001377 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001378 return rc;
1379}
1380
Tejun Heocc0680a2007-08-06 18:36:23 +09001381static int ahci_softreset(struct ata_link *link, unsigned int *class,
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001382 unsigned long deadline)
1383{
Tejun Heo7d50b602007-09-23 13:19:54 +09001384 int pmp = 0;
1385
1386 if (link->ap->flags & ATA_FLAG_PMP)
1387 pmp = SATA_PMP_CTRL_PORT;
1388
1389 return ahci_do_softreset(link, class, pmp, deadline);
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001390}
1391
Tejun Heocc0680a2007-08-06 18:36:23 +09001392static int ahci_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001393 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001394{
Tejun Heocc0680a2007-08-06 18:36:23 +09001395 struct ata_port *ap = link->ap;
Tejun Heo42969712006-05-31 18:28:18 +09001396 struct ahci_port_priv *pp = ap->private_data;
1397 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1398 struct ata_taskfile tf;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001399 int rc;
1400
1401 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402
Tejun Heo4447d352007-04-17 23:44:08 +09001403 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001404
1405 /* clear D2H reception area to properly wait for D2H FIS */
Tejun Heocc0680a2007-08-06 18:36:23 +09001406 ata_tf_init(link->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001407 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001408 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001409
Tejun Heocc0680a2007-08-06 18:36:23 +09001410 rc = sata_std_hardreset(link, class, deadline);
Tejun Heo42969712006-05-31 18:28:18 +09001411
Tejun Heo4447d352007-04-17 23:44:08 +09001412 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413
Tejun Heocc0680a2007-08-06 18:36:23 +09001414 if (rc == 0 && ata_link_online(link))
Tejun Heo4bd00f62006-02-11 16:26:02 +09001415 *class = ahci_dev_classify(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09001416 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001417 *class = ATA_DEV_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001418
Tejun Heo4bd00f62006-02-11 16:26:02 +09001419 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1420 return rc;
1421}
1422
Tejun Heocc0680a2007-08-06 18:36:23 +09001423static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001424 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001425{
Tejun Heocc0680a2007-08-06 18:36:23 +09001426 struct ata_port *ap = link->ap;
Tejun Heoda3dbb12007-07-16 14:29:40 +09001427 u32 serror;
Tejun Heoad616ff2006-11-01 18:00:24 +09001428 int rc;
1429
1430 DPRINTK("ENTER\n");
1431
Tejun Heo4447d352007-04-17 23:44:08 +09001432 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001433
Tejun Heocc0680a2007-08-06 18:36:23 +09001434 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heod4b2bab2007-02-02 16:50:52 +09001435 deadline);
Tejun Heoad616ff2006-11-01 18:00:24 +09001436
1437 /* vt8251 needs SError cleared for the port to operate */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001438 ahci_scr_read(ap, SCR_ERROR, &serror);
1439 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heoad616ff2006-11-01 18:00:24 +09001440
Tejun Heo4447d352007-04-17 23:44:08 +09001441 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001442
1443 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1444
1445 /* vt8251 doesn't clear BSY on signature FIS reception,
1446 * request follow-up softreset.
1447 */
1448 return rc ?: -EAGAIN;
1449}
1450
Tejun Heoedc93052007-10-25 14:59:16 +09001451static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1452 unsigned long deadline)
1453{
1454 struct ata_port *ap = link->ap;
1455 struct ahci_port_priv *pp = ap->private_data;
1456 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1457 struct ata_taskfile tf;
1458 int rc;
1459
1460 ahci_stop_engine(ap);
1461
1462 /* clear D2H reception area to properly wait for D2H FIS */
1463 ata_tf_init(link->device, &tf);
1464 tf.command = 0x80;
1465 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1466
1467 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1468 deadline);
1469
1470 ahci_start_engine(ap);
1471
1472 if (rc || ata_link_offline(link))
1473 return rc;
1474
1475 /* spec mandates ">= 2ms" before checking status */
1476 msleep(150);
1477
1478 /* The pseudo configuration device on SIMG4726 attached to
1479 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1480 * hardreset if no device is attached to the first downstream
1481 * port && the pseudo device locks up on SRST w/ PMP==0. To
1482 * work around this, wait for !BSY only briefly. If BSY isn't
1483 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1484 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1485 *
1486 * Wait for two seconds. Devices attached to downstream port
1487 * which can't process the following IDENTIFY after this will
1488 * have to be reset again. For most cases, this should
1489 * suffice while making probing snappish enough.
1490 */
1491 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1492 if (rc)
1493 ahci_kick_engine(ap, 0);
1494
1495 return 0;
1496}
1497
Tejun Heocc0680a2007-08-06 18:36:23 +09001498static void ahci_postreset(struct ata_link *link, unsigned int *class)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001499{
Tejun Heocc0680a2007-08-06 18:36:23 +09001500 struct ata_port *ap = link->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001501 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001502 u32 new_tmp, tmp;
1503
Tejun Heocc0680a2007-08-06 18:36:23 +09001504 ata_std_postreset(link, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001505
1506 /* Make sure port's ATAPI bit is set appropriately */
1507 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001508 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001509 new_tmp |= PORT_CMD_ATAPI;
1510 else
1511 new_tmp &= ~PORT_CMD_ATAPI;
1512 if (new_tmp != tmp) {
1513 writel(new_tmp, port_mmio + PORT_CMD);
1514 readl(port_mmio + PORT_CMD); /* flush */
1515 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001516}
1517
Tejun Heo7d50b602007-09-23 13:19:54 +09001518static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1519 unsigned long deadline)
1520{
1521 return ahci_do_softreset(link, class, link->pmp, deadline);
1522}
1523
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524static u8 ahci_check_status(struct ata_port *ap)
1525{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001526 void __iomem *mmio = ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527
1528 return readl(mmio + PORT_TFDATA) & 0xFF;
1529}
1530
Linus Torvalds1da177e2005-04-16 15:20:36 -07001531static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1532{
1533 struct ahci_port_priv *pp = ap->private_data;
1534 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1535
1536 ata_tf_from_fis(d2h_fis, tf);
1537}
1538
Tejun Heo12fad3f2006-05-15 21:03:55 +09001539static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001540{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001541 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001542 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1543 unsigned int si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544
1545 VPRINTK("ENTER\n");
1546
1547 /*
1548 * Next, the S/G list.
1549 */
Tejun Heoff2aeb12007-12-05 16:43:11 +09001550 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001551 dma_addr_t addr = sg_dma_address(sg);
1552 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553
Tejun Heoff2aeb12007-12-05 16:43:11 +09001554 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1555 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1556 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001558
Tejun Heoff2aeb12007-12-05 16:43:11 +09001559 return si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001560}
1561
1562static void ahci_qc_prep(struct ata_queued_cmd *qc)
1563{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001564 struct ata_port *ap = qc->ap;
1565 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo405e66b2007-11-27 19:28:53 +09001566 int is_atapi = ata_is_atapi(qc->tf.protocol);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001567 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001568 u32 opts;
1569 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001570 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571
1572 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001573 * Fill in command table information. First, the header,
1574 * a SATA Register - Host to Device command FIS.
1575 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001576 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1577
Tejun Heo7d50b602007-09-23 13:19:54 +09001578 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09001579 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001580 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1581 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04001582 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001583
Tejun Heocc9278e2006-02-10 17:25:47 +09001584 n_elem = 0;
1585 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001586 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001587
Tejun Heocc9278e2006-02-10 17:25:47 +09001588 /*
1589 * Fill in command slot information.
1590 */
Tejun Heo7d50b602007-09-23 13:19:54 +09001591 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
Tejun Heocc9278e2006-02-10 17:25:47 +09001592 if (qc->tf.flags & ATA_TFLAG_WRITE)
1593 opts |= AHCI_CMD_WRITE;
1594 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09001595 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001596
Tejun Heo12fad3f2006-05-15 21:03:55 +09001597 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598}
1599
Tejun Heo78cd52d2006-05-15 20:58:29 +09001600static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601{
Tejun Heo417a1a62007-09-23 13:19:55 +09001602 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001603 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001604 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1605 struct ata_link *link = NULL;
1606 struct ata_queued_cmd *active_qc;
1607 struct ata_eh_info *active_ehi;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001608 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001609
Tejun Heo7d50b602007-09-23 13:19:54 +09001610 /* determine active link */
1611 ata_port_for_each_link(link, ap)
1612 if (ata_link_active(link))
1613 break;
1614 if (!link)
1615 link = &ap->link;
1616
1617 active_qc = ata_qc_from_tag(ap, link->active_tag);
1618 active_ehi = &link->eh_info;
1619
1620 /* record irq stat */
1621 ata_ehi_clear_desc(host_ehi);
1622 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
Jeff Garzik9f68a242005-11-15 14:03:47 -05001623
Tejun Heo78cd52d2006-05-15 20:58:29 +09001624 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001625 ahci_scr_read(ap, SCR_ERROR, &serror);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001626 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heo7d50b602007-09-23 13:19:54 +09001627 host_ehi->serror |= serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001628
Tejun Heo41669552006-11-29 11:33:14 +09001629 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
Tejun Heo417a1a62007-09-23 13:19:55 +09001630 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
Tejun Heo41669552006-11-29 11:33:14 +09001631 irq_stat &= ~PORT_IRQ_IF_ERR;
1632
Conke Hu55a61602007-03-27 18:33:05 +08001633 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo7d50b602007-09-23 13:19:54 +09001634 /* If qc is active, charge it; otherwise, the active
1635 * link. There's no active qc on NCQ errors. It will
1636 * be determined by EH by reading log page 10h.
1637 */
1638 if (active_qc)
1639 active_qc->err_mask |= AC_ERR_DEV;
1640 else
1641 active_ehi->err_mask |= AC_ERR_DEV;
1642
Tejun Heo417a1a62007-09-23 13:19:55 +09001643 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
Tejun Heo7d50b602007-09-23 13:19:54 +09001644 host_ehi->serror &= ~SERR_INTERNAL;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001645 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001646
Tejun Heo78cd52d2006-05-15 20:58:29 +09001647 if (irq_stat & PORT_IRQ_UNK_FIS) {
1648 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001649
Tejun Heo7d50b602007-09-23 13:19:54 +09001650 active_ehi->err_mask |= AC_ERR_HSM;
1651 active_ehi->action |= ATA_EH_SOFTRESET;
1652 ata_ehi_push_desc(active_ehi,
1653 "unknown FIS %08x %08x %08x %08x" ,
Tejun Heo78cd52d2006-05-15 20:58:29 +09001654 unk[0], unk[1], unk[2], unk[3]);
1655 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04001656
Tejun Heo7d50b602007-09-23 13:19:54 +09001657 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1658 active_ehi->err_mask |= AC_ERR_HSM;
1659 active_ehi->action |= ATA_EH_SOFTRESET;
1660 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1661 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09001662
Tejun Heo7d50b602007-09-23 13:19:54 +09001663 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1664 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1665 host_ehi->action |= ATA_EH_SOFTRESET;
1666 ata_ehi_push_desc(host_ehi, "host bus error");
1667 }
1668
1669 if (irq_stat & PORT_IRQ_IF_ERR) {
1670 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1671 host_ehi->action |= ATA_EH_SOFTRESET;
1672 ata_ehi_push_desc(host_ehi, "interface fatal error");
1673 }
1674
1675 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1676 ata_ehi_hotplugged(host_ehi);
1677 ata_ehi_push_desc(host_ehi, "%s",
1678 irq_stat & PORT_IRQ_CONNECT ?
1679 "connection status changed" : "PHY RDY changed");
1680 }
1681
1682 /* okay, let's hand over to EH */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683
Tejun Heo78cd52d2006-05-15 20:58:29 +09001684 if (irq_stat & PORT_IRQ_FREEZE)
1685 ata_port_freeze(ap);
1686 else
1687 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001688}
1689
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001690static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691{
Tejun Heo4447d352007-04-17 23:44:08 +09001692 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001693 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09001694 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo5f226c62007-10-09 15:02:23 +09001695 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heob06ce3e2007-10-09 15:06:48 +09001696 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001697 u32 status, qc_active;
Tejun Heo459ad682007-12-07 12:46:23 +09001698 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001699
1700 status = readl(port_mmio + PORT_IRQ_STAT);
1701 writel(status, port_mmio + PORT_IRQ_STAT);
1702
Tejun Heob06ce3e2007-10-09 15:06:48 +09001703 /* ignore BAD_PMP while resetting */
1704 if (unlikely(resetting))
1705 status &= ~PORT_IRQ_BAD_PMP;
1706
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04001707 /* If we are getting PhyRdy, this is
1708 * just a power state change, we should
1709 * clear out this, plus the PhyRdy/Comm
1710 * Wake bits from Serror
1711 */
1712 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1713 (status & PORT_IRQ_PHYRDY)) {
1714 status &= ~PORT_IRQ_PHYRDY;
1715 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1716 }
1717
Tejun Heo78cd52d2006-05-15 20:58:29 +09001718 if (unlikely(status & PORT_IRQ_ERROR)) {
1719 ahci_error_intr(ap, status);
1720 return;
1721 }
1722
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001723 if (status & PORT_IRQ_SDB_FIS) {
Tejun Heo5f226c62007-10-09 15:02:23 +09001724 /* If SNotification is available, leave notification
1725 * handling to sata_async_notification(). If not,
1726 * emulate it by snooping SDB FIS RX area.
1727 *
1728 * Snooping FIS RX area is probably cheaper than
1729 * poking SNotification but some constrollers which
1730 * implement SNotification, ICH9 for example, don't
1731 * store AN SDB FIS into receive area.
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001732 */
Tejun Heo5f226c62007-10-09 15:02:23 +09001733 if (hpriv->cap & HOST_CAP_SNTF)
Tejun Heo7d77b242007-09-23 13:14:13 +09001734 sata_async_notification(ap);
Tejun Heo5f226c62007-10-09 15:02:23 +09001735 else {
1736 /* If the 'N' bit in word 0 of the FIS is set,
1737 * we just received asynchronous notification.
1738 * Tell libata about it.
1739 */
1740 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1741 u32 f0 = le32_to_cpu(f[0]);
1742
1743 if (f0 & (1 << 15))
1744 sata_async_notification(ap);
1745 }
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001746 }
1747
Tejun Heo7d50b602007-09-23 13:19:54 +09001748 /* pp->active_link is valid iff any command is in flight */
1749 if (ap->qc_active && pp->active_link->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001750 qc_active = readl(port_mmio + PORT_SCR_ACT);
1751 else
1752 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1753
1754 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
Tejun Heob06ce3e2007-10-09 15:06:48 +09001755
Tejun Heo459ad682007-12-07 12:46:23 +09001756 /* while resetting, invalid completions are expected */
1757 if (unlikely(rc < 0 && !resetting)) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001758 ehi->err_mask |= AC_ERR_HSM;
1759 ehi->action |= ATA_EH_SOFTRESET;
1760 ata_port_freeze(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001761 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001762}
1763
1764static void ahci_irq_clear(struct ata_port *ap)
1765{
1766 /* TODO */
1767}
1768
David Howells7d12e782006-10-05 14:55:46 +01001769static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770{
Jeff Garzikcca39742006-08-24 03:19:22 -04001771 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001772 struct ahci_host_priv *hpriv;
1773 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04001774 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001775 u32 irq_stat, irq_ack = 0;
1776
1777 VPRINTK("ENTER\n");
1778
Jeff Garzikcca39742006-08-24 03:19:22 -04001779 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001780 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001781
1782 /* sigh. 0xffffffff is a valid return from h/w */
1783 irq_stat = readl(mmio + HOST_IRQ_STAT);
1784 irq_stat &= hpriv->port_map;
1785 if (!irq_stat)
1786 return IRQ_NONE;
1787
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001788 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001789
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001790 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001791 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001792
Jeff Garzik67846b32005-10-05 02:58:32 -04001793 if (!(irq_stat & (1 << i)))
1794 continue;
1795
Jeff Garzikcca39742006-08-24 03:19:22 -04001796 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04001797 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001798 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04001799 VPRINTK("port %u\n", i);
1800 } else {
1801 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09001802 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04001803 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05001804 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001805 }
Jeff Garzik67846b32005-10-05 02:58:32 -04001806
1807 irq_ack |= (1 << i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001808 }
1809
1810 if (irq_ack) {
1811 writel(irq_ack, mmio + HOST_IRQ_STAT);
1812 handled = 1;
1813 }
1814
Jeff Garzikcca39742006-08-24 03:19:22 -04001815 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001816
1817 VPRINTK("EXIT\n");
1818
1819 return IRQ_RETVAL(handled);
1820}
1821
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09001822static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001823{
1824 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001825 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09001826 struct ahci_port_priv *pp = ap->private_data;
1827
1828 /* Keep track of the currently active link. It will be used
1829 * in completion path to determine whether NCQ phase is in
1830 * progress.
1831 */
1832 pp->active_link = qc->dev->link;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001833
Tejun Heo12fad3f2006-05-15 21:03:55 +09001834 if (qc->tf.protocol == ATA_PROT_NCQ)
1835 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1836 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001837 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1838
1839 return 0;
1840}
1841
Tejun Heo78cd52d2006-05-15 20:58:29 +09001842static void ahci_freeze(struct ata_port *ap)
1843{
Tejun Heo4447d352007-04-17 23:44:08 +09001844 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001845
1846 /* turn IRQ off */
1847 writel(0, port_mmio + PORT_IRQ_MASK);
1848}
1849
1850static void ahci_thaw(struct ata_port *ap)
1851{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001852 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09001853 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001854 u32 tmp;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07001855 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001856
1857 /* clear IRQ */
1858 tmp = readl(port_mmio + PORT_IRQ_STAT);
1859 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09001860 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001861
Tejun Heo1c954a42007-10-09 15:01:37 +09001862 /* turn IRQ back on */
1863 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001864}
1865
1866static void ahci_error_handler(struct ata_port *ap)
1867{
Tejun Heob51e9e52006-06-29 01:29:30 +09001868 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09001869 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001870 ahci_stop_engine(ap);
1871 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001872 }
1873
1874 /* perform recovery */
Tejun Heo7d50b602007-09-23 13:19:54 +09001875 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1876 ahci_hardreset, ahci_postreset,
1877 sata_pmp_std_prereset, ahci_pmp_softreset,
1878 sata_pmp_std_hardreset, sata_pmp_std_postreset);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001879}
1880
Tejun Heoad616ff2006-11-01 18:00:24 +09001881static void ahci_vt8251_error_handler(struct ata_port *ap)
1882{
Tejun Heoad616ff2006-11-01 18:00:24 +09001883 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1884 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001885 ahci_stop_engine(ap);
1886 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001887 }
1888
1889 /* perform recovery */
1890 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1891 ahci_postreset);
1892}
1893
Tejun Heoedc93052007-10-25 14:59:16 +09001894static void ahci_p5wdh_error_handler(struct ata_port *ap)
1895{
1896 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1897 /* restart engine */
1898 ahci_stop_engine(ap);
1899 ahci_start_engine(ap);
1900 }
1901
1902 /* perform recovery */
1903 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1904 ahci_postreset);
1905}
1906
Tejun Heo78cd52d2006-05-15 20:58:29 +09001907static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1908{
1909 struct ata_port *ap = qc->ap;
1910
Tejun Heod2e75df2007-07-16 14:29:39 +09001911 /* make DMA engine forget about the failed command */
1912 if (qc->flags & ATA_QCFLAG_FAILED)
1913 ahci_kick_engine(ap, 1);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001914}
1915
Tejun Heo7d50b602007-09-23 13:19:54 +09001916static void ahci_pmp_attach(struct ata_port *ap)
1917{
1918 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09001919 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001920 u32 cmd;
1921
1922 cmd = readl(port_mmio + PORT_CMD);
1923 cmd |= PORT_CMD_PMP;
1924 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09001925
1926 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1927 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09001928}
1929
1930static void ahci_pmp_detach(struct ata_port *ap)
1931{
1932 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09001933 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001934 u32 cmd;
1935
1936 cmd = readl(port_mmio + PORT_CMD);
1937 cmd &= ~PORT_CMD_PMP;
1938 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09001939
1940 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1941 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09001942}
1943
Alexey Dobriyan028a2592007-07-17 23:48:48 +04001944static int ahci_port_resume(struct ata_port *ap)
1945{
1946 ahci_power_up(ap);
1947 ahci_start_port(ap);
1948
Tejun Heo7d50b602007-09-23 13:19:54 +09001949 if (ap->nr_pmp_links)
1950 ahci_pmp_attach(ap);
1951 else
1952 ahci_pmp_detach(ap);
1953
Alexey Dobriyan028a2592007-07-17 23:48:48 +04001954 return 0;
1955}
1956
Tejun Heo438ac6d2007-03-02 17:31:26 +09001957#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09001958static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1959{
Tejun Heoc1332872006-07-26 15:59:26 +09001960 const char *emsg = NULL;
1961 int rc;
1962
Tejun Heo4447d352007-04-17 23:44:08 +09001963 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09001964 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09001965 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09001966 else {
Tejun Heoc1332872006-07-26 15:59:26 +09001967 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001968 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09001969 }
1970
1971 return rc;
1972}
1973
Tejun Heoc1332872006-07-26 15:59:26 +09001974static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1975{
Jeff Garzikcca39742006-08-24 03:19:22 -04001976 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001977 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09001978 u32 ctl;
1979
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01001980 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +09001981 /* AHCI spec rev1.1 section 8.3.3:
1982 * Software must disable interrupts prior to requesting a
1983 * transition of the HBA to D3 state.
1984 */
1985 ctl = readl(mmio + HOST_CTL);
1986 ctl &= ~HOST_IRQ_EN;
1987 writel(ctl, mmio + HOST_CTL);
1988 readl(mmio + HOST_CTL); /* flush */
1989 }
1990
1991 return ata_pci_device_suspend(pdev, mesg);
1992}
1993
1994static int ahci_pci_device_resume(struct pci_dev *pdev)
1995{
Jeff Garzikcca39742006-08-24 03:19:22 -04001996 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09001997 int rc;
1998
Tejun Heo553c4aa2006-12-26 19:39:50 +09001999 rc = ata_pci_device_do_resume(pdev);
2000 if (rc)
2001 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09002002
2003 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09002004 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002005 if (rc)
2006 return rc;
2007
Tejun Heo4447d352007-04-17 23:44:08 +09002008 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002009 }
2010
Jeff Garzikcca39742006-08-24 03:19:22 -04002011 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002012
2013 return 0;
2014}
Tejun Heo438ac6d2007-03-02 17:31:26 +09002015#endif
Tejun Heoc1332872006-07-26 15:59:26 +09002016
Tejun Heo254950c2006-07-26 15:59:25 +09002017static int ahci_port_start(struct ata_port *ap)
2018{
Jeff Garzikcca39742006-08-24 03:19:22 -04002019 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09002020 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09002021 void *mem;
2022 dma_addr_t mem_dma;
Tejun Heo254950c2006-07-26 15:59:25 +09002023
Tejun Heo24dc5f32007-01-20 16:00:28 +09002024 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09002025 if (!pp)
2026 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002027
Tejun Heo24dc5f32007-01-20 16:00:28 +09002028 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2029 GFP_KERNEL);
2030 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09002031 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002032 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2033
2034 /*
2035 * First item in chunk of DMA memory: 32-slot command table,
2036 * 32 bytes each in size
2037 */
2038 pp->cmd_slot = mem;
2039 pp->cmd_slot_dma = mem_dma;
2040
2041 mem += AHCI_CMD_SLOT_SZ;
2042 mem_dma += AHCI_CMD_SLOT_SZ;
2043
2044 /*
2045 * Second item: Received-FIS area
2046 */
2047 pp->rx_fis = mem;
2048 pp->rx_fis_dma = mem_dma;
2049
2050 mem += AHCI_RX_FIS_SZ;
2051 mem_dma += AHCI_RX_FIS_SZ;
2052
2053 /*
2054 * Third item: data area for storing a single command
2055 * and its scatter-gather table
2056 */
2057 pp->cmd_tbl = mem;
2058 pp->cmd_tbl_dma = mem_dma;
2059
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002060 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002061 * Save off initial list of interrupts to be enabled.
2062 * This could be changed later
2063 */
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002064 pp->intr_mask = DEF_PORT_IRQ;
2065
Tejun Heo254950c2006-07-26 15:59:25 +09002066 ap->private_data = pp;
2067
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002068 /* engage engines, captain */
2069 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09002070}
2071
2072static void ahci_port_stop(struct ata_port *ap)
2073{
Tejun Heo0be0aa92006-07-26 15:59:26 +09002074 const char *emsg = NULL;
2075 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09002076
Tejun Heo0be0aa92006-07-26 15:59:26 +09002077 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09002078 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09002079 if (rc)
2080 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09002081}
2082
Tejun Heo4447d352007-04-17 23:44:08 +09002083static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002084{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002085 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002086
Linus Torvalds1da177e2005-04-16 15:20:36 -07002087 if (using_dac &&
2088 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2089 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2090 if (rc) {
2091 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2092 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002093 dev_printk(KERN_ERR, &pdev->dev,
2094 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002095 return rc;
2096 }
2097 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002098 } else {
2099 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2100 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002101 dev_printk(KERN_ERR, &pdev->dev,
2102 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002103 return rc;
2104 }
2105 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2106 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002107 dev_printk(KERN_ERR, &pdev->dev,
2108 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002109 return rc;
2110 }
2111 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002112 return 0;
2113}
2114
Tejun Heo4447d352007-04-17 23:44:08 +09002115static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002116{
Tejun Heo4447d352007-04-17 23:44:08 +09002117 struct ahci_host_priv *hpriv = host->private_data;
2118 struct pci_dev *pdev = to_pci_dev(host->dev);
2119 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002120 u32 vers, cap, impl, speed;
2121 const char *speed_s;
2122 u16 cc;
2123 const char *scc_s;
2124
2125 vers = readl(mmio + HOST_VERSION);
2126 cap = hpriv->cap;
2127 impl = hpriv->port_map;
2128
2129 speed = (cap >> 20) & 0xf;
2130 if (speed == 1)
2131 speed_s = "1.5";
2132 else if (speed == 2)
2133 speed_s = "3";
2134 else
2135 speed_s = "?";
2136
2137 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05002138 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002139 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05002140 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002141 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05002142 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002143 scc_s = "RAID";
2144 else
2145 scc_s = "unknown";
2146
Jeff Garzika9524a72005-10-30 14:39:11 -05002147 dev_printk(KERN_INFO, &pdev->dev,
2148 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07002149 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002150 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002151
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002152 (vers >> 24) & 0xff,
2153 (vers >> 16) & 0xff,
2154 (vers >> 8) & 0xff,
2155 vers & 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002156
2157 ((cap >> 8) & 0x1f) + 1,
2158 (cap & 0x1f) + 1,
2159 speed_s,
2160 impl,
2161 scc_s);
2162
Jeff Garzika9524a72005-10-30 14:39:11 -05002163 dev_printk(KERN_INFO, &pdev->dev,
2164 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09002165 "%s%s%s%s%s%s%s"
2166 "%s%s%s%s%s%s%s\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002167 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002168
2169 cap & (1 << 31) ? "64bit " : "",
2170 cap & (1 << 30) ? "ncq " : "",
Tejun Heo203ef6c2007-07-16 14:29:40 +09002171 cap & (1 << 29) ? "sntf " : "",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002172 cap & (1 << 28) ? "ilck " : "",
2173 cap & (1 << 27) ? "stag " : "",
2174 cap & (1 << 26) ? "pm " : "",
2175 cap & (1 << 25) ? "led " : "",
2176
2177 cap & (1 << 24) ? "clo " : "",
2178 cap & (1 << 19) ? "nz " : "",
2179 cap & (1 << 18) ? "only " : "",
2180 cap & (1 << 17) ? "pmp " : "",
2181 cap & (1 << 15) ? "pio " : "",
2182 cap & (1 << 14) ? "slum " : "",
2183 cap & (1 << 13) ? "part " : ""
2184 );
2185}
2186
Tejun Heoedc93052007-10-25 14:59:16 +09002187/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2188 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2189 * support PMP and the 4726 either directly exports the device
2190 * attached to the first downstream port or acts as a hardware storage
2191 * controller and emulate a single ATA device (can be RAID 0/1 or some
2192 * other configuration).
2193 *
2194 * When there's no device attached to the first downstream port of the
2195 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2196 * configure the 4726. However, ATA emulation of the device is very
2197 * lame. It doesn't send signature D2H Reg FIS after the initial
2198 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2199 *
2200 * The following function works around the problem by always using
2201 * hardreset on the port and not depending on receiving signature FIS
2202 * afterward. If signature FIS isn't received soon, ATA class is
2203 * assumed without follow-up softreset.
2204 */
2205static void ahci_p5wdh_workaround(struct ata_host *host)
2206{
2207 static struct dmi_system_id sysids[] = {
2208 {
2209 .ident = "P5W DH Deluxe",
2210 .matches = {
2211 DMI_MATCH(DMI_SYS_VENDOR,
2212 "ASUSTEK COMPUTER INC"),
2213 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2214 },
2215 },
2216 { }
2217 };
2218 struct pci_dev *pdev = to_pci_dev(host->dev);
2219
2220 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2221 dmi_check_system(sysids)) {
2222 struct ata_port *ap = host->ports[1];
2223
2224 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2225 "Deluxe on-board SIMG4726 workaround\n");
2226
2227 ap->ops = &ahci_p5wdh_ops;
2228 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2229 }
2230}
2231
Tejun Heo24dc5f32007-01-20 16:00:28 +09002232static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002233{
2234 static int printed_version;
Tejun Heo4447d352007-04-17 23:44:08 +09002235 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2236 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09002237 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002238 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09002239 struct ata_host *host;
Tejun Heo837f5f82008-02-06 15:13:51 +09002240 int n_ports, i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002241
2242 VPRINTK("ENTER\n");
2243
Tejun Heo12fad3f2006-05-15 21:03:55 +09002244 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2245
Linus Torvalds1da177e2005-04-16 15:20:36 -07002246 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05002247 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002248
Tejun Heo4447d352007-04-17 23:44:08 +09002249 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09002250 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002251 if (rc)
2252 return rc;
2253
Tejun Heodea55132008-03-11 19:52:31 +09002254 /* AHCI controllers often implement SFF compatible interface.
2255 * Grab all PCI BARs just in case.
2256 */
2257 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002258 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002259 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002260 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002261 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002262
Tejun Heoc4f77922007-12-06 15:09:43 +09002263 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2264 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2265 u8 map;
2266
2267 /* ICH6s share the same PCI ID for both piix and ahci
2268 * modes. Enabling ahci mode while MAP indicates
2269 * combined mode is a bad idea. Yield to ata_piix.
2270 */
2271 pci_read_config_byte(pdev, ICH_MAP, &map);
2272 if (map & 0x3) {
2273 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2274 "combined mode, can't enable AHCI mode\n");
2275 return -ENODEV;
2276 }
2277 }
2278
Tejun Heo24dc5f32007-01-20 16:00:28 +09002279 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2280 if (!hpriv)
2281 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09002282 hpriv->flags |= (unsigned long)pi.private_data;
2283
2284 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2285 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002286
Tejun Heo4447d352007-04-17 23:44:08 +09002287 /* save initial config */
Tejun Heo417a1a62007-09-23 13:19:55 +09002288 ahci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002289
Tejun Heo4447d352007-04-17 23:44:08 +09002290 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09002291 if (hpriv->cap & HOST_CAP_NCQ)
Tejun Heo4447d352007-04-17 23:44:08 +09002292 pi.flags |= ATA_FLAG_NCQ;
2293
Tejun Heo7d50b602007-09-23 13:19:54 +09002294 if (hpriv->cap & HOST_CAP_PMP)
2295 pi.flags |= ATA_FLAG_PMP;
2296
Tejun Heo837f5f82008-02-06 15:13:51 +09002297 /* CAP.NP sometimes indicate the index of the last enabled
2298 * port, at other times, that of the last possible port, so
2299 * determining the maximum port number requires looking at
2300 * both CAP.NP and port_map.
2301 */
2302 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2303
2304 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09002305 if (!host)
2306 return -ENOMEM;
2307 host->iomap = pcim_iomap_table(pdev);
2308 host->private_data = hpriv;
2309
2310 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04002311 struct ata_port *ap = host->ports[i];
2312 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09002313
Tejun Heocbcdd872007-08-18 13:14:55 +09002314 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2315 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2316 0x100 + ap->port_no * 0x80, "port");
2317
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002318 /* set initial link pm policy */
2319 ap->pm_policy = NOT_AVAILABLE;
2320
Jeff Garzikdab632e2007-05-28 08:33:01 -04002321 /* standard SATA port setup */
Tejun Heo203ef6c2007-07-16 14:29:40 +09002322 if (hpriv->port_map & (1 << i))
Tejun Heo4447d352007-04-17 23:44:08 +09002323 ap->ioaddr.cmd_addr = port_mmio;
Jeff Garzikdab632e2007-05-28 08:33:01 -04002324
2325 /* disabled/not-implemented port */
2326 else
2327 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09002328 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002329
Tejun Heoedc93052007-10-25 14:59:16 +09002330 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2331 ahci_p5wdh_workaround(host);
2332
Linus Torvalds1da177e2005-04-16 15:20:36 -07002333 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09002334 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002335 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002336 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002337
Tejun Heo4447d352007-04-17 23:44:08 +09002338 rc = ahci_reset_controller(host);
2339 if (rc)
2340 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002341
Tejun Heo4447d352007-04-17 23:44:08 +09002342 ahci_init_controller(host);
2343 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002344
Tejun Heo4447d352007-04-17 23:44:08 +09002345 pci_set_master(pdev);
2346 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2347 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04002348}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002349
2350static int __init ahci_init(void)
2351{
Pavel Roskinb7887192006-08-10 18:13:18 +09002352 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002353}
2354
Linus Torvalds1da177e2005-04-16 15:20:36 -07002355static void __exit ahci_exit(void)
2356{
2357 pci_unregister_driver(&ahci_pci_driver);
2358}
2359
2360
2361MODULE_AUTHOR("Jeff Garzik");
2362MODULE_DESCRIPTION("AHCI SATA low-level driver");
2363MODULE_LICENSE("GPL");
2364MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04002365MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002366
2367module_init(ahci_init);
2368module_exit(ahci_exit);