Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ahci.c - AHCI SATA support |
| 3 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 8 | * Copyright 2004-2005 Red Hat, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2, or (at your option) |
| 14 | * any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; see the file COPYING. If not, write to |
| 23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | * |
| 25 | * |
| 26 | * libata documentation is available via 'make {ps|pdf}docs', |
| 27 | * as Documentation/DocBook/libata.* |
| 28 | * |
| 29 | * AHCI hardware documentation: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/blkdev.h> |
| 40 | #include <linux/delay.h> |
| 41 | #include <linux/interrupt.h> |
domen@coderock.org | 87507cf | 2005-04-08 09:53:06 +0200 | [diff] [blame] | 42 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 43 | #include <linux/device.h> |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 44 | #include <linux/dmi.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 46 | #include <scsi/scsi_cmnd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | #include <linux/libata.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | |
| 49 | #define DRV_NAME "ahci" |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 50 | #define DRV_VERSION "3.0" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame^] | 52 | static int ahci_skip_host_reset; |
| 53 | module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); |
| 54 | MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); |
| 55 | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 56 | static int ahci_enable_alpm(struct ata_port *ap, |
| 57 | enum link_pm policy); |
| 58 | static void ahci_disable_alpm(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | |
| 60 | enum { |
| 61 | AHCI_PCI_BAR = 5, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 62 | AHCI_MAX_PORTS = 32, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
| 64 | AHCI_DMA_BOUNDARY = 0xffffffff, |
Jens Axboe | be5d821 | 2007-05-22 09:45:39 +0200 | [diff] [blame] | 65 | AHCI_USE_CLUSTERING = 1, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 66 | AHCI_MAX_CMDS = 32, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 67 | AHCI_CMD_SZ = 32, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 68 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | AHCI_RX_FIS_SZ = 256, |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 70 | AHCI_CMD_TBL_CDB = 0x40, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 71 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
| 72 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), |
| 73 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, |
| 74 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | AHCI_RX_FIS_SZ, |
| 76 | AHCI_IRQ_ON_SG = (1 << 31), |
| 77 | AHCI_CMD_ATAPI = (1 << 5), |
| 78 | AHCI_CMD_WRITE = (1 << 6), |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 79 | AHCI_CMD_PREFETCH = (1 << 7), |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 80 | AHCI_CMD_RESET = (1 << 8), |
| 81 | AHCI_CMD_CLR_BUSY = (1 << 10), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | |
| 83 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 84 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 85 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | |
| 87 | board_ahci = 0, |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 88 | board_ahci_vt8251 = 1, |
| 89 | board_ahci_ign_iferr = 2, |
| 90 | board_ahci_sb600 = 3, |
| 91 | board_ahci_mv = 4, |
Shane Huang | e39fc8c | 2008-02-22 05:00:31 -0800 | [diff] [blame] | 92 | board_ahci_sb700 = 5, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 93 | |
| 94 | /* global controller registers */ |
| 95 | HOST_CAP = 0x00, /* host capabilities */ |
| 96 | HOST_CTL = 0x04, /* global host control */ |
| 97 | HOST_IRQ_STAT = 0x08, /* interrupt status */ |
| 98 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
| 99 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
| 100 | |
| 101 | /* HOST_CTL bits */ |
| 102 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ |
| 103 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ |
| 104 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ |
| 105 | |
| 106 | /* HOST_CAP bits */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 107 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 108 | HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 109 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 110 | HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 111 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 112 | HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
Tejun Heo | 979db80 | 2006-05-15 21:03:52 +0900 | [diff] [blame] | 113 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 114 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | |
| 116 | /* registers for each SATA port */ |
| 117 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
| 118 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
| 119 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
| 120 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
| 121 | PORT_IRQ_STAT = 0x10, /* interrupt status */ |
| 122 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
| 123 | PORT_CMD = 0x18, /* port command */ |
| 124 | PORT_TFDATA = 0x20, /* taskfile data */ |
| 125 | PORT_SIG = 0x24, /* device TF signature */ |
| 126 | PORT_CMD_ISSUE = 0x38, /* command issue */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
| 128 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
| 129 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
| 130 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 131 | PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | |
| 133 | /* PORT_IRQ_{STAT,MASK} bits */ |
| 134 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ |
| 135 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ |
| 136 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ |
| 137 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ |
| 138 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ |
| 139 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ |
| 140 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ |
| 141 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ |
| 142 | |
| 143 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ |
| 144 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ |
| 145 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ |
| 146 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ |
| 147 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ |
| 148 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ |
| 149 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ |
| 150 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ |
| 151 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ |
| 152 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 153 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
| 154 | PORT_IRQ_IF_ERR | |
| 155 | PORT_IRQ_CONNECT | |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 156 | PORT_IRQ_PHYRDY | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 157 | PORT_IRQ_UNK_FIS | |
| 158 | PORT_IRQ_BAD_PMP, |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 159 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
| 160 | PORT_IRQ_TF_ERR | |
| 161 | PORT_IRQ_HBUS_DATA_ERR, |
| 162 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | |
| 163 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | |
| 164 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 165 | |
| 166 | /* PORT_CMD bits */ |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 167 | PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
| 168 | PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 169 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 170 | PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
| 172 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
| 173 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 174 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
| 176 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ |
| 177 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ |
| 178 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 179 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
| 181 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ |
| 182 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 183 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 184 | /* hpriv->flags bits */ |
| 185 | AHCI_HFLAG_NO_NCQ = (1 << 0), |
| 186 | AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ |
| 187 | AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ |
| 188 | AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ |
| 189 | AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ |
| 190 | AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ |
Tejun Heo | 6949b91 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 191 | AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 192 | AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */ |
Jeff Garzik | a878539 | 2008-02-28 15:43:48 -0500 | [diff] [blame] | 193 | AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 194 | |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 195 | /* ap->flags bits */ |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 196 | |
| 197 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 198 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 199 | ATA_FLAG_ACPI_SATA | ATA_FLAG_AN | |
| 200 | ATA_FLAG_IPM, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 201 | AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY, |
Tejun Heo | c4f7792 | 2007-12-06 15:09:43 +0900 | [diff] [blame] | 202 | |
| 203 | ICH_MAP = 0x90, /* ICH MAP register */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | }; |
| 205 | |
| 206 | struct ahci_cmd_hdr { |
Al Viro | 4ca4e43 | 2007-12-30 09:32:22 +0000 | [diff] [blame] | 207 | __le32 opts; |
| 208 | __le32 status; |
| 209 | __le32 tbl_addr; |
| 210 | __le32 tbl_addr_hi; |
| 211 | __le32 reserved[4]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | }; |
| 213 | |
| 214 | struct ahci_sg { |
Al Viro | 4ca4e43 | 2007-12-30 09:32:22 +0000 | [diff] [blame] | 215 | __le32 addr; |
| 216 | __le32 addr_hi; |
| 217 | __le32 reserved; |
| 218 | __le32 flags_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | }; |
| 220 | |
| 221 | struct ahci_host_priv { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 222 | unsigned int flags; /* AHCI_HFLAG_* */ |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 223 | u32 cap; /* cap to use */ |
| 224 | u32 port_map; /* port map to use */ |
| 225 | u32 saved_cap; /* saved initial cap */ |
| 226 | u32 saved_port_map; /* saved initial port_map */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | }; |
| 228 | |
| 229 | struct ahci_port_priv { |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 230 | struct ata_link *active_link; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 231 | struct ahci_cmd_hdr *cmd_slot; |
| 232 | dma_addr_t cmd_slot_dma; |
| 233 | void *cmd_tbl; |
| 234 | dma_addr_t cmd_tbl_dma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | void *rx_fis; |
| 236 | dma_addr_t rx_fis_dma; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 237 | /* for NCQ spurious interrupt analysis */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 238 | unsigned int ncq_saw_d2h:1; |
| 239 | unsigned int ncq_saw_dmas:1; |
Tejun Heo | afb2d55 | 2007-02-27 13:24:19 +0900 | [diff] [blame] | 240 | unsigned int ncq_saw_sdb:1; |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 241 | u32 intr_mask; /* interrupts to enable */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | }; |
| 243 | |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 244 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
| 245 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 246 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 247 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | static void ahci_irq_clear(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 249 | static int ahci_port_start(struct ata_port *ap); |
| 250 | static void ahci_port_stop(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
| 252 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
| 253 | static u8 ahci_check_status(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 254 | static void ahci_freeze(struct ata_port *ap); |
| 255 | static void ahci_thaw(struct ata_port *ap); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 256 | static void ahci_pmp_attach(struct ata_port *ap); |
| 257 | static void ahci_pmp_detach(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 258 | static void ahci_error_handler(struct ata_port *ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 259 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 260 | static void ahci_p5wdh_error_handler(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 261 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 262 | static int ahci_port_resume(struct ata_port *ap); |
Jeff Garzik | a878539 | 2008-02-28 15:43:48 -0500 | [diff] [blame] | 263 | static void ahci_dev_config(struct ata_device *dev); |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 264 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
| 265 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 266 | u32 opts); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 267 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 268 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 269 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
| 270 | static int ahci_pci_device_resume(struct pci_dev *pdev); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 271 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 273 | static struct class_device_attribute *ahci_shost_attrs[] = { |
| 274 | &class_device_attr_link_power_management_policy, |
| 275 | NULL |
| 276 | }; |
| 277 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 278 | static struct scsi_host_template ahci_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | .module = THIS_MODULE, |
| 280 | .name = DRV_NAME, |
| 281 | .ioctl = ata_scsi_ioctl, |
| 282 | .queuecommand = ata_scsi_queuecmd, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 283 | .change_queue_depth = ata_scsi_change_queue_depth, |
| 284 | .can_queue = AHCI_MAX_CMDS - 1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 285 | .this_id = ATA_SHT_THIS_ID, |
| 286 | .sg_tablesize = AHCI_MAX_SG, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 288 | .emulated = ATA_SHT_EMULATED, |
| 289 | .use_clustering = AHCI_USE_CLUSTERING, |
| 290 | .proc_name = DRV_NAME, |
| 291 | .dma_boundary = AHCI_DMA_BOUNDARY, |
| 292 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 293 | .slave_destroy = ata_scsi_slave_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | .bios_param = ata_std_bios_param, |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 295 | .shost_attrs = ahci_shost_attrs, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | }; |
| 297 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 298 | static const struct ata_port_operations ahci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | .check_status = ahci_check_status, |
| 300 | .check_altstatus = ahci_check_status, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | .dev_select = ata_noop_dev_select, |
| 302 | |
Jeff Garzik | a878539 | 2008-02-28 15:43:48 -0500 | [diff] [blame] | 303 | .dev_config = ahci_dev_config, |
| 304 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | .tf_read = ahci_tf_read, |
| 306 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 307 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 308 | .qc_prep = ahci_qc_prep, |
| 309 | .qc_issue = ahci_qc_issue, |
| 310 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 311 | .irq_clear = ahci_irq_clear, |
| 312 | |
| 313 | .scr_read = ahci_scr_read, |
| 314 | .scr_write = ahci_scr_write, |
| 315 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 316 | .freeze = ahci_freeze, |
| 317 | .thaw = ahci_thaw, |
| 318 | |
| 319 | .error_handler = ahci_error_handler, |
| 320 | .post_internal_cmd = ahci_post_internal_cmd, |
| 321 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 322 | .pmp_attach = ahci_pmp_attach, |
| 323 | .pmp_detach = ahci_pmp_detach, |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 324 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 325 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 326 | .port_suspend = ahci_port_suspend, |
| 327 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 328 | #endif |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 329 | .enable_pm = ahci_enable_alpm, |
| 330 | .disable_pm = ahci_disable_alpm, |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 331 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | .port_start = ahci_port_start, |
| 333 | .port_stop = ahci_port_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | }; |
| 335 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 336 | static const struct ata_port_operations ahci_vt8251_ops = { |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 337 | .check_status = ahci_check_status, |
| 338 | .check_altstatus = ahci_check_status, |
| 339 | .dev_select = ata_noop_dev_select, |
| 340 | |
| 341 | .tf_read = ahci_tf_read, |
| 342 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 343 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 344 | .qc_prep = ahci_qc_prep, |
| 345 | .qc_issue = ahci_qc_issue, |
| 346 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 347 | .irq_clear = ahci_irq_clear, |
| 348 | |
| 349 | .scr_read = ahci_scr_read, |
| 350 | .scr_write = ahci_scr_write, |
| 351 | |
| 352 | .freeze = ahci_freeze, |
| 353 | .thaw = ahci_thaw, |
| 354 | |
| 355 | .error_handler = ahci_vt8251_error_handler, |
| 356 | .post_internal_cmd = ahci_post_internal_cmd, |
| 357 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 358 | .pmp_attach = ahci_pmp_attach, |
| 359 | .pmp_detach = ahci_pmp_detach, |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 360 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 361 | #ifdef CONFIG_PM |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 362 | .port_suspend = ahci_port_suspend, |
| 363 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 364 | #endif |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 365 | |
| 366 | .port_start = ahci_port_start, |
| 367 | .port_stop = ahci_port_stop, |
| 368 | }; |
| 369 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 370 | static const struct ata_port_operations ahci_p5wdh_ops = { |
| 371 | .check_status = ahci_check_status, |
| 372 | .check_altstatus = ahci_check_status, |
| 373 | .dev_select = ata_noop_dev_select, |
| 374 | |
| 375 | .tf_read = ahci_tf_read, |
| 376 | |
| 377 | .qc_defer = sata_pmp_qc_defer_cmd_switch, |
| 378 | .qc_prep = ahci_qc_prep, |
| 379 | .qc_issue = ahci_qc_issue, |
| 380 | |
| 381 | .irq_clear = ahci_irq_clear, |
| 382 | |
| 383 | .scr_read = ahci_scr_read, |
| 384 | .scr_write = ahci_scr_write, |
| 385 | |
| 386 | .freeze = ahci_freeze, |
| 387 | .thaw = ahci_thaw, |
| 388 | |
| 389 | .error_handler = ahci_p5wdh_error_handler, |
| 390 | .post_internal_cmd = ahci_post_internal_cmd, |
| 391 | |
| 392 | .pmp_attach = ahci_pmp_attach, |
| 393 | .pmp_detach = ahci_pmp_detach, |
| 394 | |
| 395 | #ifdef CONFIG_PM |
| 396 | .port_suspend = ahci_port_suspend, |
| 397 | .port_resume = ahci_port_resume, |
| 398 | #endif |
| 399 | |
| 400 | .port_start = ahci_port_start, |
| 401 | .port_stop = ahci_port_stop, |
| 402 | }; |
| 403 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 404 | #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
| 405 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 406 | static const struct ata_port_info ahci_port_info[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | /* board_ahci */ |
| 408 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 409 | .flags = AHCI_FLAG_COMMON, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 410 | .link_flags = AHCI_LFLAG_COMMON, |
Brett Russ | 7da7931 | 2005-09-01 21:53:34 -0400 | [diff] [blame] | 411 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 412 | .udma_mask = ATA_UDMA6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | .port_ops = &ahci_ops, |
| 414 | }, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 415 | /* board_ahci_vt8251 */ |
| 416 | { |
Tejun Heo | 6949b91 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 417 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 418 | .flags = AHCI_FLAG_COMMON, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 419 | .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 420 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 421 | .udma_mask = ATA_UDMA6, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 422 | .port_ops = &ahci_vt8251_ops, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 423 | }, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 424 | /* board_ahci_ign_iferr */ |
| 425 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 426 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
| 427 | .flags = AHCI_FLAG_COMMON, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 428 | .link_flags = AHCI_LFLAG_COMMON, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 429 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 430 | .udma_mask = ATA_UDMA6, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 431 | .port_ops = &ahci_ops, |
| 432 | }, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 433 | /* board_ahci_sb600 */ |
| 434 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 435 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
Jeff Garzik | a878539 | 2008-02-28 15:43:48 -0500 | [diff] [blame] | 436 | AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP), |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 437 | .flags = AHCI_FLAG_COMMON, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 438 | .link_flags = AHCI_LFLAG_COMMON, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 439 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame] | 440 | .udma_mask = ATA_UDMA6, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 441 | .port_ops = &ahci_ops, |
| 442 | }, |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 443 | /* board_ahci_mv */ |
| 444 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 445 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
| 446 | AHCI_HFLAG_MV_PATA), |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 447 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 448 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, |
Tejun Heo | 0c88758 | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 449 | .link_flags = AHCI_LFLAG_COMMON, |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 450 | .pio_mask = 0x1f, /* pio0-4 */ |
| 451 | .udma_mask = ATA_UDMA6, |
| 452 | .port_ops = &ahci_ops, |
| 453 | }, |
Shane Huang | e39fc8c | 2008-02-22 05:00:31 -0800 | [diff] [blame] | 454 | /* board_ahci_sb700 */ |
| 455 | { |
| 456 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
| 457 | AHCI_HFLAG_NO_PMP), |
| 458 | .flags = AHCI_FLAG_COMMON, |
| 459 | .link_flags = AHCI_LFLAG_COMMON, |
| 460 | .pio_mask = 0x1f, /* pio0-4 */ |
| 461 | .udma_mask = ATA_UDMA6, |
| 462 | .port_ops = &ahci_ops, |
| 463 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | }; |
| 465 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 466 | static const struct pci_device_id ahci_pci_tbl[] = { |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 467 | /* Intel */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 468 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
| 469 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ |
| 470 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ |
| 471 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ |
| 472 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ |
Tejun Heo | 82490c0 | 2007-01-23 15:13:39 +0900 | [diff] [blame] | 473 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 474 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
| 475 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ |
| 476 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ |
| 477 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 478 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
| 479 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */ |
| 480 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ |
| 481 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ |
| 482 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ |
| 483 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ |
| 484 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ |
| 485 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ |
| 486 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ |
| 487 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ |
| 488 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ |
| 489 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ |
| 490 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ |
| 491 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ |
| 492 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ |
| 493 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ |
| 494 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ |
Jason Gaston | d4155e6 | 2007-09-20 17:35:00 -0400 | [diff] [blame] | 495 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
| 496 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ |
Jason Gaston | 16ad1ad | 2008-01-28 17:34:14 -0800 | [diff] [blame] | 497 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
| 498 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 499 | |
Tejun Heo | e34bb37 | 2007-02-26 20:24:03 +0900 | [diff] [blame] | 500 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
| 501 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 502 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 503 | |
| 504 | /* ATI */ |
Conke Hu | c65ec1c | 2007-04-11 18:23:14 +0800 | [diff] [blame] | 505 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
Shane Huang | e39fc8c | 2008-02-22 05:00:31 -0800 | [diff] [blame] | 506 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
| 507 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ |
| 508 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ |
| 509 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ |
| 510 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ |
| 511 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 512 | |
| 513 | /* VIA */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 514 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
Tejun Heo | bf33554 | 2007-04-11 17:27:14 +0900 | [diff] [blame] | 515 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 516 | |
| 517 | /* NVIDIA */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 518 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
| 519 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ |
| 520 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ |
| 521 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ |
Peer Chen | 6fbf5ba | 2006-12-20 14:18:00 -0500 | [diff] [blame] | 522 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
| 523 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ |
| 524 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ |
| 525 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ |
| 526 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ |
| 527 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ |
| 528 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ |
| 529 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ |
Peer Chen | 895663c | 2006-11-02 17:59:46 -0500 | [diff] [blame] | 530 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
| 531 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ |
| 532 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ |
| 533 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ |
| 534 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ |
| 535 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ |
| 536 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ |
| 537 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ |
Peer Chen | 0522b28 | 2007-06-07 18:05:12 +0800 | [diff] [blame] | 538 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
| 539 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ |
| 540 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ |
| 541 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ |
| 542 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ |
| 543 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ |
| 544 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ |
| 545 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ |
| 546 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ |
| 547 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ |
| 548 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ |
| 549 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ |
| 550 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ |
| 551 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ |
| 552 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ |
| 553 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ |
| 554 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ |
| 555 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ |
| 556 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ |
| 557 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ |
| 558 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ |
| 559 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ |
| 560 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ |
| 561 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ |
peerchen | 6ba8695 | 2007-12-03 22:20:37 +0800 | [diff] [blame] | 562 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */ |
| 563 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */ |
| 564 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */ |
| 565 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */ |
Peer Chen | 7100819 | 2007-09-24 10:16:25 +0800 | [diff] [blame] | 566 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */ |
| 567 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */ |
| 568 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */ |
| 569 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */ |
| 570 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */ |
| 571 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ |
| 572 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ |
| 573 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ |
peerchen | 70d562c | 2008-03-06 21:22:41 +0800 | [diff] [blame] | 574 | { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */ |
| 575 | { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */ |
| 576 | { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */ |
| 577 | { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */ |
| 578 | { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */ |
| 579 | { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */ |
| 580 | { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */ |
| 581 | { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */ |
| 582 | { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */ |
| 583 | { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */ |
| 584 | { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */ |
| 585 | { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 586 | |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 587 | /* SiS */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 588 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
| 589 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ |
| 590 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 591 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 592 | /* Marvell */ |
| 593 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ |
| 594 | |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 595 | /* Generic, PCI class code for AHCI */ |
| 596 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 597 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 598 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | { } /* terminate list */ |
| 600 | }; |
| 601 | |
| 602 | |
| 603 | static struct pci_driver ahci_pci_driver = { |
| 604 | .name = DRV_NAME, |
| 605 | .id_table = ahci_pci_tbl, |
| 606 | .probe = ahci_init_one, |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 607 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 608 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 609 | .suspend = ahci_pci_device_suspend, |
| 610 | .resume = ahci_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 611 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 612 | }; |
| 613 | |
| 614 | |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 615 | static inline int ahci_nr_ports(u32 cap) |
| 616 | { |
| 617 | return (cap & 0x1f) + 1; |
| 618 | } |
| 619 | |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 620 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
| 621 | unsigned int port_no) |
| 622 | { |
| 623 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 624 | |
| 625 | return mmio + 0x100 + (port_no * 0x80); |
| 626 | } |
| 627 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 628 | static inline void __iomem *ahci_port_base(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 629 | { |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 630 | return __ahci_port_base(ap->host, ap->port_no); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 631 | } |
| 632 | |
Tejun Heo | b710a1f | 2008-01-05 23:11:57 +0900 | [diff] [blame] | 633 | static void ahci_enable_ahci(void __iomem *mmio) |
| 634 | { |
| 635 | u32 tmp; |
| 636 | |
| 637 | /* turn on AHCI_EN */ |
| 638 | tmp = readl(mmio + HOST_CTL); |
| 639 | if (!(tmp & HOST_AHCI_EN)) { |
| 640 | tmp |= HOST_AHCI_EN; |
| 641 | writel(tmp, mmio + HOST_CTL); |
| 642 | tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ |
| 643 | WARN_ON(!(tmp & HOST_AHCI_EN)); |
| 644 | } |
| 645 | } |
| 646 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 647 | /** |
| 648 | * ahci_save_initial_config - Save and fixup initial config values |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 649 | * @pdev: target PCI device |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 650 | * @hpriv: host private area to store config values |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 651 | * |
| 652 | * Some registers containing configuration info might be setup by |
| 653 | * BIOS and might be cleared on reset. This function saves the |
| 654 | * initial values of those registers into @hpriv such that they |
| 655 | * can be restored after controller reset. |
| 656 | * |
| 657 | * If inconsistent, config values are fixed up by this function. |
| 658 | * |
| 659 | * LOCKING: |
| 660 | * None. |
| 661 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 662 | static void ahci_save_initial_config(struct pci_dev *pdev, |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 663 | struct ahci_host_priv *hpriv) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 664 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 665 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 666 | u32 cap, port_map; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 667 | int i; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 668 | |
Tejun Heo | b710a1f | 2008-01-05 23:11:57 +0900 | [diff] [blame] | 669 | /* make sure AHCI mode is enabled before accessing CAP */ |
| 670 | ahci_enable_ahci(mmio); |
| 671 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 672 | /* Values prefixed with saved_ are written back to host after |
| 673 | * reset. Values without are used for driver operation. |
| 674 | */ |
| 675 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); |
| 676 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); |
| 677 | |
Tejun Heo | 274c1fd | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 678 | /* some chips have errata preventing 64bit use */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 679 | if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { |
Tejun Heo | c7a4215 | 2007-05-18 16:23:19 +0200 | [diff] [blame] | 680 | dev_printk(KERN_INFO, &pdev->dev, |
| 681 | "controller can't do 64bit DMA, forcing 32bit\n"); |
| 682 | cap &= ~HOST_CAP_64; |
| 683 | } |
| 684 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 685 | if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { |
Tejun Heo | 274c1fd | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 686 | dev_printk(KERN_INFO, &pdev->dev, |
| 687 | "controller can't do NCQ, turning off CAP_NCQ\n"); |
| 688 | cap &= ~HOST_CAP_NCQ; |
| 689 | } |
| 690 | |
Roel Kluin | 258cd84 | 2008-03-09 21:42:40 +0100 | [diff] [blame] | 691 | if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { |
Tejun Heo | 6949b91 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 692 | dev_printk(KERN_INFO, &pdev->dev, |
| 693 | "controller can't do PMP, turning off CAP_PMP\n"); |
| 694 | cap &= ~HOST_CAP_PMP; |
| 695 | } |
| 696 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 697 | /* |
| 698 | * Temporary Marvell 6145 hack: PATA port presence |
| 699 | * is asserted through the standard AHCI port |
| 700 | * presence register, as bit 4 (counting from 0) |
| 701 | */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 702 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 703 | dev_printk(KERN_ERR, &pdev->dev, |
| 704 | "MV_AHCI HACK: port_map %x -> %x\n", |
| 705 | hpriv->port_map, |
| 706 | hpriv->port_map & 0xf); |
| 707 | |
| 708 | port_map &= 0xf; |
| 709 | } |
| 710 | |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 711 | /* cross check port_map and cap.n_ports */ |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 712 | if (port_map) { |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 713 | int map_ports = 0; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 714 | |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 715 | for (i = 0; i < AHCI_MAX_PORTS; i++) |
| 716 | if (port_map & (1 << i)) |
| 717 | map_ports++; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 718 | |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 719 | /* If PI has more ports than n_ports, whine, clear |
| 720 | * port_map and let it be generated from n_ports. |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 721 | */ |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 722 | if (map_ports > ahci_nr_ports(cap)) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 723 | dev_printk(KERN_WARNING, &pdev->dev, |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 724 | "implemented port map (0x%x) contains more " |
| 725 | "ports than nr_ports (%u), using nr_ports\n", |
| 726 | port_map, ahci_nr_ports(cap)); |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 727 | port_map = 0; |
| 728 | } |
| 729 | } |
| 730 | |
| 731 | /* fabricate port_map from cap.nr_ports */ |
| 732 | if (!port_map) { |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 733 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
Tejun Heo | 7a234af | 2007-09-03 12:44:57 +0900 | [diff] [blame] | 734 | dev_printk(KERN_WARNING, &pdev->dev, |
| 735 | "forcing PORTS_IMPL to 0x%x\n", port_map); |
| 736 | |
| 737 | /* write the fixed up value to the PI register */ |
| 738 | hpriv->saved_port_map = port_map; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 739 | } |
| 740 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 741 | /* record values to use during operation */ |
| 742 | hpriv->cap = cap; |
| 743 | hpriv->port_map = port_map; |
| 744 | } |
| 745 | |
| 746 | /** |
| 747 | * ahci_restore_initial_config - Restore initial config |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 748 | * @host: target ATA host |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 749 | * |
| 750 | * Restore initial config stored by ahci_save_initial_config(). |
| 751 | * |
| 752 | * LOCKING: |
| 753 | * None. |
| 754 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 755 | static void ahci_restore_initial_config(struct ata_host *host) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 756 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 757 | struct ahci_host_priv *hpriv = host->private_data; |
| 758 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 759 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 760 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
| 761 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); |
| 762 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ |
| 763 | } |
| 764 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 765 | static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 766 | { |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 767 | static const int offset[] = { |
| 768 | [SCR_STATUS] = PORT_SCR_STAT, |
| 769 | [SCR_CONTROL] = PORT_SCR_CTL, |
| 770 | [SCR_ERROR] = PORT_SCR_ERR, |
| 771 | [SCR_ACTIVE] = PORT_SCR_ACT, |
| 772 | [SCR_NOTIFICATION] = PORT_SCR_NTF, |
| 773 | }; |
| 774 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 776 | if (sc_reg < ARRAY_SIZE(offset) && |
| 777 | (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) |
| 778 | return offset[sc_reg]; |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 779 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 780 | } |
| 781 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 782 | static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 783 | { |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 784 | void __iomem *port_mmio = ahci_port_base(ap); |
| 785 | int offset = ahci_scr_offset(ap, sc_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 786 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 787 | if (offset) { |
| 788 | *val = readl(port_mmio + offset); |
| 789 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 790 | } |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 791 | return -EINVAL; |
| 792 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 793 | |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 794 | static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
| 795 | { |
| 796 | void __iomem *port_mmio = ahci_port_base(ap); |
| 797 | int offset = ahci_scr_offset(ap, sc_reg); |
| 798 | |
| 799 | if (offset) { |
| 800 | writel(val, port_mmio + offset); |
| 801 | return 0; |
| 802 | } |
| 803 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 804 | } |
| 805 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 806 | static void ahci_start_engine(struct ata_port *ap) |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 807 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 808 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 809 | u32 tmp; |
| 810 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 811 | /* start DMA */ |
Tejun Heo | 9f59205 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 812 | tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 813 | tmp |= PORT_CMD_START; |
| 814 | writel(tmp, port_mmio + PORT_CMD); |
| 815 | readl(port_mmio + PORT_CMD); /* flush */ |
| 816 | } |
| 817 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 818 | static int ahci_stop_engine(struct ata_port *ap) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 819 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 820 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 821 | u32 tmp; |
| 822 | |
| 823 | tmp = readl(port_mmio + PORT_CMD); |
| 824 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 825 | /* check if the HBA is idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 826 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
| 827 | return 0; |
| 828 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 829 | /* setting HBA to idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 830 | tmp &= ~PORT_CMD_START; |
| 831 | writel(tmp, port_mmio + PORT_CMD); |
| 832 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 833 | /* wait for engine to stop. This could be as long as 500 msec */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 834 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 835 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 836 | if (tmp & PORT_CMD_LIST_ON) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 837 | return -EIO; |
| 838 | |
| 839 | return 0; |
| 840 | } |
| 841 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 842 | static void ahci_start_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 843 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 844 | void __iomem *port_mmio = ahci_port_base(ap); |
| 845 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 846 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 847 | u32 tmp; |
| 848 | |
| 849 | /* set FIS registers */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 850 | if (hpriv->cap & HOST_CAP_64) |
| 851 | writel((pp->cmd_slot_dma >> 16) >> 16, |
| 852 | port_mmio + PORT_LST_ADDR_HI); |
| 853 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 854 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 855 | if (hpriv->cap & HOST_CAP_64) |
| 856 | writel((pp->rx_fis_dma >> 16) >> 16, |
| 857 | port_mmio + PORT_FIS_ADDR_HI); |
| 858 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 859 | |
| 860 | /* enable FIS reception */ |
| 861 | tmp = readl(port_mmio + PORT_CMD); |
| 862 | tmp |= PORT_CMD_FIS_RX; |
| 863 | writel(tmp, port_mmio + PORT_CMD); |
| 864 | |
| 865 | /* flush */ |
| 866 | readl(port_mmio + PORT_CMD); |
| 867 | } |
| 868 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 869 | static int ahci_stop_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 870 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 871 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 872 | u32 tmp; |
| 873 | |
| 874 | /* disable FIS reception */ |
| 875 | tmp = readl(port_mmio + PORT_CMD); |
| 876 | tmp &= ~PORT_CMD_FIS_RX; |
| 877 | writel(tmp, port_mmio + PORT_CMD); |
| 878 | |
| 879 | /* wait for completion, spec says 500ms, give it 1000 */ |
| 880 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, |
| 881 | PORT_CMD_FIS_ON, 10, 1000); |
| 882 | if (tmp & PORT_CMD_FIS_ON) |
| 883 | return -EBUSY; |
| 884 | |
| 885 | return 0; |
| 886 | } |
| 887 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 888 | static void ahci_power_up(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 889 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 890 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 891 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 892 | u32 cmd; |
| 893 | |
| 894 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
| 895 | |
| 896 | /* spin up device */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 897 | if (hpriv->cap & HOST_CAP_SSS) { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 898 | cmd |= PORT_CMD_SPIN_UP; |
| 899 | writel(cmd, port_mmio + PORT_CMD); |
| 900 | } |
| 901 | |
| 902 | /* wake up link */ |
| 903 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); |
| 904 | } |
| 905 | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 906 | static void ahci_disable_alpm(struct ata_port *ap) |
| 907 | { |
| 908 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 909 | void __iomem *port_mmio = ahci_port_base(ap); |
| 910 | u32 cmd; |
| 911 | struct ahci_port_priv *pp = ap->private_data; |
| 912 | |
| 913 | /* IPM bits should be disabled by libata-core */ |
| 914 | /* get the existing command bits */ |
| 915 | cmd = readl(port_mmio + PORT_CMD); |
| 916 | |
| 917 | /* disable ALPM and ASP */ |
| 918 | cmd &= ~PORT_CMD_ASP; |
| 919 | cmd &= ~PORT_CMD_ALPE; |
| 920 | |
| 921 | /* force the interface back to active */ |
| 922 | cmd |= PORT_CMD_ICC_ACTIVE; |
| 923 | |
| 924 | /* write out new cmd value */ |
| 925 | writel(cmd, port_mmio + PORT_CMD); |
| 926 | cmd = readl(port_mmio + PORT_CMD); |
| 927 | |
| 928 | /* wait 10ms to be sure we've come out of any low power state */ |
| 929 | msleep(10); |
| 930 | |
| 931 | /* clear out any PhyRdy stuff from interrupt status */ |
| 932 | writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); |
| 933 | |
| 934 | /* go ahead and clean out PhyRdy Change from Serror too */ |
| 935 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); |
| 936 | |
| 937 | /* |
| 938 | * Clear flag to indicate that we should ignore all PhyRdy |
| 939 | * state changes |
| 940 | */ |
| 941 | hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; |
| 942 | |
| 943 | /* |
| 944 | * Enable interrupts on Phy Ready. |
| 945 | */ |
| 946 | pp->intr_mask |= PORT_IRQ_PHYRDY; |
| 947 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
| 948 | |
| 949 | /* |
| 950 | * don't change the link pm policy - we can be called |
| 951 | * just to turn of link pm temporarily |
| 952 | */ |
| 953 | } |
| 954 | |
| 955 | static int ahci_enable_alpm(struct ata_port *ap, |
| 956 | enum link_pm policy) |
| 957 | { |
| 958 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 959 | void __iomem *port_mmio = ahci_port_base(ap); |
| 960 | u32 cmd; |
| 961 | struct ahci_port_priv *pp = ap->private_data; |
| 962 | u32 asp; |
| 963 | |
| 964 | /* Make sure the host is capable of link power management */ |
| 965 | if (!(hpriv->cap & HOST_CAP_ALPM)) |
| 966 | return -EINVAL; |
| 967 | |
| 968 | switch (policy) { |
| 969 | case MAX_PERFORMANCE: |
| 970 | case NOT_AVAILABLE: |
| 971 | /* |
| 972 | * if we came here with NOT_AVAILABLE, |
| 973 | * it just means this is the first time we |
| 974 | * have tried to enable - default to max performance, |
| 975 | * and let the user go to lower power modes on request. |
| 976 | */ |
| 977 | ahci_disable_alpm(ap); |
| 978 | return 0; |
| 979 | case MIN_POWER: |
| 980 | /* configure HBA to enter SLUMBER */ |
| 981 | asp = PORT_CMD_ASP; |
| 982 | break; |
| 983 | case MEDIUM_POWER: |
| 984 | /* configure HBA to enter PARTIAL */ |
| 985 | asp = 0; |
| 986 | break; |
| 987 | default: |
| 988 | return -EINVAL; |
| 989 | } |
| 990 | |
| 991 | /* |
| 992 | * Disable interrupts on Phy Ready. This keeps us from |
| 993 | * getting woken up due to spurious phy ready interrupts |
| 994 | * TBD - Hot plug should be done via polling now, is |
| 995 | * that even supported? |
| 996 | */ |
| 997 | pp->intr_mask &= ~PORT_IRQ_PHYRDY; |
| 998 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
| 999 | |
| 1000 | /* |
| 1001 | * Set a flag to indicate that we should ignore all PhyRdy |
| 1002 | * state changes since these can happen now whenever we |
| 1003 | * change link state |
| 1004 | */ |
| 1005 | hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; |
| 1006 | |
| 1007 | /* get the existing command bits */ |
| 1008 | cmd = readl(port_mmio + PORT_CMD); |
| 1009 | |
| 1010 | /* |
| 1011 | * Set ASP based on Policy |
| 1012 | */ |
| 1013 | cmd |= asp; |
| 1014 | |
| 1015 | /* |
| 1016 | * Setting this bit will instruct the HBA to aggressively |
| 1017 | * enter a lower power link state when it's appropriate and |
| 1018 | * based on the value set above for ASP |
| 1019 | */ |
| 1020 | cmd |= PORT_CMD_ALPE; |
| 1021 | |
| 1022 | /* write out new cmd value */ |
| 1023 | writel(cmd, port_mmio + PORT_CMD); |
| 1024 | cmd = readl(port_mmio + PORT_CMD); |
| 1025 | |
| 1026 | /* IPM bits should be set by libata-core */ |
| 1027 | return 0; |
| 1028 | } |
| 1029 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1030 | #ifdef CONFIG_PM |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1031 | static void ahci_power_down(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1032 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1033 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 1034 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1035 | u32 cmd, scontrol; |
| 1036 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1037 | if (!(hpriv->cap & HOST_CAP_SSS)) |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 1038 | return; |
| 1039 | |
| 1040 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
| 1041 | scontrol = readl(port_mmio + PORT_SCR_CTL); |
| 1042 | scontrol &= ~0xf; |
| 1043 | writel(scontrol, port_mmio + PORT_SCR_CTL); |
| 1044 | |
| 1045 | /* then set PxCMD.SUD to 0 */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1046 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 1047 | cmd &= ~PORT_CMD_SPIN_UP; |
| 1048 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1049 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1050 | #endif |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1051 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1052 | static void ahci_start_port(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1053 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1054 | /* enable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1055 | ahci_start_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1056 | |
| 1057 | /* enable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1058 | ahci_start_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1059 | } |
| 1060 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1061 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1062 | { |
| 1063 | int rc; |
| 1064 | |
| 1065 | /* disable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1066 | rc = ahci_stop_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1067 | if (rc) { |
| 1068 | *emsg = "failed to stop engine"; |
| 1069 | return rc; |
| 1070 | } |
| 1071 | |
| 1072 | /* disable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1073 | rc = ahci_stop_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1074 | if (rc) { |
| 1075 | *emsg = "failed stop FIS RX"; |
| 1076 | return rc; |
| 1077 | } |
| 1078 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1079 | return 0; |
| 1080 | } |
| 1081 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1082 | static int ahci_reset_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1083 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1084 | struct pci_dev *pdev = to_pci_dev(host->dev); |
Tejun Heo | 49f2909 | 2007-11-19 16:03:44 +0900 | [diff] [blame] | 1085 | struct ahci_host_priv *hpriv = host->private_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1086 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 1087 | u32 tmp; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1088 | |
Jeff Garzik | 3cc3eb1 | 2007-09-26 00:02:41 -0400 | [diff] [blame] | 1089 | /* we must be in AHCI mode, before using anything |
| 1090 | * AHCI-specific, such as HOST_RESET. |
| 1091 | */ |
Tejun Heo | b710a1f | 2008-01-05 23:11:57 +0900 | [diff] [blame] | 1092 | ahci_enable_ahci(mmio); |
Jeff Garzik | 3cc3eb1 | 2007-09-26 00:02:41 -0400 | [diff] [blame] | 1093 | |
| 1094 | /* global controller reset */ |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame^] | 1095 | if (!ahci_skip_host_reset) { |
| 1096 | tmp = readl(mmio + HOST_CTL); |
| 1097 | if ((tmp & HOST_RESET) == 0) { |
| 1098 | writel(tmp | HOST_RESET, mmio + HOST_CTL); |
| 1099 | readl(mmio + HOST_CTL); /* flush */ |
| 1100 | } |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1101 | |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame^] | 1102 | /* reset must complete within 1 second, or |
| 1103 | * the hardware should be considered fried. |
| 1104 | */ |
| 1105 | ssleep(1); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1106 | |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame^] | 1107 | tmp = readl(mmio + HOST_CTL); |
| 1108 | if (tmp & HOST_RESET) { |
| 1109 | dev_printk(KERN_ERR, host->dev, |
| 1110 | "controller reset failed (0x%x)\n", tmp); |
| 1111 | return -EIO; |
| 1112 | } |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1113 | |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame^] | 1114 | /* turn on AHCI mode */ |
| 1115 | ahci_enable_ahci(mmio); |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 1116 | |
Tejun Heo | a22e644 | 2008-03-10 10:25:25 +0900 | [diff] [blame^] | 1117 | /* Some registers might be cleared on reset. Restore |
| 1118 | * initial values. |
| 1119 | */ |
| 1120 | ahci_restore_initial_config(host); |
| 1121 | } else |
| 1122 | dev_printk(KERN_INFO, host->dev, |
| 1123 | "skipping global host reset\n"); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1124 | |
| 1125 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
| 1126 | u16 tmp16; |
| 1127 | |
| 1128 | /* configure PCS */ |
| 1129 | pci_read_config_word(pdev, 0x92, &tmp16); |
Tejun Heo | 49f2909 | 2007-11-19 16:03:44 +0900 | [diff] [blame] | 1130 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { |
| 1131 | tmp16 |= hpriv->port_map; |
| 1132 | pci_write_config_word(pdev, 0x92, tmp16); |
| 1133 | } |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1134 | } |
| 1135 | |
| 1136 | return 0; |
| 1137 | } |
| 1138 | |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 1139 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
| 1140 | int port_no, void __iomem *mmio, |
| 1141 | void __iomem *port_mmio) |
| 1142 | { |
| 1143 | const char *emsg = NULL; |
| 1144 | int rc; |
| 1145 | u32 tmp; |
| 1146 | |
| 1147 | /* make sure port is not active */ |
| 1148 | rc = ahci_deinit_port(ap, &emsg); |
| 1149 | if (rc) |
| 1150 | dev_printk(KERN_WARNING, &pdev->dev, |
| 1151 | "%s (%d)\n", emsg, rc); |
| 1152 | |
| 1153 | /* clear SError */ |
| 1154 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 1155 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); |
| 1156 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 1157 | |
| 1158 | /* clear port IRQ */ |
| 1159 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 1160 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 1161 | if (tmp) |
| 1162 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 1163 | |
| 1164 | writel(1 << port_no, mmio + HOST_IRQ_STAT); |
| 1165 | } |
| 1166 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1167 | static void ahci_init_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1168 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 1169 | struct ahci_host_priv *hpriv = host->private_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1170 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 1171 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 1172 | int i; |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 1173 | void __iomem *port_mmio; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1174 | u32 tmp; |
| 1175 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 1176 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 1177 | port_mmio = __ahci_port_base(host, 4); |
| 1178 | |
| 1179 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 1180 | |
| 1181 | /* clear port IRQ */ |
| 1182 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 1183 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 1184 | if (tmp) |
| 1185 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 1186 | } |
| 1187 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1188 | for (i = 0; i < host->n_ports; i++) { |
| 1189 | struct ata_port *ap = host->ports[i]; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1190 | |
Jeff Garzik | cd70c26 | 2007-07-08 02:29:42 -0400 | [diff] [blame] | 1191 | port_mmio = ahci_port_base(ap); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1192 | if (ata_port_is_dummy(ap)) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1193 | continue; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1194 | |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 1195 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1196 | } |
| 1197 | |
| 1198 | tmp = readl(mmio + HOST_CTL); |
| 1199 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 1200 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 1201 | tmp = readl(mmio + HOST_CTL); |
| 1202 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 1203 | } |
| 1204 | |
Jeff Garzik | a878539 | 2008-02-28 15:43:48 -0500 | [diff] [blame] | 1205 | static void ahci_dev_config(struct ata_device *dev) |
| 1206 | { |
| 1207 | struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; |
| 1208 | |
| 1209 | if (hpriv->flags & AHCI_HFLAG_SECT255) |
| 1210 | dev->max_sectors = 255; |
| 1211 | } |
| 1212 | |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1213 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1214 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1215 | void __iomem *port_mmio = ahci_port_base(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1216 | struct ata_taskfile tf; |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1217 | u32 tmp; |
| 1218 | |
| 1219 | tmp = readl(port_mmio + PORT_SIG); |
| 1220 | tf.lbah = (tmp >> 24) & 0xff; |
| 1221 | tf.lbam = (tmp >> 16) & 0xff; |
| 1222 | tf.lbal = (tmp >> 8) & 0xff; |
| 1223 | tf.nsect = (tmp) & 0xff; |
| 1224 | |
| 1225 | return ata_dev_classify(&tf); |
| 1226 | } |
| 1227 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1228 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 1229 | u32 opts) |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1230 | { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1231 | dma_addr_t cmd_tbl_dma; |
| 1232 | |
| 1233 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; |
| 1234 | |
| 1235 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); |
| 1236 | pp->cmd_slot[tag].status = 0; |
| 1237 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); |
| 1238 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1239 | } |
| 1240 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1241 | static int ahci_kick_engine(struct ata_port *ap, int force_restart) |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1242 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1243 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1244 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1245 | u32 tmp; |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1246 | int busy, rc; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1247 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1248 | /* do we need to kick the port? */ |
| 1249 | busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ); |
| 1250 | if (!busy && !force_restart) |
| 1251 | return 0; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1252 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1253 | /* stop engine */ |
| 1254 | rc = ahci_stop_engine(ap); |
| 1255 | if (rc) |
| 1256 | goto out_restart; |
| 1257 | |
| 1258 | /* need to do CLO? */ |
| 1259 | if (!busy) { |
| 1260 | rc = 0; |
| 1261 | goto out_restart; |
| 1262 | } |
| 1263 | |
| 1264 | if (!(hpriv->cap & HOST_CAP_CLO)) { |
| 1265 | rc = -EOPNOTSUPP; |
| 1266 | goto out_restart; |
| 1267 | } |
| 1268 | |
| 1269 | /* perform CLO */ |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1270 | tmp = readl(port_mmio + PORT_CMD); |
| 1271 | tmp |= PORT_CMD_CLO; |
| 1272 | writel(tmp, port_mmio + PORT_CMD); |
| 1273 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1274 | rc = 0; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1275 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 1276 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); |
| 1277 | if (tmp & PORT_CMD_CLO) |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1278 | rc = -EIO; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1279 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1280 | /* restart engine */ |
| 1281 | out_restart: |
| 1282 | ahci_start_engine(ap); |
| 1283 | return rc; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 1284 | } |
| 1285 | |
Tejun Heo | 91c4a2e | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1286 | static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, |
| 1287 | struct ata_taskfile *tf, int is_cmd, u16 flags, |
| 1288 | unsigned long timeout_msec) |
| 1289 | { |
| 1290 | const u32 cmd_fis_len = 5; /* five dwords */ |
| 1291 | struct ahci_port_priv *pp = ap->private_data; |
| 1292 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1293 | u8 *fis = pp->cmd_tbl; |
| 1294 | u32 tmp; |
| 1295 | |
| 1296 | /* prep the command */ |
| 1297 | ata_tf_to_fis(tf, pmp, is_cmd, fis); |
| 1298 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); |
| 1299 | |
| 1300 | /* issue & wait */ |
| 1301 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 1302 | |
| 1303 | if (timeout_msec) { |
| 1304 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, |
| 1305 | 1, timeout_msec); |
| 1306 | if (tmp & 0x1) { |
| 1307 | ahci_kick_engine(ap, 1); |
| 1308 | return -EBUSY; |
| 1309 | } |
| 1310 | } else |
| 1311 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 1312 | |
| 1313 | return 0; |
| 1314 | } |
| 1315 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1316 | static int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1317 | int pmp, unsigned long deadline) |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1318 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1319 | struct ata_port *ap = link->ap; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1320 | const char *reason = NULL; |
Tejun Heo | 2cbb79e | 2007-07-16 14:29:38 +0900 | [diff] [blame] | 1321 | unsigned long now, msecs; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1322 | struct ata_taskfile tf; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1323 | int rc; |
| 1324 | |
| 1325 | DPRINTK("ENTER\n"); |
| 1326 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1327 | if (ata_link_offline(link)) { |
Tejun Heo | c2a6585 | 2006-04-03 01:58:06 +0900 | [diff] [blame] | 1328 | DPRINTK("PHY reports no device\n"); |
| 1329 | *class = ATA_DEV_NONE; |
| 1330 | return 0; |
| 1331 | } |
| 1332 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1333 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1334 | rc = ahci_kick_engine(ap, 1); |
Tejun Heo | 994056d | 2007-12-06 15:02:48 +0900 | [diff] [blame] | 1335 | if (rc && rc != -EOPNOTSUPP) |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1336 | ata_link_printk(link, KERN_WARNING, |
Tejun Heo | 994056d | 2007-12-06 15:02:48 +0900 | [diff] [blame] | 1337 | "failed to reset engine (errno=%d)\n", rc); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1338 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1339 | ata_tf_init(link->device, &tf); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1340 | |
| 1341 | /* issue the first D2H Register FIS */ |
Tejun Heo | 2cbb79e | 2007-07-16 14:29:38 +0900 | [diff] [blame] | 1342 | msecs = 0; |
| 1343 | now = jiffies; |
| 1344 | if (time_after(now, deadline)) |
| 1345 | msecs = jiffies_to_msecs(deadline - now); |
| 1346 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1347 | tf.ctl |= ATA_SRST; |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1348 | if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, |
Tejun Heo | 91c4a2e | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1349 | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1350 | rc = -EIO; |
| 1351 | reason = "1st FIS failed"; |
| 1352 | goto fail; |
| 1353 | } |
| 1354 | |
| 1355 | /* spec says at least 5us, but be generous and sleep for 1ms */ |
| 1356 | msleep(1); |
| 1357 | |
| 1358 | /* issue the second D2H Register FIS */ |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1359 | tf.ctl &= ~ATA_SRST; |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1360 | ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1361 | |
Tejun Heo | 88ff6ea | 2007-10-16 14:21:24 -0700 | [diff] [blame] | 1362 | /* wait a while before checking status */ |
| 1363 | ata_wait_after_reset(ap, deadline); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1364 | |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1365 | rc = ata_wait_ready(ap, deadline); |
| 1366 | /* link occupied, -ENODEV too is an error */ |
| 1367 | if (rc) { |
| 1368 | reason = "device not ready"; |
| 1369 | goto fail; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1370 | } |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1371 | *class = ahci_dev_classify(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1372 | |
| 1373 | DPRINTK("EXIT, class=%u\n", *class); |
| 1374 | return 0; |
| 1375 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1376 | fail: |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1377 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1378 | return rc; |
| 1379 | } |
| 1380 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1381 | static int ahci_softreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1382 | unsigned long deadline) |
| 1383 | { |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1384 | int pmp = 0; |
| 1385 | |
| 1386 | if (link->ap->flags & ATA_FLAG_PMP) |
| 1387 | pmp = SATA_PMP_CTRL_PORT; |
| 1388 | |
| 1389 | return ahci_do_softreset(link, class, pmp, deadline); |
Tejun Heo | a9cf5e8 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1390 | } |
| 1391 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1392 | static int ahci_hardreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1393 | unsigned long deadline) |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1394 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1395 | struct ata_port *ap = link->ap; |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1396 | struct ahci_port_priv *pp = ap->private_data; |
| 1397 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1398 | struct ata_taskfile tf; |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1399 | int rc; |
| 1400 | |
| 1401 | DPRINTK("ENTER\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1402 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1403 | ahci_stop_engine(ap); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1404 | |
| 1405 | /* clear D2H reception area to properly wait for D2H FIS */ |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1406 | ata_tf_init(link->device, &tf); |
Tejun Heo | dfd7a3d | 2007-01-26 15:37:20 +0900 | [diff] [blame] | 1407 | tf.command = 0x80; |
Tejun Heo | 9977126 | 2007-07-16 14:29:38 +0900 | [diff] [blame] | 1408 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1409 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1410 | rc = sata_std_hardreset(link, class, deadline); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1411 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1412 | ahci_start_engine(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1413 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1414 | if (rc == 0 && ata_link_online(link)) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1415 | *class = ahci_dev_classify(ap); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1416 | if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1417 | *class = ATA_DEV_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1418 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1419 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1420 | return rc; |
| 1421 | } |
| 1422 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1423 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1424 | unsigned long deadline) |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1425 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1426 | struct ata_port *ap = link->ap; |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1427 | u32 serror; |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1428 | int rc; |
| 1429 | |
| 1430 | DPRINTK("ENTER\n"); |
| 1431 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1432 | ahci_stop_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1433 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1434 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1435 | deadline); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1436 | |
| 1437 | /* vt8251 needs SError cleared for the port to operate */ |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1438 | ahci_scr_read(ap, SCR_ERROR, &serror); |
| 1439 | ahci_scr_write(ap, SCR_ERROR, serror); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1440 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1441 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1442 | |
| 1443 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1444 | |
| 1445 | /* vt8251 doesn't clear BSY on signature FIS reception, |
| 1446 | * request follow-up softreset. |
| 1447 | */ |
| 1448 | return rc ?: -EAGAIN; |
| 1449 | } |
| 1450 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 1451 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
| 1452 | unsigned long deadline) |
| 1453 | { |
| 1454 | struct ata_port *ap = link->ap; |
| 1455 | struct ahci_port_priv *pp = ap->private_data; |
| 1456 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1457 | struct ata_taskfile tf; |
| 1458 | int rc; |
| 1459 | |
| 1460 | ahci_stop_engine(ap); |
| 1461 | |
| 1462 | /* clear D2H reception area to properly wait for D2H FIS */ |
| 1463 | ata_tf_init(link->device, &tf); |
| 1464 | tf.command = 0x80; |
| 1465 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
| 1466 | |
| 1467 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
| 1468 | deadline); |
| 1469 | |
| 1470 | ahci_start_engine(ap); |
| 1471 | |
| 1472 | if (rc || ata_link_offline(link)) |
| 1473 | return rc; |
| 1474 | |
| 1475 | /* spec mandates ">= 2ms" before checking status */ |
| 1476 | msleep(150); |
| 1477 | |
| 1478 | /* The pseudo configuration device on SIMG4726 attached to |
| 1479 | * ASUS P5W-DH Deluxe doesn't send signature FIS after |
| 1480 | * hardreset if no device is attached to the first downstream |
| 1481 | * port && the pseudo device locks up on SRST w/ PMP==0. To |
| 1482 | * work around this, wait for !BSY only briefly. If BSY isn't |
| 1483 | * cleared, perform CLO and proceed to IDENTIFY (achieved by |
| 1484 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). |
| 1485 | * |
| 1486 | * Wait for two seconds. Devices attached to downstream port |
| 1487 | * which can't process the following IDENTIFY after this will |
| 1488 | * have to be reset again. For most cases, this should |
| 1489 | * suffice while making probing snappish enough. |
| 1490 | */ |
| 1491 | rc = ata_wait_ready(ap, jiffies + 2 * HZ); |
| 1492 | if (rc) |
| 1493 | ahci_kick_engine(ap, 0); |
| 1494 | |
| 1495 | return 0; |
| 1496 | } |
| 1497 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1498 | static void ahci_postreset(struct ata_link *link, unsigned int *class) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1499 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1500 | struct ata_port *ap = link->ap; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1501 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1502 | u32 new_tmp, tmp; |
| 1503 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 1504 | ata_std_postreset(link, class); |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1505 | |
| 1506 | /* Make sure port's ATAPI bit is set appropriately */ |
| 1507 | new_tmp = tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1508 | if (*class == ATA_DEV_ATAPI) |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1509 | new_tmp |= PORT_CMD_ATAPI; |
| 1510 | else |
| 1511 | new_tmp &= ~PORT_CMD_ATAPI; |
| 1512 | if (new_tmp != tmp) { |
| 1513 | writel(new_tmp, port_mmio + PORT_CMD); |
| 1514 | readl(port_mmio + PORT_CMD); /* flush */ |
| 1515 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1516 | } |
| 1517 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1518 | static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class, |
| 1519 | unsigned long deadline) |
| 1520 | { |
| 1521 | return ahci_do_softreset(link, class, link->pmp, deadline); |
| 1522 | } |
| 1523 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1524 | static u8 ahci_check_status(struct ata_port *ap) |
| 1525 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1526 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1527 | |
| 1528 | return readl(mmio + PORT_TFDATA) & 0xFF; |
| 1529 | } |
| 1530 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1531 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
| 1532 | { |
| 1533 | struct ahci_port_priv *pp = ap->private_data; |
| 1534 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1535 | |
| 1536 | ata_tf_from_fis(d2h_fis, tf); |
| 1537 | } |
| 1538 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1539 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1540 | { |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1541 | struct scatterlist *sg; |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 1542 | struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
| 1543 | unsigned int si; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1544 | |
| 1545 | VPRINTK("ENTER\n"); |
| 1546 | |
| 1547 | /* |
| 1548 | * Next, the S/G list. |
| 1549 | */ |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 1550 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1551 | dma_addr_t addr = sg_dma_address(sg); |
| 1552 | u32 sg_len = sg_dma_len(sg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1553 | |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 1554 | ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); |
| 1555 | ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); |
| 1556 | ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1557 | } |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1558 | |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 1559 | return si; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1560 | } |
| 1561 | |
| 1562 | static void ahci_qc_prep(struct ata_queued_cmd *qc) |
| 1563 | { |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 1564 | struct ata_port *ap = qc->ap; |
| 1565 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 405e66b | 2007-11-27 19:28:53 +0900 | [diff] [blame] | 1566 | int is_atapi = ata_is_atapi(qc->tf.protocol); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1567 | void *cmd_tbl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1568 | u32 opts; |
| 1569 | const u32 cmd_fis_len = 5; /* five dwords */ |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1570 | unsigned int n_elem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1571 | |
| 1572 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1573 | * Fill in command table information. First, the header, |
| 1574 | * a SATA Register - Host to Device command FIS. |
| 1575 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1576 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
| 1577 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1578 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1579 | if (is_atapi) { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1580 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
| 1581 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 1582 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1583 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1584 | n_elem = 0; |
| 1585 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1586 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1587 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1588 | /* |
| 1589 | * Fill in command slot information. |
| 1590 | */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1591 | opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1592 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
| 1593 | opts |= AHCI_CMD_WRITE; |
| 1594 | if (is_atapi) |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 1595 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1596 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1597 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1598 | } |
| 1599 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1600 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1601 | { |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 1602 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1603 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1604 | struct ata_eh_info *host_ehi = &ap->link.eh_info; |
| 1605 | struct ata_link *link = NULL; |
| 1606 | struct ata_queued_cmd *active_qc; |
| 1607 | struct ata_eh_info *active_ehi; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1608 | u32 serror; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1609 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1610 | /* determine active link */ |
| 1611 | ata_port_for_each_link(link, ap) |
| 1612 | if (ata_link_active(link)) |
| 1613 | break; |
| 1614 | if (!link) |
| 1615 | link = &ap->link; |
| 1616 | |
| 1617 | active_qc = ata_qc_from_tag(ap, link->active_tag); |
| 1618 | active_ehi = &link->eh_info; |
| 1619 | |
| 1620 | /* record irq stat */ |
| 1621 | ata_ehi_clear_desc(host_ehi); |
| 1622 | ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 1623 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1624 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 1625 | ahci_scr_read(ap, SCR_ERROR, &serror); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1626 | ahci_scr_write(ap, SCR_ERROR, serror); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1627 | host_ehi->serror |= serror; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1628 | |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 1629 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 1630 | if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 1631 | irq_stat &= ~PORT_IRQ_IF_ERR; |
| 1632 | |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 1633 | if (irq_stat & PORT_IRQ_TF_ERR) { |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1634 | /* If qc is active, charge it; otherwise, the active |
| 1635 | * link. There's no active qc on NCQ errors. It will |
| 1636 | * be determined by EH by reading log page 10h. |
| 1637 | */ |
| 1638 | if (active_qc) |
| 1639 | active_qc->err_mask |= AC_ERR_DEV; |
| 1640 | else |
| 1641 | active_ehi->err_mask |= AC_ERR_DEV; |
| 1642 | |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 1643 | if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1644 | host_ehi->serror &= ~SERR_INTERNAL; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1645 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1646 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1647 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
| 1648 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1649 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1650 | active_ehi->err_mask |= AC_ERR_HSM; |
| 1651 | active_ehi->action |= ATA_EH_SOFTRESET; |
| 1652 | ata_ehi_push_desc(active_ehi, |
| 1653 | "unknown FIS %08x %08x %08x %08x" , |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1654 | unk[0], unk[1], unk[2], unk[3]); |
| 1655 | } |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 1656 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1657 | if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) { |
| 1658 | active_ehi->err_mask |= AC_ERR_HSM; |
| 1659 | active_ehi->action |= ATA_EH_SOFTRESET; |
| 1660 | ata_ehi_push_desc(active_ehi, "incorrect PMP"); |
| 1661 | } |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1662 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1663 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { |
| 1664 | host_ehi->err_mask |= AC_ERR_HOST_BUS; |
| 1665 | host_ehi->action |= ATA_EH_SOFTRESET; |
| 1666 | ata_ehi_push_desc(host_ehi, "host bus error"); |
| 1667 | } |
| 1668 | |
| 1669 | if (irq_stat & PORT_IRQ_IF_ERR) { |
| 1670 | host_ehi->err_mask |= AC_ERR_ATA_BUS; |
| 1671 | host_ehi->action |= ATA_EH_SOFTRESET; |
| 1672 | ata_ehi_push_desc(host_ehi, "interface fatal error"); |
| 1673 | } |
| 1674 | |
| 1675 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
| 1676 | ata_ehi_hotplugged(host_ehi); |
| 1677 | ata_ehi_push_desc(host_ehi, "%s", |
| 1678 | irq_stat & PORT_IRQ_CONNECT ? |
| 1679 | "connection status changed" : "PHY RDY changed"); |
| 1680 | } |
| 1681 | |
| 1682 | /* okay, let's hand over to EH */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1683 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1684 | if (irq_stat & PORT_IRQ_FREEZE) |
| 1685 | ata_port_freeze(ap); |
| 1686 | else |
| 1687 | ata_port_abort(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1688 | } |
| 1689 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1690 | static void ahci_port_intr(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1691 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1692 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1693 | struct ata_eh_info *ehi = &ap->link.eh_info; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1694 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 1695 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | b06ce3e | 2007-10-09 15:06:48 +0900 | [diff] [blame] | 1696 | int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1697 | u32 status, qc_active; |
Tejun Heo | 459ad68 | 2007-12-07 12:46:23 +0900 | [diff] [blame] | 1698 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1699 | |
| 1700 | status = readl(port_mmio + PORT_IRQ_STAT); |
| 1701 | writel(status, port_mmio + PORT_IRQ_STAT); |
| 1702 | |
Tejun Heo | b06ce3e | 2007-10-09 15:06:48 +0900 | [diff] [blame] | 1703 | /* ignore BAD_PMP while resetting */ |
| 1704 | if (unlikely(resetting)) |
| 1705 | status &= ~PORT_IRQ_BAD_PMP; |
| 1706 | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 1707 | /* If we are getting PhyRdy, this is |
| 1708 | * just a power state change, we should |
| 1709 | * clear out this, plus the PhyRdy/Comm |
| 1710 | * Wake bits from Serror |
| 1711 | */ |
| 1712 | if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && |
| 1713 | (status & PORT_IRQ_PHYRDY)) { |
| 1714 | status &= ~PORT_IRQ_PHYRDY; |
| 1715 | ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18))); |
| 1716 | } |
| 1717 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1718 | if (unlikely(status & PORT_IRQ_ERROR)) { |
| 1719 | ahci_error_intr(ap, status); |
| 1720 | return; |
| 1721 | } |
| 1722 | |
Kristen Carlson Accardi | 2f29496 | 2007-08-15 04:11:25 -0400 | [diff] [blame] | 1723 | if (status & PORT_IRQ_SDB_FIS) { |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 1724 | /* If SNotification is available, leave notification |
| 1725 | * handling to sata_async_notification(). If not, |
| 1726 | * emulate it by snooping SDB FIS RX area. |
| 1727 | * |
| 1728 | * Snooping FIS RX area is probably cheaper than |
| 1729 | * poking SNotification but some constrollers which |
| 1730 | * implement SNotification, ICH9 for example, don't |
| 1731 | * store AN SDB FIS into receive area. |
Kristen Carlson Accardi | 2f29496 | 2007-08-15 04:11:25 -0400 | [diff] [blame] | 1732 | */ |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 1733 | if (hpriv->cap & HOST_CAP_SNTF) |
Tejun Heo | 7d77b24 | 2007-09-23 13:14:13 +0900 | [diff] [blame] | 1734 | sata_async_notification(ap); |
Tejun Heo | 5f226c6 | 2007-10-09 15:02:23 +0900 | [diff] [blame] | 1735 | else { |
| 1736 | /* If the 'N' bit in word 0 of the FIS is set, |
| 1737 | * we just received asynchronous notification. |
| 1738 | * Tell libata about it. |
| 1739 | */ |
| 1740 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
| 1741 | u32 f0 = le32_to_cpu(f[0]); |
| 1742 | |
| 1743 | if (f0 & (1 << 15)) |
| 1744 | sata_async_notification(ap); |
| 1745 | } |
Kristen Carlson Accardi | 2f29496 | 2007-08-15 04:11:25 -0400 | [diff] [blame] | 1746 | } |
| 1747 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1748 | /* pp->active_link is valid iff any command is in flight */ |
| 1749 | if (ap->qc_active && pp->active_link->sactive) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1750 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
| 1751 | else |
| 1752 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); |
| 1753 | |
| 1754 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); |
Tejun Heo | b06ce3e | 2007-10-09 15:06:48 +0900 | [diff] [blame] | 1755 | |
Tejun Heo | 459ad68 | 2007-12-07 12:46:23 +0900 | [diff] [blame] | 1756 | /* while resetting, invalid completions are expected */ |
| 1757 | if (unlikely(rc < 0 && !resetting)) { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1758 | ehi->err_mask |= AC_ERR_HSM; |
| 1759 | ehi->action |= ATA_EH_SOFTRESET; |
| 1760 | ata_port_freeze(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1761 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1762 | } |
| 1763 | |
| 1764 | static void ahci_irq_clear(struct ata_port *ap) |
| 1765 | { |
| 1766 | /* TODO */ |
| 1767 | } |
| 1768 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1769 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1770 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1771 | struct ata_host *host = dev_instance; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1772 | struct ahci_host_priv *hpriv; |
| 1773 | unsigned int i, handled = 0; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1774 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1775 | u32 irq_stat, irq_ack = 0; |
| 1776 | |
| 1777 | VPRINTK("ENTER\n"); |
| 1778 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1779 | hpriv = host->private_data; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1780 | mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1781 | |
| 1782 | /* sigh. 0xffffffff is a valid return from h/w */ |
| 1783 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
| 1784 | irq_stat &= hpriv->port_map; |
| 1785 | if (!irq_stat) |
| 1786 | return IRQ_NONE; |
| 1787 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 1788 | spin_lock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1789 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 1790 | for (i = 0; i < host->n_ports; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1791 | struct ata_port *ap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1792 | |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1793 | if (!(irq_stat & (1 << i))) |
| 1794 | continue; |
| 1795 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1796 | ap = host->ports[i]; |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1797 | if (ap) { |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1798 | ahci_port_intr(ap); |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1799 | VPRINTK("port %u\n", i); |
| 1800 | } else { |
| 1801 | VPRINTK("port %u (no irq)\n", i); |
Tejun Heo | 6971ed1 | 2006-03-11 12:47:54 +0900 | [diff] [blame] | 1802 | if (ata_ratelimit()) |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1803 | dev_printk(KERN_WARNING, host->dev, |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1804 | "interrupt on disabled port %u\n", i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1805 | } |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1806 | |
| 1807 | irq_ack |= (1 << i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1808 | } |
| 1809 | |
| 1810 | if (irq_ack) { |
| 1811 | writel(irq_ack, mmio + HOST_IRQ_STAT); |
| 1812 | handled = 1; |
| 1813 | } |
| 1814 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1815 | spin_unlock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1816 | |
| 1817 | VPRINTK("EXIT\n"); |
| 1818 | |
| 1819 | return IRQ_RETVAL(handled); |
| 1820 | } |
| 1821 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 1822 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1823 | { |
| 1824 | struct ata_port *ap = qc->ap; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1825 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1826 | struct ahci_port_priv *pp = ap->private_data; |
| 1827 | |
| 1828 | /* Keep track of the currently active link. It will be used |
| 1829 | * in completion path to determine whether NCQ phase is in |
| 1830 | * progress. |
| 1831 | */ |
| 1832 | pp->active_link = qc->dev->link; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1833 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1834 | if (qc->tf.protocol == ATA_PROT_NCQ) |
| 1835 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); |
| 1836 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1837 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 1838 | |
| 1839 | return 0; |
| 1840 | } |
| 1841 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1842 | static void ahci_freeze(struct ata_port *ap) |
| 1843 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1844 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1845 | |
| 1846 | /* turn IRQ off */ |
| 1847 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 1848 | } |
| 1849 | |
| 1850 | static void ahci_thaw(struct ata_port *ap) |
| 1851 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1852 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1853 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1854 | u32 tmp; |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 1855 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1856 | |
| 1857 | /* clear IRQ */ |
| 1858 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 1859 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
Tejun Heo | a718728 | 2007-01-27 11:04:26 +0900 | [diff] [blame] | 1860 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1861 | |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 1862 | /* turn IRQ back on */ |
| 1863 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1864 | } |
| 1865 | |
| 1866 | static void ahci_error_handler(struct ata_port *ap) |
| 1867 | { |
Tejun Heo | b51e9e5 | 2006-06-29 01:29:30 +0900 | [diff] [blame] | 1868 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1869 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1870 | ahci_stop_engine(ap); |
| 1871 | ahci_start_engine(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1872 | } |
| 1873 | |
| 1874 | /* perform recovery */ |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1875 | sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset, |
| 1876 | ahci_hardreset, ahci_postreset, |
| 1877 | sata_pmp_std_prereset, ahci_pmp_softreset, |
| 1878 | sata_pmp_std_hardreset, sata_pmp_std_postreset); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1879 | } |
| 1880 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1881 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
| 1882 | { |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1883 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
| 1884 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1885 | ahci_stop_engine(ap); |
| 1886 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1887 | } |
| 1888 | |
| 1889 | /* perform recovery */ |
| 1890 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, |
| 1891 | ahci_postreset); |
| 1892 | } |
| 1893 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 1894 | static void ahci_p5wdh_error_handler(struct ata_port *ap) |
| 1895 | { |
| 1896 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
| 1897 | /* restart engine */ |
| 1898 | ahci_stop_engine(ap); |
| 1899 | ahci_start_engine(ap); |
| 1900 | } |
| 1901 | |
| 1902 | /* perform recovery */ |
| 1903 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset, |
| 1904 | ahci_postreset); |
| 1905 | } |
| 1906 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1907 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
| 1908 | { |
| 1909 | struct ata_port *ap = qc->ap; |
| 1910 | |
Tejun Heo | d2e75df | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1911 | /* make DMA engine forget about the failed command */ |
| 1912 | if (qc->flags & ATA_QCFLAG_FAILED) |
| 1913 | ahci_kick_engine(ap, 1); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1914 | } |
| 1915 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1916 | static void ahci_pmp_attach(struct ata_port *ap) |
| 1917 | { |
| 1918 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 1919 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1920 | u32 cmd; |
| 1921 | |
| 1922 | cmd = readl(port_mmio + PORT_CMD); |
| 1923 | cmd |= PORT_CMD_PMP; |
| 1924 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 1925 | |
| 1926 | pp->intr_mask |= PORT_IRQ_BAD_PMP; |
| 1927 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1928 | } |
| 1929 | |
| 1930 | static void ahci_pmp_detach(struct ata_port *ap) |
| 1931 | { |
| 1932 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 1933 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1934 | u32 cmd; |
| 1935 | |
| 1936 | cmd = readl(port_mmio + PORT_CMD); |
| 1937 | cmd &= ~PORT_CMD_PMP; |
| 1938 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 1c954a4 | 2007-10-09 15:01:37 +0900 | [diff] [blame] | 1939 | |
| 1940 | pp->intr_mask &= ~PORT_IRQ_BAD_PMP; |
| 1941 | writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1942 | } |
| 1943 | |
Alexey Dobriyan | 028a259 | 2007-07-17 23:48:48 +0400 | [diff] [blame] | 1944 | static int ahci_port_resume(struct ata_port *ap) |
| 1945 | { |
| 1946 | ahci_power_up(ap); |
| 1947 | ahci_start_port(ap); |
| 1948 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1949 | if (ap->nr_pmp_links) |
| 1950 | ahci_pmp_attach(ap); |
| 1951 | else |
| 1952 | ahci_pmp_detach(ap); |
| 1953 | |
Alexey Dobriyan | 028a259 | 2007-07-17 23:48:48 +0400 | [diff] [blame] | 1954 | return 0; |
| 1955 | } |
| 1956 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1957 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1958 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
| 1959 | { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1960 | const char *emsg = NULL; |
| 1961 | int rc; |
| 1962 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1963 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1964 | if (rc == 0) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1965 | ahci_power_down(ap); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1966 | else { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1967 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1968 | ahci_start_port(ap); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1969 | } |
| 1970 | |
| 1971 | return rc; |
| 1972 | } |
| 1973 | |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1974 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
| 1975 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1976 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1977 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1978 | u32 ctl; |
| 1979 | |
Rafael J. Wysocki | 3a2d5b7 | 2008-02-23 19:13:25 +0100 | [diff] [blame] | 1980 | if (mesg.event & PM_EVENT_SLEEP) { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1981 | /* AHCI spec rev1.1 section 8.3.3: |
| 1982 | * Software must disable interrupts prior to requesting a |
| 1983 | * transition of the HBA to D3 state. |
| 1984 | */ |
| 1985 | ctl = readl(mmio + HOST_CTL); |
| 1986 | ctl &= ~HOST_IRQ_EN; |
| 1987 | writel(ctl, mmio + HOST_CTL); |
| 1988 | readl(mmio + HOST_CTL); /* flush */ |
| 1989 | } |
| 1990 | |
| 1991 | return ata_pci_device_suspend(pdev, mesg); |
| 1992 | } |
| 1993 | |
| 1994 | static int ahci_pci_device_resume(struct pci_dev *pdev) |
| 1995 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1996 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1997 | int rc; |
| 1998 | |
Tejun Heo | 553c4aa | 2006-12-26 19:39:50 +0900 | [diff] [blame] | 1999 | rc = ata_pci_device_do_resume(pdev); |
| 2000 | if (rc) |
| 2001 | return rc; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2002 | |
| 2003 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2004 | rc = ahci_reset_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2005 | if (rc) |
| 2006 | return rc; |
| 2007 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2008 | ahci_init_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2009 | } |
| 2010 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2011 | ata_host_resume(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2012 | |
| 2013 | return 0; |
| 2014 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 2015 | #endif |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2016 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2017 | static int ahci_port_start(struct ata_port *ap) |
| 2018 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2019 | struct device *dev = ap->host->dev; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2020 | struct ahci_port_priv *pp; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2021 | void *mem; |
| 2022 | dma_addr_t mem_dma; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2023 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2024 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2025 | if (!pp) |
| 2026 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2027 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2028 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
| 2029 | GFP_KERNEL); |
| 2030 | if (!mem) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2031 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2032 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
| 2033 | |
| 2034 | /* |
| 2035 | * First item in chunk of DMA memory: 32-slot command table, |
| 2036 | * 32 bytes each in size |
| 2037 | */ |
| 2038 | pp->cmd_slot = mem; |
| 2039 | pp->cmd_slot_dma = mem_dma; |
| 2040 | |
| 2041 | mem += AHCI_CMD_SLOT_SZ; |
| 2042 | mem_dma += AHCI_CMD_SLOT_SZ; |
| 2043 | |
| 2044 | /* |
| 2045 | * Second item: Received-FIS area |
| 2046 | */ |
| 2047 | pp->rx_fis = mem; |
| 2048 | pp->rx_fis_dma = mem_dma; |
| 2049 | |
| 2050 | mem += AHCI_RX_FIS_SZ; |
| 2051 | mem_dma += AHCI_RX_FIS_SZ; |
| 2052 | |
| 2053 | /* |
| 2054 | * Third item: data area for storing a single command |
| 2055 | * and its scatter-gather table |
| 2056 | */ |
| 2057 | pp->cmd_tbl = mem; |
| 2058 | pp->cmd_tbl_dma = mem_dma; |
| 2059 | |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 2060 | /* |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2061 | * Save off initial list of interrupts to be enabled. |
| 2062 | * This could be changed later |
| 2063 | */ |
Kristen Carlson Accardi | a738492 | 2007-08-09 14:23:41 -0700 | [diff] [blame] | 2064 | pp->intr_mask = DEF_PORT_IRQ; |
| 2065 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2066 | ap->private_data = pp; |
| 2067 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 2068 | /* engage engines, captain */ |
| 2069 | return ahci_port_resume(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2070 | } |
| 2071 | |
| 2072 | static void ahci_port_stop(struct ata_port *ap) |
| 2073 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2074 | const char *emsg = NULL; |
| 2075 | int rc; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2076 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2077 | /* de-initialize port */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2078 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 2079 | if (rc) |
| 2080 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 2081 | } |
| 2082 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2083 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2084 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2085 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2086 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2087 | if (using_dac && |
| 2088 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 2089 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 2090 | if (rc) { |
| 2091 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 2092 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2093 | dev_printk(KERN_ERR, &pdev->dev, |
| 2094 | "64-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2095 | return rc; |
| 2096 | } |
| 2097 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2098 | } else { |
| 2099 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 2100 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2101 | dev_printk(KERN_ERR, &pdev->dev, |
| 2102 | "32-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2103 | return rc; |
| 2104 | } |
| 2105 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 2106 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2107 | dev_printk(KERN_ERR, &pdev->dev, |
| 2108 | "32-bit consistent DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2109 | return rc; |
| 2110 | } |
| 2111 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2112 | return 0; |
| 2113 | } |
| 2114 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2115 | static void ahci_print_info(struct ata_host *host) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2116 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2117 | struct ahci_host_priv *hpriv = host->private_data; |
| 2118 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2119 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2120 | u32 vers, cap, impl, speed; |
| 2121 | const char *speed_s; |
| 2122 | u16 cc; |
| 2123 | const char *scc_s; |
| 2124 | |
| 2125 | vers = readl(mmio + HOST_VERSION); |
| 2126 | cap = hpriv->cap; |
| 2127 | impl = hpriv->port_map; |
| 2128 | |
| 2129 | speed = (cap >> 20) & 0xf; |
| 2130 | if (speed == 1) |
| 2131 | speed_s = "1.5"; |
| 2132 | else if (speed == 2) |
| 2133 | speed_s = "3"; |
| 2134 | else |
| 2135 | speed_s = "?"; |
| 2136 | |
| 2137 | pci_read_config_word(pdev, 0x0a, &cc); |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 2138 | if (cc == PCI_CLASS_STORAGE_IDE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2139 | scc_s = "IDE"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 2140 | else if (cc == PCI_CLASS_STORAGE_SATA) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2141 | scc_s = "SATA"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 2142 | else if (cc == PCI_CLASS_STORAGE_RAID) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2143 | scc_s = "RAID"; |
| 2144 | else |
| 2145 | scc_s = "unknown"; |
| 2146 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2147 | dev_printk(KERN_INFO, &pdev->dev, |
| 2148 | "AHCI %02x%02x.%02x%02x " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2149 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2150 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2151 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2152 | (vers >> 24) & 0xff, |
| 2153 | (vers >> 16) & 0xff, |
| 2154 | (vers >> 8) & 0xff, |
| 2155 | vers & 0xff, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2156 | |
| 2157 | ((cap >> 8) & 0x1f) + 1, |
| 2158 | (cap & 0x1f) + 1, |
| 2159 | speed_s, |
| 2160 | impl, |
| 2161 | scc_s); |
| 2162 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2163 | dev_printk(KERN_INFO, &pdev->dev, |
| 2164 | "flags: " |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2165 | "%s%s%s%s%s%s%s" |
| 2166 | "%s%s%s%s%s%s%s\n" |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 2167 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2168 | |
| 2169 | cap & (1 << 31) ? "64bit " : "", |
| 2170 | cap & (1 << 30) ? "ncq " : "", |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2171 | cap & (1 << 29) ? "sntf " : "", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2172 | cap & (1 << 28) ? "ilck " : "", |
| 2173 | cap & (1 << 27) ? "stag " : "", |
| 2174 | cap & (1 << 26) ? "pm " : "", |
| 2175 | cap & (1 << 25) ? "led " : "", |
| 2176 | |
| 2177 | cap & (1 << 24) ? "clo " : "", |
| 2178 | cap & (1 << 19) ? "nz " : "", |
| 2179 | cap & (1 << 18) ? "only " : "", |
| 2180 | cap & (1 << 17) ? "pmp " : "", |
| 2181 | cap & (1 << 15) ? "pio " : "", |
| 2182 | cap & (1 << 14) ? "slum " : "", |
| 2183 | cap & (1 << 13) ? "part " : "" |
| 2184 | ); |
| 2185 | } |
| 2186 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 2187 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
| 2188 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't |
| 2189 | * support PMP and the 4726 either directly exports the device |
| 2190 | * attached to the first downstream port or acts as a hardware storage |
| 2191 | * controller and emulate a single ATA device (can be RAID 0/1 or some |
| 2192 | * other configuration). |
| 2193 | * |
| 2194 | * When there's no device attached to the first downstream port of the |
| 2195 | * 4726, "Config Disk" appears, which is a pseudo ATA device to |
| 2196 | * configure the 4726. However, ATA emulation of the device is very |
| 2197 | * lame. It doesn't send signature D2H Reg FIS after the initial |
| 2198 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. |
| 2199 | * |
| 2200 | * The following function works around the problem by always using |
| 2201 | * hardreset on the port and not depending on receiving signature FIS |
| 2202 | * afterward. If signature FIS isn't received soon, ATA class is |
| 2203 | * assumed without follow-up softreset. |
| 2204 | */ |
| 2205 | static void ahci_p5wdh_workaround(struct ata_host *host) |
| 2206 | { |
| 2207 | static struct dmi_system_id sysids[] = { |
| 2208 | { |
| 2209 | .ident = "P5W DH Deluxe", |
| 2210 | .matches = { |
| 2211 | DMI_MATCH(DMI_SYS_VENDOR, |
| 2212 | "ASUSTEK COMPUTER INC"), |
| 2213 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), |
| 2214 | }, |
| 2215 | }, |
| 2216 | { } |
| 2217 | }; |
| 2218 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 2219 | |
| 2220 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && |
| 2221 | dmi_check_system(sysids)) { |
| 2222 | struct ata_port *ap = host->ports[1]; |
| 2223 | |
| 2224 | dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH " |
| 2225 | "Deluxe on-board SIMG4726 workaround\n"); |
| 2226 | |
| 2227 | ap->ops = &ahci_p5wdh_ops; |
| 2228 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; |
| 2229 | } |
| 2230 | } |
| 2231 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2232 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2233 | { |
| 2234 | static int printed_version; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2235 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
| 2236 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2237 | struct device *dev = &pdev->dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2238 | struct ahci_host_priv *hpriv; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2239 | struct ata_host *host; |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 2240 | int n_ports, i, rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2241 | |
| 2242 | VPRINTK("ENTER\n"); |
| 2243 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2244 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
| 2245 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2246 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2247 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2248 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2249 | /* acquire resources */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2250 | rc = pcim_enable_device(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2251 | if (rc) |
| 2252 | return rc; |
| 2253 | |
Tejun Heo | dea5513 | 2008-03-11 19:52:31 +0900 | [diff] [blame] | 2254 | /* AHCI controllers often implement SFF compatible interface. |
| 2255 | * Grab all PCI BARs just in case. |
| 2256 | */ |
| 2257 | rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2258 | if (rc == -EBUSY) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2259 | pcim_pin_device(pdev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2260 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2261 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2262 | |
Tejun Heo | c4f7792 | 2007-12-06 15:09:43 +0900 | [diff] [blame] | 2263 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
| 2264 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { |
| 2265 | u8 map; |
| 2266 | |
| 2267 | /* ICH6s share the same PCI ID for both piix and ahci |
| 2268 | * modes. Enabling ahci mode while MAP indicates |
| 2269 | * combined mode is a bad idea. Yield to ata_piix. |
| 2270 | */ |
| 2271 | pci_read_config_byte(pdev, ICH_MAP, &map); |
| 2272 | if (map & 0x3) { |
| 2273 | dev_printk(KERN_INFO, &pdev->dev, "controller is in " |
| 2274 | "combined mode, can't enable AHCI mode\n"); |
| 2275 | return -ENODEV; |
| 2276 | } |
| 2277 | } |
| 2278 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2279 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
| 2280 | if (!hpriv) |
| 2281 | return -ENOMEM; |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 2282 | hpriv->flags |= (unsigned long)pi.private_data; |
| 2283 | |
| 2284 | if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev)) |
| 2285 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2286 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2287 | /* save initial config */ |
Tejun Heo | 417a1a6 | 2007-09-23 13:19:55 +0900 | [diff] [blame] | 2288 | ahci_save_initial_config(pdev, hpriv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2289 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2290 | /* prepare host */ |
Tejun Heo | 274c1fd | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2291 | if (hpriv->cap & HOST_CAP_NCQ) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2292 | pi.flags |= ATA_FLAG_NCQ; |
| 2293 | |
Tejun Heo | 7d50b60 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 2294 | if (hpriv->cap & HOST_CAP_PMP) |
| 2295 | pi.flags |= ATA_FLAG_PMP; |
| 2296 | |
Tejun Heo | 837f5f8 | 2008-02-06 15:13:51 +0900 | [diff] [blame] | 2297 | /* CAP.NP sometimes indicate the index of the last enabled |
| 2298 | * port, at other times, that of the last possible port, so |
| 2299 | * determining the maximum port number requires looking at |
| 2300 | * both CAP.NP and port_map. |
| 2301 | */ |
| 2302 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); |
| 2303 | |
| 2304 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2305 | if (!host) |
| 2306 | return -ENOMEM; |
| 2307 | host->iomap = pcim_iomap_table(pdev); |
| 2308 | host->private_data = hpriv; |
| 2309 | |
| 2310 | for (i = 0; i < host->n_ports; i++) { |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 2311 | struct ata_port *ap = host->ports[i]; |
| 2312 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2313 | |
Tejun Heo | cbcdd87 | 2007-08-18 13:14:55 +0900 | [diff] [blame] | 2314 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
| 2315 | ata_port_pbar_desc(ap, AHCI_PCI_BAR, |
| 2316 | 0x100 + ap->port_no * 0x80, "port"); |
| 2317 | |
Kristen Carlson Accardi | 3155659 | 2007-10-25 01:33:26 -0400 | [diff] [blame] | 2318 | /* set initial link pm policy */ |
| 2319 | ap->pm_policy = NOT_AVAILABLE; |
| 2320 | |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 2321 | /* standard SATA port setup */ |
Tejun Heo | 203ef6c | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 2322 | if (hpriv->port_map & (1 << i)) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2323 | ap->ioaddr.cmd_addr = port_mmio; |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 2324 | |
| 2325 | /* disabled/not-implemented port */ |
| 2326 | else |
| 2327 | ap->ops = &ata_dummy_port_ops; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2328 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2329 | |
Tejun Heo | edc9305 | 2007-10-25 14:59:16 +0900 | [diff] [blame] | 2330 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
| 2331 | ahci_p5wdh_workaround(host); |
| 2332 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2333 | /* initialize adapter */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2334 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2335 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2336 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2337 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2338 | rc = ahci_reset_controller(host); |
| 2339 | if (rc) |
| 2340 | return rc; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 2341 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2342 | ahci_init_controller(host); |
| 2343 | ahci_print_info(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2344 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 2345 | pci_set_master(pdev); |
| 2346 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, |
| 2347 | &ahci_sht); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 2348 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2349 | |
| 2350 | static int __init ahci_init(void) |
| 2351 | { |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 2352 | return pci_register_driver(&ahci_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2353 | } |
| 2354 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2355 | static void __exit ahci_exit(void) |
| 2356 | { |
| 2357 | pci_unregister_driver(&ahci_pci_driver); |
| 2358 | } |
| 2359 | |
| 2360 | |
| 2361 | MODULE_AUTHOR("Jeff Garzik"); |
| 2362 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); |
| 2363 | MODULE_LICENSE("GPL"); |
| 2364 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); |
Jeff Garzik | 6885433 | 2005-08-23 02:53:51 -0400 | [diff] [blame] | 2365 | MODULE_VERSION(DRV_VERSION); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2366 | |
| 2367 | module_init(ahci_init); |
| 2368 | module_exit(ahci_exit); |