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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050045#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48#define DRV_NAME "ahci"
Jeff Garzikcd70c262007-07-08 02:29:42 -040049#define DRV_VERSION "2.3"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51
52enum {
53 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090054 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
Jens Axboebe5d8212007-05-22 09:45:39 +020057 AHCI_USE_CLUSTERING = 1,
Tejun Heo12fad3f2006-05-15 21:03:55 +090058 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090059 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090060 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040062 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090063 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070067 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090071 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +090072 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +090076 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +090077 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
79 board_ahci = 0,
Tejun Heo648a88b2006-11-09 15:08:40 +090080 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
Conke Hu55a61602007-03-27 18:33:05 +080083 board_ahci_sb600 = 4,
Jeff Garzikcd70c262007-07-08 02:29:42 -040084 board_ahci_mv = 5,
Linus Torvalds1da177e2005-04-16 15:20:36 -070085
86 /* global controller registers */
87 HOST_CAP = 0x00, /* host capabilities */
88 HOST_CTL = 0x04, /* global host control */
89 HOST_IRQ_STAT = 0x08, /* interrupt status */
90 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
91 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
92
93 /* HOST_CTL bits */
94 HOST_RESET = (1 << 0), /* reset controller; self-clear */
95 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
96 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
97
98 /* HOST_CAP bits */
Tejun Heo0be0aa92006-07-26 15:59:26 +090099 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo22b49982006-01-23 21:38:44 +0900100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo979db802006-05-15 21:03:52 +0900102 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900103 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104
105 /* registers for each SATA port */
106 PORT_LST_ADDR = 0x00, /* command list DMA addr */
107 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
108 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
109 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
110 PORT_IRQ_STAT = 0x10, /* interrupt status */
111 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
112 PORT_CMD = 0x18, /* port command */
113 PORT_TFDATA = 0x20, /* taskfile data */
114 PORT_SIG = 0x24, /* device TF signature */
115 PORT_CMD_ISSUE = 0x38, /* command issue */
116 PORT_SCR = 0x28, /* SATA phy register block */
117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
121
122 /* PORT_IRQ_{STAT,MASK} bits */
123 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
124 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
125 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
126 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
127 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
128 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
129 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
130 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
131
132 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
133 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
134 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
135 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
136 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
137 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
138 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
139 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
140 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
141
Tejun Heo78cd52d2006-05-15 20:58:29 +0900142 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
143 PORT_IRQ_IF_ERR |
144 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900145 PORT_IRQ_PHYRDY |
Tejun Heo78cd52d2006-05-15 20:58:29 +0900146 PORT_IRQ_UNK_FIS,
147 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
148 PORT_IRQ_TF_ERR |
149 PORT_IRQ_HBUS_DATA_ERR,
150 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
151 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
152 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153
154 /* PORT_CMD bits */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500155 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
157 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
158 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900159 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
161 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
162 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
163
Tejun Heo0be0aa92006-07-26 15:59:26 +0900164 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
166 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
167 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400168
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200169 /* ap->flags bits */
Tejun Heo4aeb0e32006-11-01 17:58:33 +0900170 AHCI_FLAG_NO_NCQ = (1 << 24),
171 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
Tejun Heo648a88b2006-11-09 15:08:40 +0900172 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
Conke Hu55a61602007-03-27 18:33:05 +0800173 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
Tejun Heoc7a42152007-05-18 16:23:19 +0200174 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
Jeff Garzikcd70c262007-07-08 02:29:42 -0400175 AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
176 AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900177
178 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Tejun Heo3cadbcc2007-05-15 03:28:15 +0900180 ATA_FLAG_SKIP_D2H_BSY |
181 ATA_FLAG_ACPI_SATA,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182};
183
184struct ahci_cmd_hdr {
185 u32 opts;
186 u32 status;
187 u32 tbl_addr;
188 u32 tbl_addr_hi;
189 u32 reserved[4];
190};
191
192struct ahci_sg {
193 u32 addr;
194 u32 addr_hi;
195 u32 reserved;
196 u32 flags_size;
197};
198
199struct ahci_host_priv {
Tejun Heod447df12007-03-18 22:15:33 +0900200 u32 cap; /* cap to use */
201 u32 port_map; /* port map to use */
202 u32 saved_cap; /* saved initial cap */
203 u32 saved_port_map; /* saved initial port_map */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204};
205
206struct ahci_port_priv {
207 struct ahci_cmd_hdr *cmd_slot;
208 dma_addr_t cmd_slot_dma;
209 void *cmd_tbl;
210 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 void *rx_fis;
212 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900213 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900214 unsigned int ncq_saw_d2h:1;
215 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900216 unsigned int ncq_saw_sdb:1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217};
218
Tejun Heoda3dbb12007-07-16 14:29:40 +0900219static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
220static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900222static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223static void ahci_irq_clear(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224static int ahci_port_start(struct ata_port *ap);
225static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
227static void ahci_qc_prep(struct ata_queued_cmd *qc);
228static u8 ahci_check_status(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900229static void ahci_freeze(struct ata_port *ap);
230static void ahci_thaw(struct ata_port *ap);
231static void ahci_error_handler(struct ata_port *ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900232static void ahci_vt8251_error_handler(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900233static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400234static int ahci_port_resume(struct ata_port *ap);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400235static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
236static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
237 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900238#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900239static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900240static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
241static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900242#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243
Jeff Garzik193515d2005-11-07 00:59:37 -0500244static struct scsi_host_template ahci_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 .module = THIS_MODULE,
246 .name = DRV_NAME,
247 .ioctl = ata_scsi_ioctl,
248 .queuecommand = ata_scsi_queuecmd,
Tejun Heo12fad3f2006-05-15 21:03:55 +0900249 .change_queue_depth = ata_scsi_change_queue_depth,
250 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 .this_id = ATA_SHT_THIS_ID,
252 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
254 .emulated = ATA_SHT_EMULATED,
255 .use_clustering = AHCI_USE_CLUSTERING,
256 .proc_name = DRV_NAME,
257 .dma_boundary = AHCI_DMA_BOUNDARY,
258 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900259 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261};
262
Jeff Garzik057ace52005-10-22 14:27:05 -0400263static const struct ata_port_operations ahci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 .port_disable = ata_port_disable,
265
266 .check_status = ahci_check_status,
267 .check_altstatus = ahci_check_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 .dev_select = ata_noop_dev_select,
269
270 .tf_read = ahci_tf_read,
271
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 .qc_prep = ahci_qc_prep,
273 .qc_issue = ahci_qc_issue,
274
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275 .irq_clear = ahci_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900276 .irq_on = ata_dummy_irq_on,
277 .irq_ack = ata_dummy_irq_ack,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278
279 .scr_read = ahci_scr_read,
280 .scr_write = ahci_scr_write,
281
Tejun Heo78cd52d2006-05-15 20:58:29 +0900282 .freeze = ahci_freeze,
283 .thaw = ahci_thaw,
284
285 .error_handler = ahci_error_handler,
286 .post_internal_cmd = ahci_post_internal_cmd,
287
Tejun Heo438ac6d2007-03-02 17:31:26 +0900288#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900289 .port_suspend = ahci_port_suspend,
290 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900291#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900292
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293 .port_start = ahci_port_start,
294 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295};
296
Tejun Heoad616ff2006-11-01 18:00:24 +0900297static const struct ata_port_operations ahci_vt8251_ops = {
298 .port_disable = ata_port_disable,
299
300 .check_status = ahci_check_status,
301 .check_altstatus = ahci_check_status,
302 .dev_select = ata_noop_dev_select,
303
304 .tf_read = ahci_tf_read,
305
306 .qc_prep = ahci_qc_prep,
307 .qc_issue = ahci_qc_issue,
308
Tejun Heoad616ff2006-11-01 18:00:24 +0900309 .irq_clear = ahci_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900310 .irq_on = ata_dummy_irq_on,
311 .irq_ack = ata_dummy_irq_ack,
Tejun Heoad616ff2006-11-01 18:00:24 +0900312
313 .scr_read = ahci_scr_read,
314 .scr_write = ahci_scr_write,
315
316 .freeze = ahci_freeze,
317 .thaw = ahci_thaw,
318
319 .error_handler = ahci_vt8251_error_handler,
320 .post_internal_cmd = ahci_post_internal_cmd,
321
Tejun Heo438ac6d2007-03-02 17:31:26 +0900322#ifdef CONFIG_PM
Tejun Heoad616ff2006-11-01 18:00:24 +0900323 .port_suspend = ahci_port_suspend,
324 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900325#endif
Tejun Heoad616ff2006-11-01 18:00:24 +0900326
327 .port_start = ahci_port_start,
328 .port_stop = ahci_port_stop,
329};
330
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100331static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 /* board_ahci */
333 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900334 .flags = AHCI_FLAG_COMMON,
Brett Russ7da79312005-09-01 21:53:34 -0400335 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400336 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337 .port_ops = &ahci_ops,
338 },
Tejun Heo648a88b2006-11-09 15:08:40 +0900339 /* board_ahci_pi */
340 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900341 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
Tejun Heo648a88b2006-11-09 15:08:40 +0900342 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400343 .udma_mask = ATA_UDMA6,
Tejun Heo648a88b2006-11-09 15:08:40 +0900344 .port_ops = &ahci_ops,
345 },
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200346 /* board_ahci_vt8251 */
347 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900348 .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME |
349 AHCI_FLAG_NO_NCQ,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200350 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400351 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900352 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200353 },
Tejun Heo41669552006-11-29 11:33:14 +0900354 /* board_ahci_ign_iferr */
355 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900356 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
Tejun Heo41669552006-11-29 11:33:14 +0900357 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400358 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900359 .port_ops = &ahci_ops,
360 },
Conke Hu55a61602007-03-27 18:33:05 +0800361 /* board_ahci_sb600 */
362 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900363 .flags = AHCI_FLAG_COMMON |
Tejun Heoc7a42152007-05-18 16:23:19 +0200364 AHCI_FLAG_IGN_SERR_INTERNAL |
365 AHCI_FLAG_32BIT_ONLY,
Conke Hu55a61602007-03-27 18:33:05 +0800366 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400367 .udma_mask = ATA_UDMA6,
Conke Hu55a61602007-03-27 18:33:05 +0800368 .port_ops = &ahci_ops,
369 },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400370 /* board_ahci_mv */
371 {
372 .sht = &ahci_sht,
373 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
374 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
375 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI |
376 AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
377 AHCI_FLAG_MV_PATA,
378 .pio_mask = 0x1f, /* pio0-4 */
379 .udma_mask = ATA_UDMA6,
380 .port_ops = &ahci_ops,
381 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382};
383
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500384static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400385 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400386 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
387 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
388 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
389 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
390 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900391 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400392 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
393 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
394 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
395 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo648a88b2006-11-09 15:08:40 +0900396 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
397 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
398 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
399 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
400 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
401 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
402 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
403 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
404 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
405 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
406 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
407 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
408 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
Jason Gaston8af12cd2007-03-02 17:39:46 -0800409 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
Tejun Heo648a88b2006-11-09 15:08:40 +0900410 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
411 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
412 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400413
Tejun Heoe34bb372007-02-26 20:24:03 +0900414 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
415 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
416 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400417
418 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800419 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Henry Su2bcfdde2007-05-10 22:48:51 -0700420 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400421
422 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400423 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900424 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400425
426 /* NVIDIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400427 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
Peer Chen6fbf5ba2006-12-20 14:18:00 -0500431 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
433 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
434 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
Peer Chen895663c2006-11-02 17:59:46 -0500439 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
Peer Chen0522b282007-06-07 18:05:12 +0800447 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
448 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
449 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
450 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
451 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
460 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
461 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
462 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
463 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400471
Jeff Garzik95916ed2006-07-29 04:10:14 -0400472 /* SiS */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400473 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
474 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
475 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400476
Jeff Garzikcd70c262007-07-08 02:29:42 -0400477 /* Marvell */
478 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
479
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500480 /* Generic, PCI class code for AHCI */
481 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500482 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500483
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484 { } /* terminate list */
485};
486
487
488static struct pci_driver ahci_pci_driver = {
489 .name = DRV_NAME,
490 .id_table = ahci_pci_tbl,
491 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900492 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900493#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900494 .suspend = ahci_pci_device_suspend,
495 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900496#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497};
498
499
Tejun Heo98fa4b62006-11-02 12:17:23 +0900500static inline int ahci_nr_ports(u32 cap)
501{
502 return (cap & 0x1f) + 1;
503}
504
Jeff Garzikdab632e2007-05-28 08:33:01 -0400505static inline void __iomem *__ahci_port_base(struct ata_host *host,
506 unsigned int port_no)
507{
508 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
509
510 return mmio + 0x100 + (port_no * 0x80);
511}
512
Tejun Heo4447d352007-04-17 23:44:08 +0900513static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400515 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516}
517
Tejun Heod447df12007-03-18 22:15:33 +0900518/**
519 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900520 * @pdev: target PCI device
521 * @pi: associated ATA port info
522 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900523 *
524 * Some registers containing configuration info might be setup by
525 * BIOS and might be cleared on reset. This function saves the
526 * initial values of those registers into @hpriv such that they
527 * can be restored after controller reset.
528 *
529 * If inconsistent, config values are fixed up by this function.
530 *
531 * LOCKING:
532 * None.
533 */
Tejun Heo4447d352007-04-17 23:44:08 +0900534static void ahci_save_initial_config(struct pci_dev *pdev,
535 const struct ata_port_info *pi,
536 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900537{
Tejun Heo4447d352007-04-17 23:44:08 +0900538 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900539 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900540 int i;
Tejun Heod447df12007-03-18 22:15:33 +0900541
542 /* Values prefixed with saved_ are written back to host after
543 * reset. Values without are used for driver operation.
544 */
545 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
546 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
547
Tejun Heoc7a42152007-05-18 16:23:19 +0200548 /* some chips lie about 64bit support */
549 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
550 dev_printk(KERN_INFO, &pdev->dev,
551 "controller can't do 64bit DMA, forcing 32bit\n");
552 cap &= ~HOST_CAP_64;
553 }
554
Tejun Heod447df12007-03-18 22:15:33 +0900555 /* fixup zero port_map */
556 if (!port_map) {
Tejun Heoa3d2cc52007-06-19 18:52:56 +0900557 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo4447d352007-04-17 23:44:08 +0900558 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heod447df12007-03-18 22:15:33 +0900559 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
560
561 /* write the fixed up value to the PI register */
562 hpriv->saved_port_map = port_map;
563 }
564
Jeff Garzikcd70c262007-07-08 02:29:42 -0400565 /*
566 * Temporary Marvell 6145 hack: PATA port presence
567 * is asserted through the standard AHCI port
568 * presence register, as bit 4 (counting from 0)
569 */
570 if (pi->flags & AHCI_FLAG_MV_PATA) {
571 dev_printk(KERN_ERR, &pdev->dev,
572 "MV_AHCI HACK: port_map %x -> %x\n",
573 hpriv->port_map,
574 hpriv->port_map & 0xf);
575
576 port_map &= 0xf;
577 }
578
Tejun Heo17199b12007-03-18 22:26:53 +0900579 /* cross check port_map and cap.n_ports */
Tejun Heo4447d352007-04-17 23:44:08 +0900580 if (pi->flags & AHCI_FLAG_HONOR_PI) {
Tejun Heo17199b12007-03-18 22:26:53 +0900581 u32 tmp_port_map = port_map;
582 int n_ports = ahci_nr_ports(cap);
583
584 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
585 if (tmp_port_map & (1 << i)) {
586 n_ports--;
587 tmp_port_map &= ~(1 << i);
588 }
589 }
590
591 /* Whine if inconsistent. No need to update cap.
592 * port_map is used to determine number of ports.
593 */
594 if (n_ports || tmp_port_map)
Tejun Heo4447d352007-04-17 23:44:08 +0900595 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo17199b12007-03-18 22:26:53 +0900596 "nr_ports (%u) and implemented port map "
597 "(0x%x) don't match\n",
598 ahci_nr_ports(cap), port_map);
599 } else {
600 /* fabricate port_map from cap.nr_ports */
601 port_map = (1 << ahci_nr_ports(cap)) - 1;
602 }
603
Tejun Heod447df12007-03-18 22:15:33 +0900604 /* record values to use during operation */
605 hpriv->cap = cap;
606 hpriv->port_map = port_map;
607}
608
609/**
610 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900611 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900612 *
613 * Restore initial config stored by ahci_save_initial_config().
614 *
615 * LOCKING:
616 * None.
617 */
Tejun Heo4447d352007-04-17 23:44:08 +0900618static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900619{
Tejun Heo4447d352007-04-17 23:44:08 +0900620 struct ahci_host_priv *hpriv = host->private_data;
621 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
622
Tejun Heod447df12007-03-18 22:15:33 +0900623 writel(hpriv->saved_cap, mmio + HOST_CAP);
624 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
625 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
626}
627
Tejun Heoda3dbb12007-07-16 14:29:40 +0900628static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629{
630 unsigned int sc_reg;
631
632 switch (sc_reg_in) {
633 case SCR_STATUS: sc_reg = 0; break;
634 case SCR_CONTROL: sc_reg = 1; break;
635 case SCR_ERROR: sc_reg = 2; break;
636 case SCR_ACTIVE: sc_reg = 3; break;
637 default:
Tejun Heoda3dbb12007-07-16 14:29:40 +0900638 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639 }
640
Tejun Heoda3dbb12007-07-16 14:29:40 +0900641 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
642 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643}
644
645
Tejun Heoda3dbb12007-07-16 14:29:40 +0900646static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647{
648 unsigned int sc_reg;
649
650 switch (sc_reg_in) {
651 case SCR_STATUS: sc_reg = 0; break;
652 case SCR_CONTROL: sc_reg = 1; break;
653 case SCR_ERROR: sc_reg = 2; break;
654 case SCR_ACTIVE: sc_reg = 3; break;
655 default:
Tejun Heoda3dbb12007-07-16 14:29:40 +0900656 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 }
658
Tejun Heo0d5ff562007-02-01 15:06:36 +0900659 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
Tejun Heoda3dbb12007-07-16 14:29:40 +0900660 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661}
662
Tejun Heo4447d352007-04-17 23:44:08 +0900663static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900664{
Tejun Heo4447d352007-04-17 23:44:08 +0900665 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900666 u32 tmp;
667
Tejun Heod8fcd112006-07-26 15:59:25 +0900668 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900669 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900670 tmp |= PORT_CMD_START;
671 writel(tmp, port_mmio + PORT_CMD);
672 readl(port_mmio + PORT_CMD); /* flush */
673}
674
Tejun Heo4447d352007-04-17 23:44:08 +0900675static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900676{
Tejun Heo4447d352007-04-17 23:44:08 +0900677 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900678 u32 tmp;
679
680 tmp = readl(port_mmio + PORT_CMD);
681
Tejun Heod8fcd112006-07-26 15:59:25 +0900682 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900683 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
684 return 0;
685
Tejun Heod8fcd112006-07-26 15:59:25 +0900686 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900687 tmp &= ~PORT_CMD_START;
688 writel(tmp, port_mmio + PORT_CMD);
689
Tejun Heod8fcd112006-07-26 15:59:25 +0900690 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900691 tmp = ata_wait_register(port_mmio + PORT_CMD,
692 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900693 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900694 return -EIO;
695
696 return 0;
697}
698
Tejun Heo4447d352007-04-17 23:44:08 +0900699static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900700{
Tejun Heo4447d352007-04-17 23:44:08 +0900701 void __iomem *port_mmio = ahci_port_base(ap);
702 struct ahci_host_priv *hpriv = ap->host->private_data;
703 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900704 u32 tmp;
705
706 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900707 if (hpriv->cap & HOST_CAP_64)
708 writel((pp->cmd_slot_dma >> 16) >> 16,
709 port_mmio + PORT_LST_ADDR_HI);
710 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900711
Tejun Heo4447d352007-04-17 23:44:08 +0900712 if (hpriv->cap & HOST_CAP_64)
713 writel((pp->rx_fis_dma >> 16) >> 16,
714 port_mmio + PORT_FIS_ADDR_HI);
715 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900716
717 /* enable FIS reception */
718 tmp = readl(port_mmio + PORT_CMD);
719 tmp |= PORT_CMD_FIS_RX;
720 writel(tmp, port_mmio + PORT_CMD);
721
722 /* flush */
723 readl(port_mmio + PORT_CMD);
724}
725
Tejun Heo4447d352007-04-17 23:44:08 +0900726static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900727{
Tejun Heo4447d352007-04-17 23:44:08 +0900728 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900729 u32 tmp;
730
731 /* disable FIS reception */
732 tmp = readl(port_mmio + PORT_CMD);
733 tmp &= ~PORT_CMD_FIS_RX;
734 writel(tmp, port_mmio + PORT_CMD);
735
736 /* wait for completion, spec says 500ms, give it 1000 */
737 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
738 PORT_CMD_FIS_ON, 10, 1000);
739 if (tmp & PORT_CMD_FIS_ON)
740 return -EBUSY;
741
742 return 0;
743}
744
Tejun Heo4447d352007-04-17 23:44:08 +0900745static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900746{
Tejun Heo4447d352007-04-17 23:44:08 +0900747 struct ahci_host_priv *hpriv = ap->host->private_data;
748 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900749 u32 cmd;
750
751 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
752
753 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +0900754 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +0900755 cmd |= PORT_CMD_SPIN_UP;
756 writel(cmd, port_mmio + PORT_CMD);
757 }
758
759 /* wake up link */
760 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
761}
762
Tejun Heo438ac6d2007-03-02 17:31:26 +0900763#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +0900764static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900765{
Tejun Heo4447d352007-04-17 23:44:08 +0900766 struct ahci_host_priv *hpriv = ap->host->private_data;
767 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900768 u32 cmd, scontrol;
769
Tejun Heo4447d352007-04-17 23:44:08 +0900770 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +0900771 return;
772
773 /* put device into listen mode, first set PxSCTL.DET to 0 */
774 scontrol = readl(port_mmio + PORT_SCR_CTL);
775 scontrol &= ~0xf;
776 writel(scontrol, port_mmio + PORT_SCR_CTL);
777
778 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900779 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +0900780 cmd &= ~PORT_CMD_SPIN_UP;
781 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900782}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900783#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +0900784
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400785static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900786{
Tejun Heo0be0aa92006-07-26 15:59:26 +0900787 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +0900788 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900789
790 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +0900791 ahci_start_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900792}
793
Tejun Heo4447d352007-04-17 23:44:08 +0900794static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900795{
796 int rc;
797
798 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +0900799 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900800 if (rc) {
801 *emsg = "failed to stop engine";
802 return rc;
803 }
804
805 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +0900806 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900807 if (rc) {
808 *emsg = "failed stop FIS RX";
809 return rc;
810 }
811
Tejun Heo0be0aa92006-07-26 15:59:26 +0900812 return 0;
813}
814
Tejun Heo4447d352007-04-17 23:44:08 +0900815static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +0900816{
Tejun Heo4447d352007-04-17 23:44:08 +0900817 struct pci_dev *pdev = to_pci_dev(host->dev);
818 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900819 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +0900820
821 /* global controller reset */
822 tmp = readl(mmio + HOST_CTL);
823 if ((tmp & HOST_RESET) == 0) {
824 writel(tmp | HOST_RESET, mmio + HOST_CTL);
825 readl(mmio + HOST_CTL); /* flush */
826 }
827
828 /* reset must complete within 1 second, or
829 * the hardware should be considered fried.
830 */
831 ssleep(1);
832
833 tmp = readl(mmio + HOST_CTL);
834 if (tmp & HOST_RESET) {
Tejun Heo4447d352007-04-17 23:44:08 +0900835 dev_printk(KERN_ERR, host->dev,
Tejun Heod91542c2006-07-26 15:59:26 +0900836 "controller reset failed (0x%x)\n", tmp);
837 return -EIO;
838 }
839
Tejun Heo98fa4b62006-11-02 12:17:23 +0900840 /* turn on AHCI mode */
Tejun Heod91542c2006-07-26 15:59:26 +0900841 writel(HOST_AHCI_EN, mmio + HOST_CTL);
842 (void) readl(mmio + HOST_CTL); /* flush */
Tejun Heo98fa4b62006-11-02 12:17:23 +0900843
Tejun Heod447df12007-03-18 22:15:33 +0900844 /* some registers might be cleared on reset. restore initial values */
Tejun Heo4447d352007-04-17 23:44:08 +0900845 ahci_restore_initial_config(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900846
847 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
848 u16 tmp16;
849
850 /* configure PCS */
851 pci_read_config_word(pdev, 0x92, &tmp16);
852 tmp16 |= 0xf;
853 pci_write_config_word(pdev, 0x92, tmp16);
854 }
855
856 return 0;
857}
858
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400859static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
860 int port_no, void __iomem *mmio,
861 void __iomem *port_mmio)
862{
863 const char *emsg = NULL;
864 int rc;
865 u32 tmp;
866
867 /* make sure port is not active */
868 rc = ahci_deinit_port(ap, &emsg);
869 if (rc)
870 dev_printk(KERN_WARNING, &pdev->dev,
871 "%s (%d)\n", emsg, rc);
872
873 /* clear SError */
874 tmp = readl(port_mmio + PORT_SCR_ERR);
875 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
876 writel(tmp, port_mmio + PORT_SCR_ERR);
877
878 /* clear port IRQ */
879 tmp = readl(port_mmio + PORT_IRQ_STAT);
880 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
881 if (tmp)
882 writel(tmp, port_mmio + PORT_IRQ_STAT);
883
884 writel(1 << port_no, mmio + HOST_IRQ_STAT);
885}
886
Tejun Heo4447d352007-04-17 23:44:08 +0900887static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +0900888{
Tejun Heo4447d352007-04-17 23:44:08 +0900889 struct pci_dev *pdev = to_pci_dev(host->dev);
890 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400891 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400892 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +0900893 u32 tmp;
894
Jeff Garzikcd70c262007-07-08 02:29:42 -0400895 if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
896 port_mmio = __ahci_port_base(host, 4);
897
898 writel(0, port_mmio + PORT_IRQ_MASK);
899
900 /* clear port IRQ */
901 tmp = readl(port_mmio + PORT_IRQ_STAT);
902 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
903 if (tmp)
904 writel(tmp, port_mmio + PORT_IRQ_STAT);
905 }
906
Tejun Heo4447d352007-04-17 23:44:08 +0900907 for (i = 0; i < host->n_ports; i++) {
908 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +0900909
Jeff Garzikcd70c262007-07-08 02:29:42 -0400910 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +0900911 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +0900912 continue;
Tejun Heod91542c2006-07-26 15:59:26 +0900913
Jeff Garzik2bcd8662007-05-28 07:45:27 -0400914 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +0900915 }
916
917 tmp = readl(mmio + HOST_CTL);
918 VPRINTK("HOST_CTL 0x%x\n", tmp);
919 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
920 tmp = readl(mmio + HOST_CTL);
921 VPRINTK("HOST_CTL 0x%x\n", tmp);
922}
923
Tejun Heo422b7592005-12-19 22:37:17 +0900924static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925{
Tejun Heo4447d352007-04-17 23:44:08 +0900926 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +0900928 u32 tmp;
929
930 tmp = readl(port_mmio + PORT_SIG);
931 tf.lbah = (tmp >> 24) & 0xff;
932 tf.lbam = (tmp >> 16) & 0xff;
933 tf.lbal = (tmp >> 8) & 0xff;
934 tf.nsect = (tmp) & 0xff;
935
936 return ata_dev_classify(&tf);
937}
938
Tejun Heo12fad3f2006-05-15 21:03:55 +0900939static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
940 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +0900941{
Tejun Heo12fad3f2006-05-15 21:03:55 +0900942 dma_addr_t cmd_tbl_dma;
943
944 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
945
946 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
947 pp->cmd_slot[tag].status = 0;
948 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
949 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +0900950}
951
Tejun Heod2e75df2007-07-16 14:29:39 +0900952static int ahci_kick_engine(struct ata_port *ap, int force_restart)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200953{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900954 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Jeff Garzikcca39742006-08-24 03:19:22 -0400955 struct ahci_host_priv *hpriv = ap->host->private_data;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200956 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +0900957 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200958
Tejun Heod2e75df2007-07-16 14:29:39 +0900959 /* do we need to kick the port? */
960 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
961 if (!busy && !force_restart)
962 return 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200963
Tejun Heod2e75df2007-07-16 14:29:39 +0900964 /* stop engine */
965 rc = ahci_stop_engine(ap);
966 if (rc)
967 goto out_restart;
968
969 /* need to do CLO? */
970 if (!busy) {
971 rc = 0;
972 goto out_restart;
973 }
974
975 if (!(hpriv->cap & HOST_CAP_CLO)) {
976 rc = -EOPNOTSUPP;
977 goto out_restart;
978 }
979
980 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200981 tmp = readl(port_mmio + PORT_CMD);
982 tmp |= PORT_CMD_CLO;
983 writel(tmp, port_mmio + PORT_CMD);
984
Tejun Heod2e75df2007-07-16 14:29:39 +0900985 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200986 tmp = ata_wait_register(port_mmio + PORT_CMD,
987 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
988 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +0900989 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200990
Tejun Heod2e75df2007-07-16 14:29:39 +0900991 /* restart engine */
992 out_restart:
993 ahci_start_engine(ap);
994 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200995}
996
Tejun Heo91c4a2e2007-07-16 14:29:39 +0900997static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
998 struct ata_taskfile *tf, int is_cmd, u16 flags,
999 unsigned long timeout_msec)
1000{
1001 const u32 cmd_fis_len = 5; /* five dwords */
1002 struct ahci_port_priv *pp = ap->private_data;
1003 void __iomem *port_mmio = ahci_port_base(ap);
1004 u8 *fis = pp->cmd_tbl;
1005 u32 tmp;
1006
1007 /* prep the command */
1008 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1009 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1010
1011 /* issue & wait */
1012 writel(1, port_mmio + PORT_CMD_ISSUE);
1013
1014 if (timeout_msec) {
1015 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1016 1, timeout_msec);
1017 if (tmp & 0x1) {
1018 ahci_kick_engine(ap, 1);
1019 return -EBUSY;
1020 }
1021 } else
1022 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1023
1024 return 0;
1025}
1026
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001027static int ahci_do_softreset(struct ata_port *ap, unsigned int *class,
1028 int pmp, unsigned long deadline)
Tejun Heo4658f792006-03-22 21:07:03 +09001029{
Tejun Heo4658f792006-03-22 21:07:03 +09001030 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001031 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001032 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001033 int rc;
1034
1035 DPRINTK("ENTER\n");
1036
Tejun Heo81952c52006-05-15 20:57:47 +09001037 if (ata_port_offline(ap)) {
Tejun Heoc2a65852006-04-03 01:58:06 +09001038 DPRINTK("PHY reports no device\n");
1039 *class = ATA_DEV_NONE;
1040 return 0;
1041 }
1042
Tejun Heo4658f792006-03-22 21:07:03 +09001043 /* prepare for SRST (AHCI-1.1 10.4.1) */
Tejun Heod2e75df2007-07-16 14:29:39 +09001044 rc = ahci_kick_engine(ap, 1);
1045 if (rc)
1046 ata_port_printk(ap, KERN_WARNING,
1047 "failed to reset engine (errno=%d)", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001048
Tejun Heo3373efd2006-05-15 20:57:53 +09001049 ata_tf_init(ap->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001050
1051 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001052 msecs = 0;
1053 now = jiffies;
1054 if (time_after(now, deadline))
1055 msecs = jiffies_to_msecs(deadline - now);
1056
Tejun Heo4658f792006-03-22 21:07:03 +09001057 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001058 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001059 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001060 rc = -EIO;
1061 reason = "1st FIS failed";
1062 goto fail;
1063 }
1064
1065 /* spec says at least 5us, but be generous and sleep for 1ms */
1066 msleep(1);
1067
1068 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001069 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001070 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001071
1072 /* spec mandates ">= 2ms" before checking status.
1073 * We wait 150ms, because that was the magic delay used for
1074 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1075 * between when the ATA command register is written, and then
1076 * status is checked. Because waiting for "a while" before
1077 * checking status is fine, post SRST, we perform this magic
1078 * delay here as well.
1079 */
1080 msleep(150);
1081
Tejun Heo9b893912007-02-02 16:50:52 +09001082 rc = ata_wait_ready(ap, deadline);
1083 /* link occupied, -ENODEV too is an error */
1084 if (rc) {
1085 reason = "device not ready";
1086 goto fail;
Tejun Heo4658f792006-03-22 21:07:03 +09001087 }
Tejun Heo9b893912007-02-02 16:50:52 +09001088 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001089
1090 DPRINTK("EXIT, class=%u\n", *class);
1091 return 0;
1092
Tejun Heo4658f792006-03-22 21:07:03 +09001093 fail:
Tejun Heof15a1da2006-05-15 20:57:56 +09001094 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001095 return rc;
1096}
1097
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001098static int ahci_softreset(struct ata_port *ap, unsigned int *class,
1099 unsigned long deadline)
1100{
1101 return ahci_do_softreset(ap, class, 0, deadline);
1102}
1103
Tejun Heod4b2bab2007-02-02 16:50:52 +09001104static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
1105 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001106{
Tejun Heo42969712006-05-31 18:28:18 +09001107 struct ahci_port_priv *pp = ap->private_data;
1108 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1109 struct ata_taskfile tf;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001110 int rc;
1111
1112 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113
Tejun Heo4447d352007-04-17 23:44:08 +09001114 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001115
1116 /* clear D2H reception area to properly wait for D2H FIS */
1117 ata_tf_init(ap->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001118 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001119 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001120
Tejun Heod4b2bab2007-02-02 16:50:52 +09001121 rc = sata_std_hardreset(ap, class, deadline);
Tejun Heo42969712006-05-31 18:28:18 +09001122
Tejun Heo4447d352007-04-17 23:44:08 +09001123 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124
Tejun Heo81952c52006-05-15 20:57:47 +09001125 if (rc == 0 && ata_port_online(ap))
Tejun Heo4bd00f62006-02-11 16:26:02 +09001126 *class = ahci_dev_classify(ap);
1127 if (*class == ATA_DEV_UNKNOWN)
1128 *class = ATA_DEV_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129
Tejun Heo4bd00f62006-02-11 16:26:02 +09001130 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1131 return rc;
1132}
1133
Tejun Heod4b2bab2007-02-02 16:50:52 +09001134static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
1135 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001136{
Tejun Heoda3dbb12007-07-16 14:29:40 +09001137 u32 serror;
Tejun Heoad616ff2006-11-01 18:00:24 +09001138 int rc;
1139
1140 DPRINTK("ENTER\n");
1141
Tejun Heo4447d352007-04-17 23:44:08 +09001142 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001143
Tejun Heod4b2bab2007-02-02 16:50:52 +09001144 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context),
1145 deadline);
Tejun Heoad616ff2006-11-01 18:00:24 +09001146
1147 /* vt8251 needs SError cleared for the port to operate */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001148 ahci_scr_read(ap, SCR_ERROR, &serror);
1149 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heoad616ff2006-11-01 18:00:24 +09001150
Tejun Heo4447d352007-04-17 23:44:08 +09001151 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001152
1153 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1154
1155 /* vt8251 doesn't clear BSY on signature FIS reception,
1156 * request follow-up softreset.
1157 */
1158 return rc ?: -EAGAIN;
1159}
1160
Tejun Heo4bd00f62006-02-11 16:26:02 +09001161static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1162{
Tejun Heo4447d352007-04-17 23:44:08 +09001163 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001164 u32 new_tmp, tmp;
1165
1166 ata_std_postreset(ap, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001167
1168 /* Make sure port's ATAPI bit is set appropriately */
1169 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001170 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001171 new_tmp |= PORT_CMD_ATAPI;
1172 else
1173 new_tmp &= ~PORT_CMD_ATAPI;
1174 if (new_tmp != tmp) {
1175 writel(new_tmp, port_mmio + PORT_CMD);
1176 readl(port_mmio + PORT_CMD); /* flush */
1177 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178}
1179
1180static u8 ahci_check_status(struct ata_port *ap)
1181{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001182 void __iomem *mmio = ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183
1184 return readl(mmio + PORT_TFDATA) & 0xFF;
1185}
1186
Linus Torvalds1da177e2005-04-16 15:20:36 -07001187static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1188{
1189 struct ahci_port_priv *pp = ap->private_data;
1190 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1191
1192 ata_tf_from_fis(d2h_fis, tf);
1193}
1194
Tejun Heo12fad3f2006-05-15 21:03:55 +09001195static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001197 struct scatterlist *sg;
1198 struct ahci_sg *ahci_sg;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001199 unsigned int n_sg = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001200
1201 VPRINTK("ENTER\n");
1202
1203 /*
1204 * Next, the S/G list.
1205 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001206 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001207 ata_for_each_sg(sg, qc) {
1208 dma_addr_t addr = sg_dma_address(sg);
1209 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001211 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1212 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1213 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
Jeff Garzik828d09d2005-11-12 01:27:07 -05001214
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001215 ahci_sg++;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001216 n_sg++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001218
1219 return n_sg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220}
1221
1222static void ahci_qc_prep(struct ata_queued_cmd *qc)
1223{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001224 struct ata_port *ap = qc->ap;
1225 struct ahci_port_priv *pp = ap->private_data;
Tejun Heocc9278e2006-02-10 17:25:47 +09001226 int is_atapi = is_atapi_taskfile(&qc->tf);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001227 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228 u32 opts;
1229 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001230 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001231
1232 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233 * Fill in command table information. First, the header,
1234 * a SATA Register - Host to Device command FIS.
1235 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001236 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1237
Tejun Heo99771262007-07-16 14:29:38 +09001238 ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09001239 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001240 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1241 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04001242 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243
Tejun Heocc9278e2006-02-10 17:25:47 +09001244 n_elem = 0;
1245 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001246 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001247
Tejun Heocc9278e2006-02-10 17:25:47 +09001248 /*
1249 * Fill in command slot information.
1250 */
1251 opts = cmd_fis_len | n_elem << 16;
1252 if (qc->tf.flags & ATA_TFLAG_WRITE)
1253 opts |= AHCI_CMD_WRITE;
1254 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09001255 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001256
Tejun Heo12fad3f2006-05-15 21:03:55 +09001257 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001258}
1259
Tejun Heo78cd52d2006-05-15 20:58:29 +09001260static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261{
Tejun Heo78cd52d2006-05-15 20:58:29 +09001262 struct ahci_port_priv *pp = ap->private_data;
1263 struct ata_eh_info *ehi = &ap->eh_info;
1264 unsigned int err_mask = 0, action = 0;
1265 struct ata_queued_cmd *qc;
1266 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001267
Tejun Heo78cd52d2006-05-15 20:58:29 +09001268 ata_ehi_clear_desc(ehi);
Jeff Garzik9f68a242005-11-15 14:03:47 -05001269
Tejun Heo78cd52d2006-05-15 20:58:29 +09001270 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001271 ahci_scr_read(ap, SCR_ERROR, &serror);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001272 ahci_scr_write(ap, SCR_ERROR, serror);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273
Tejun Heo78cd52d2006-05-15 20:58:29 +09001274 /* analyze @irq_stat */
1275 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276
Tejun Heo41669552006-11-29 11:33:14 +09001277 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1278 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1279 irq_stat &= ~PORT_IRQ_IF_ERR;
1280
Conke Hu55a61602007-03-27 18:33:05 +08001281 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09001282 err_mask |= AC_ERR_DEV;
Conke Hu55a61602007-03-27 18:33:05 +08001283 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1284 serror &= ~SERR_INTERNAL;
1285 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09001286
1287 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1288 err_mask |= AC_ERR_HOST_BUS;
1289 action |= ATA_EH_SOFTRESET;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001290 }
1291
Tejun Heo78cd52d2006-05-15 20:58:29 +09001292 if (irq_stat & PORT_IRQ_IF_ERR) {
1293 err_mask |= AC_ERR_ATA_BUS;
1294 action |= ATA_EH_SOFTRESET;
Tejun Heob64bbc32007-07-16 14:29:39 +09001295 ata_ehi_push_desc(ehi, "interface fatal error");
Tejun Heo78cd52d2006-05-15 20:58:29 +09001296 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001297
Tejun Heo78cd52d2006-05-15 20:58:29 +09001298 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
Tejun Heo42969712006-05-31 18:28:18 +09001299 ata_ehi_hotplugged(ehi);
Tejun Heob64bbc32007-07-16 14:29:39 +09001300 ata_ehi_push_desc(ehi, "%s", irq_stat & PORT_IRQ_CONNECT ?
Tejun Heo78cd52d2006-05-15 20:58:29 +09001301 "connection status changed" : "PHY RDY changed");
1302 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001303
Tejun Heo78cd52d2006-05-15 20:58:29 +09001304 if (irq_stat & PORT_IRQ_UNK_FIS) {
1305 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001306
Tejun Heo78cd52d2006-05-15 20:58:29 +09001307 err_mask |= AC_ERR_HSM;
1308 action |= ATA_EH_SOFTRESET;
Tejun Heob64bbc32007-07-16 14:29:39 +09001309 ata_ehi_push_desc(ehi, "unknown FIS %08x %08x %08x %08x",
Tejun Heo78cd52d2006-05-15 20:58:29 +09001310 unk[0], unk[1], unk[2], unk[3]);
1311 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04001312
Tejun Heo78cd52d2006-05-15 20:58:29 +09001313 /* okay, let's hand over to EH */
1314 ehi->serror |= serror;
1315 ehi->action |= action;
1316
Linus Torvalds1da177e2005-04-16 15:20:36 -07001317 qc = ata_qc_from_tag(ap, ap->active_tag);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001318 if (qc)
1319 qc->err_mask |= err_mask;
1320 else
1321 ehi->err_mask |= err_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322
Tejun Heo78cd52d2006-05-15 20:58:29 +09001323 if (irq_stat & PORT_IRQ_FREEZE)
1324 ata_port_freeze(ap);
1325 else
1326 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001327}
1328
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001329static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330{
Tejun Heo4447d352007-04-17 23:44:08 +09001331 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001332 struct ata_eh_info *ehi = &ap->eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09001333 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001334 u32 status, qc_active;
Tejun Heo0291f952007-01-25 19:16:28 +09001335 int rc, known_irq = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336
1337 status = readl(port_mmio + PORT_IRQ_STAT);
1338 writel(status, port_mmio + PORT_IRQ_STAT);
1339
Tejun Heo78cd52d2006-05-15 20:58:29 +09001340 if (unlikely(status & PORT_IRQ_ERROR)) {
1341 ahci_error_intr(ap, status);
1342 return;
1343 }
1344
Tejun Heo12fad3f2006-05-15 21:03:55 +09001345 if (ap->sactive)
1346 qc_active = readl(port_mmio + PORT_SCR_ACT);
1347 else
1348 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1349
1350 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1351 if (rc > 0)
1352 return;
1353 if (rc < 0) {
1354 ehi->err_mask |= AC_ERR_HSM;
1355 ehi->action |= ATA_EH_SOFTRESET;
1356 ata_port_freeze(ap);
1357 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358 }
1359
Tejun Heo2a3917a2006-05-15 20:58:30 +09001360 /* hmmm... a spurious interupt */
1361
Tejun Heo0291f952007-01-25 19:16:28 +09001362 /* if !NCQ, ignore. No modern ATA device has broken HSM
1363 * implementation for non-NCQ commands.
1364 */
1365 if (!ap->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001366 return;
1367
Tejun Heo0291f952007-01-25 19:16:28 +09001368 if (status & PORT_IRQ_D2H_REG_FIS) {
1369 if (!pp->ncq_saw_d2h)
1370 ata_port_printk(ap, KERN_INFO,
1371 "D2H reg with I during NCQ, "
1372 "this message won't be printed again\n");
1373 pp->ncq_saw_d2h = 1;
1374 known_irq = 1;
1375 }
Tejun Heo2a3917a2006-05-15 20:58:30 +09001376
Tejun Heo0291f952007-01-25 19:16:28 +09001377 if (status & PORT_IRQ_DMAS_FIS) {
1378 if (!pp->ncq_saw_dmas)
1379 ata_port_printk(ap, KERN_INFO,
1380 "DMAS FIS during NCQ, "
1381 "this message won't be printed again\n");
1382 pp->ncq_saw_dmas = 1;
1383 known_irq = 1;
1384 }
1385
Tejun Heoa2bbd0c2007-02-21 16:34:25 +09001386 if (status & PORT_IRQ_SDB_FIS) {
Al Viro04d4f7a2007-02-09 16:39:30 +00001387 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
Tejun Heo0291f952007-01-25 19:16:28 +09001388
Tejun Heoafb2d552007-02-27 13:24:19 +09001389 if (le32_to_cpu(f[1])) {
1390 /* SDB FIS containing spurious completions
1391 * might be dangerous, whine and fail commands
1392 * with HSM violation. EH will turn off NCQ
1393 * after several such failures.
1394 */
1395 ata_ehi_push_desc(ehi,
1396 "spurious completions during NCQ "
1397 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1398 readl(port_mmio + PORT_CMD_ISSUE),
1399 readl(port_mmio + PORT_SCR_ACT),
1400 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1401 ehi->err_mask |= AC_ERR_HSM;
1402 ehi->action |= ATA_EH_SOFTRESET;
1403 ata_port_freeze(ap);
1404 } else {
1405 if (!pp->ncq_saw_sdb)
1406 ata_port_printk(ap, KERN_INFO,
1407 "spurious SDB FIS %08x:%08x during NCQ, "
1408 "this message won't be printed again\n",
1409 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1410 pp->ncq_saw_sdb = 1;
1411 }
Tejun Heo0291f952007-01-25 19:16:28 +09001412 known_irq = 1;
1413 }
1414
1415 if (!known_irq)
Tejun Heo78cd52d2006-05-15 20:58:29 +09001416 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
Tejun Heo0291f952007-01-25 19:16:28 +09001417 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
Tejun Heo12fad3f2006-05-15 21:03:55 +09001418 status, ap->active_tag, ap->sactive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419}
1420
1421static void ahci_irq_clear(struct ata_port *ap)
1422{
1423 /* TODO */
1424}
1425
David Howells7d12e782006-10-05 14:55:46 +01001426static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427{
Jeff Garzikcca39742006-08-24 03:19:22 -04001428 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429 struct ahci_host_priv *hpriv;
1430 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04001431 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432 u32 irq_stat, irq_ack = 0;
1433
1434 VPRINTK("ENTER\n");
1435
Jeff Garzikcca39742006-08-24 03:19:22 -04001436 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001437 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001438
1439 /* sigh. 0xffffffff is a valid return from h/w */
1440 irq_stat = readl(mmio + HOST_IRQ_STAT);
1441 irq_stat &= hpriv->port_map;
1442 if (!irq_stat)
1443 return IRQ_NONE;
1444
Jeff Garzikcca39742006-08-24 03:19:22 -04001445 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446
Jeff Garzikcca39742006-08-24 03:19:22 -04001447 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449
Jeff Garzik67846b32005-10-05 02:58:32 -04001450 if (!(irq_stat & (1 << i)))
1451 continue;
1452
Jeff Garzikcca39742006-08-24 03:19:22 -04001453 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04001454 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001455 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04001456 VPRINTK("port %u\n", i);
1457 } else {
1458 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09001459 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04001460 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05001461 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462 }
Jeff Garzik67846b32005-10-05 02:58:32 -04001463
1464 irq_ack |= (1 << i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001465 }
1466
1467 if (irq_ack) {
1468 writel(irq_ack, mmio + HOST_IRQ_STAT);
1469 handled = 1;
1470 }
1471
Jeff Garzikcca39742006-08-24 03:19:22 -04001472 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001473
1474 VPRINTK("EXIT\n");
1475
1476 return IRQ_RETVAL(handled);
1477}
1478
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09001479static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480{
1481 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001482 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001483
Tejun Heo12fad3f2006-05-15 21:03:55 +09001484 if (qc->tf.protocol == ATA_PROT_NCQ)
1485 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1486 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001487 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1488
1489 return 0;
1490}
1491
Tejun Heo78cd52d2006-05-15 20:58:29 +09001492static void ahci_freeze(struct ata_port *ap)
1493{
Tejun Heo4447d352007-04-17 23:44:08 +09001494 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001495
1496 /* turn IRQ off */
1497 writel(0, port_mmio + PORT_IRQ_MASK);
1498}
1499
1500static void ahci_thaw(struct ata_port *ap)
1501{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001502 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09001503 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001504 u32 tmp;
1505
1506 /* clear IRQ */
1507 tmp = readl(port_mmio + PORT_IRQ_STAT);
1508 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09001509 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001510
1511 /* turn IRQ back on */
1512 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1513}
1514
1515static void ahci_error_handler(struct ata_port *ap)
1516{
Tejun Heob51e9e52006-06-29 01:29:30 +09001517 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09001518 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001519 ahci_stop_engine(ap);
1520 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001521 }
1522
1523 /* perform recovery */
Tejun Heo4aeb0e32006-11-01 17:58:33 +09001524 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
Tejun Heof5914a42006-05-31 18:27:48 +09001525 ahci_postreset);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001526}
1527
Tejun Heoad616ff2006-11-01 18:00:24 +09001528static void ahci_vt8251_error_handler(struct ata_port *ap)
1529{
Tejun Heoad616ff2006-11-01 18:00:24 +09001530 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1531 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001532 ahci_stop_engine(ap);
1533 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001534 }
1535
1536 /* perform recovery */
1537 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1538 ahci_postreset);
1539}
1540
Tejun Heo78cd52d2006-05-15 20:58:29 +09001541static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1542{
1543 struct ata_port *ap = qc->ap;
1544
Tejun Heod2e75df2007-07-16 14:29:39 +09001545 /* make DMA engine forget about the failed command */
1546 if (qc->flags & ATA_QCFLAG_FAILED)
1547 ahci_kick_engine(ap, 1);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001548}
1549
Alexey Dobriyan028a2592007-07-17 23:48:48 +04001550static int ahci_port_resume(struct ata_port *ap)
1551{
1552 ahci_power_up(ap);
1553 ahci_start_port(ap);
1554
1555 return 0;
1556}
1557
Tejun Heo438ac6d2007-03-02 17:31:26 +09001558#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09001559static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1560{
Tejun Heoc1332872006-07-26 15:59:26 +09001561 const char *emsg = NULL;
1562 int rc;
1563
Tejun Heo4447d352007-04-17 23:44:08 +09001564 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09001565 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09001566 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09001567 else {
Tejun Heoc1332872006-07-26 15:59:26 +09001568 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001569 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09001570 }
1571
1572 return rc;
1573}
1574
Tejun Heoc1332872006-07-26 15:59:26 +09001575static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1576{
Jeff Garzikcca39742006-08-24 03:19:22 -04001577 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001578 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09001579 u32 ctl;
1580
1581 if (mesg.event == PM_EVENT_SUSPEND) {
1582 /* AHCI spec rev1.1 section 8.3.3:
1583 * Software must disable interrupts prior to requesting a
1584 * transition of the HBA to D3 state.
1585 */
1586 ctl = readl(mmio + HOST_CTL);
1587 ctl &= ~HOST_IRQ_EN;
1588 writel(ctl, mmio + HOST_CTL);
1589 readl(mmio + HOST_CTL); /* flush */
1590 }
1591
1592 return ata_pci_device_suspend(pdev, mesg);
1593}
1594
1595static int ahci_pci_device_resume(struct pci_dev *pdev)
1596{
Jeff Garzikcca39742006-08-24 03:19:22 -04001597 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09001598 int rc;
1599
Tejun Heo553c4aa2006-12-26 19:39:50 +09001600 rc = ata_pci_device_do_resume(pdev);
1601 if (rc)
1602 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09001603
1604 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09001605 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001606 if (rc)
1607 return rc;
1608
Tejun Heo4447d352007-04-17 23:44:08 +09001609 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001610 }
1611
Jeff Garzikcca39742006-08-24 03:19:22 -04001612 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001613
1614 return 0;
1615}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001616#endif
Tejun Heoc1332872006-07-26 15:59:26 +09001617
Tejun Heo254950c2006-07-26 15:59:25 +09001618static int ahci_port_start(struct ata_port *ap)
1619{
Jeff Garzikcca39742006-08-24 03:19:22 -04001620 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09001621 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09001622 void *mem;
1623 dma_addr_t mem_dma;
1624 int rc;
1625
Tejun Heo24dc5f32007-01-20 16:00:28 +09001626 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09001627 if (!pp)
1628 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09001629
1630 rc = ata_pad_alloc(ap, dev);
Tejun Heo24dc5f32007-01-20 16:00:28 +09001631 if (rc)
Tejun Heo254950c2006-07-26 15:59:25 +09001632 return rc;
Tejun Heo254950c2006-07-26 15:59:25 +09001633
Tejun Heo24dc5f32007-01-20 16:00:28 +09001634 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1635 GFP_KERNEL);
1636 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09001637 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09001638 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1639
1640 /*
1641 * First item in chunk of DMA memory: 32-slot command table,
1642 * 32 bytes each in size
1643 */
1644 pp->cmd_slot = mem;
1645 pp->cmd_slot_dma = mem_dma;
1646
1647 mem += AHCI_CMD_SLOT_SZ;
1648 mem_dma += AHCI_CMD_SLOT_SZ;
1649
1650 /*
1651 * Second item: Received-FIS area
1652 */
1653 pp->rx_fis = mem;
1654 pp->rx_fis_dma = mem_dma;
1655
1656 mem += AHCI_RX_FIS_SZ;
1657 mem_dma += AHCI_RX_FIS_SZ;
1658
1659 /*
1660 * Third item: data area for storing a single command
1661 * and its scatter-gather table
1662 */
1663 pp->cmd_tbl = mem;
1664 pp->cmd_tbl_dma = mem_dma;
1665
1666 ap->private_data = pp;
1667
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001668 /* engage engines, captain */
1669 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09001670}
1671
1672static void ahci_port_stop(struct ata_port *ap)
1673{
Tejun Heo0be0aa92006-07-26 15:59:26 +09001674 const char *emsg = NULL;
1675 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09001676
Tejun Heo0be0aa92006-07-26 15:59:26 +09001677 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09001678 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001679 if (rc)
1680 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09001681}
1682
Tejun Heo4447d352007-04-17 23:44:08 +09001683static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001685 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001686
Linus Torvalds1da177e2005-04-16 15:20:36 -07001687 if (using_dac &&
1688 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1689 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1690 if (rc) {
1691 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1692 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001693 dev_printk(KERN_ERR, &pdev->dev,
1694 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001695 return rc;
1696 }
1697 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001698 } else {
1699 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1700 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001701 dev_printk(KERN_ERR, &pdev->dev,
1702 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001703 return rc;
1704 }
1705 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1706 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05001707 dev_printk(KERN_ERR, &pdev->dev,
1708 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001709 return rc;
1710 }
1711 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001712 return 0;
1713}
1714
Tejun Heo4447d352007-04-17 23:44:08 +09001715static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716{
Tejun Heo4447d352007-04-17 23:44:08 +09001717 struct ahci_host_priv *hpriv = host->private_data;
1718 struct pci_dev *pdev = to_pci_dev(host->dev);
1719 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001720 u32 vers, cap, impl, speed;
1721 const char *speed_s;
1722 u16 cc;
1723 const char *scc_s;
1724
1725 vers = readl(mmio + HOST_VERSION);
1726 cap = hpriv->cap;
1727 impl = hpriv->port_map;
1728
1729 speed = (cap >> 20) & 0xf;
1730 if (speed == 1)
1731 speed_s = "1.5";
1732 else if (speed == 2)
1733 speed_s = "3";
1734 else
1735 speed_s = "?";
1736
1737 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05001738 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001739 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05001740 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001741 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05001742 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001743 scc_s = "RAID";
1744 else
1745 scc_s = "unknown";
1746
Jeff Garzika9524a72005-10-30 14:39:11 -05001747 dev_printk(KERN_INFO, &pdev->dev,
1748 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001749 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1750 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001751
1752 (vers >> 24) & 0xff,
1753 (vers >> 16) & 0xff,
1754 (vers >> 8) & 0xff,
1755 vers & 0xff,
1756
1757 ((cap >> 8) & 0x1f) + 1,
1758 (cap & 0x1f) + 1,
1759 speed_s,
1760 impl,
1761 scc_s);
1762
Jeff Garzika9524a72005-10-30 14:39:11 -05001763 dev_printk(KERN_INFO, &pdev->dev,
1764 "flags: "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001765 "%s%s%s%s%s%s"
1766 "%s%s%s%s%s%s%s\n"
1767 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001768
1769 cap & (1 << 31) ? "64bit " : "",
1770 cap & (1 << 30) ? "ncq " : "",
1771 cap & (1 << 28) ? "ilck " : "",
1772 cap & (1 << 27) ? "stag " : "",
1773 cap & (1 << 26) ? "pm " : "",
1774 cap & (1 << 25) ? "led " : "",
1775
1776 cap & (1 << 24) ? "clo " : "",
1777 cap & (1 << 19) ? "nz " : "",
1778 cap & (1 << 18) ? "only " : "",
1779 cap & (1 << 17) ? "pmp " : "",
1780 cap & (1 << 15) ? "pio " : "",
1781 cap & (1 << 14) ? "slum " : "",
1782 cap & (1 << 13) ? "part " : ""
1783 );
1784}
1785
Tejun Heo24dc5f32007-01-20 16:00:28 +09001786static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787{
1788 static int printed_version;
Tejun Heo4447d352007-04-17 23:44:08 +09001789 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1790 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001791 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001792 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001793 struct ata_host *host;
1794 int i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795
1796 VPRINTK("ENTER\n");
1797
Tejun Heo12fad3f2006-05-15 21:03:55 +09001798 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1799
Linus Torvalds1da177e2005-04-16 15:20:36 -07001800 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001801 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001802
Tejun Heo4447d352007-04-17 23:44:08 +09001803 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001804 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001805 if (rc)
1806 return rc;
1807
Tejun Heo0d5ff562007-02-01 15:06:36 +09001808 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1809 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001810 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001811 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001812 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001813
Jeff Garzikcd70c262007-07-08 02:29:42 -04001814 if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
Jeff Garzik907f4672005-05-12 15:03:42 -04001815 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001816
Tejun Heo24dc5f32007-01-20 16:00:28 +09001817 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1818 if (!hpriv)
1819 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001820
Tejun Heo4447d352007-04-17 23:44:08 +09001821 /* save initial config */
1822 ahci_save_initial_config(pdev, &pi, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001823
Tejun Heo4447d352007-04-17 23:44:08 +09001824 /* prepare host */
1825 if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ))
1826 pi.flags |= ATA_FLAG_NCQ;
1827
1828 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1829 if (!host)
1830 return -ENOMEM;
1831 host->iomap = pcim_iomap_table(pdev);
1832 host->private_data = hpriv;
1833
1834 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04001835 struct ata_port *ap = host->ports[i];
1836 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09001837
Jeff Garzikdab632e2007-05-28 08:33:01 -04001838 /* standard SATA port setup */
1839 if (hpriv->port_map & (1 << i)) {
Tejun Heo4447d352007-04-17 23:44:08 +09001840 ap->ioaddr.cmd_addr = port_mmio;
1841 ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
Jeff Garzikdab632e2007-05-28 08:33:01 -04001842 }
1843
1844 /* disabled/not-implemented port */
1845 else
1846 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09001847 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001848
1849 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09001850 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001851 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001852 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001853
Tejun Heo4447d352007-04-17 23:44:08 +09001854 rc = ahci_reset_controller(host);
1855 if (rc)
1856 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001857
Tejun Heo4447d352007-04-17 23:44:08 +09001858 ahci_init_controller(host);
1859 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001860
Tejun Heo4447d352007-04-17 23:44:08 +09001861 pci_set_master(pdev);
1862 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1863 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04001864}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001865
1866static int __init ahci_init(void)
1867{
Pavel Roskinb7887192006-08-10 18:13:18 +09001868 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001869}
1870
Linus Torvalds1da177e2005-04-16 15:20:36 -07001871static void __exit ahci_exit(void)
1872{
1873 pci_unregister_driver(&ahci_pci_driver);
1874}
1875
1876
1877MODULE_AUTHOR("Jeff Garzik");
1878MODULE_DESCRIPTION("AHCI SATA low-level driver");
1879MODULE_LICENSE("GPL");
1880MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001881MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001882
1883module_init(ahci_init);
1884module_exit(ahci_exit);