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Tomi Valkeinen559d6702009-11-03 11:23:50 +02001/*
Tomi Valkeinen559d6702009-11-03 11:23:50 +02002 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
Tomi Valkeinena0b38cc2011-05-11 14:05:07 +030018#ifndef __OMAP_OMAPDSS_H
19#define __OMAP_OMAPDSS_H
Tomi Valkeinen559d6702009-11-03 11:23:50 +020020
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
Tomi Valkeinen348be692012-11-07 18:17:35 +020024#include <linux/interrupt.h>
Tomi Valkeinen559d6702009-11-03 11:23:50 +020025
Tomi Valkeinen6fcd4852013-05-10 13:02:32 +030026#include <video/videomode.h>
27
Tomi Valkeinen559d6702009-11-03 11:23:50 +020028#define DISPC_IRQ_FRAMEDONE (1 << 0)
29#define DISPC_IRQ_VSYNC (1 << 1)
30#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
31#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
32#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
33#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
34#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
35#define DISPC_IRQ_GFX_END_WIN (1 << 7)
36#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
37#define DISPC_IRQ_OCP_ERR (1 << 9)
38#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
39#define DISPC_IRQ_VID1_END_WIN (1 << 11)
40#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
41#define DISPC_IRQ_VID2_END_WIN (1 << 13)
42#define DISPC_IRQ_SYNC_LOST (1 << 14)
43#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
44#define DISPC_IRQ_WAKEUP (1 << 16)
Sumit Semwal2a205f32010-12-02 11:27:12 +000045#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
46#define DISPC_IRQ_VSYNC2 (1 << 18)
Archit Tanejab8c095b2011-09-13 18:20:33 +053047#define DISPC_IRQ_VID3_END_WIN (1 << 19)
48#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
Sumit Semwal2a205f32010-12-02 11:27:12 +000049#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
50#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
Tomi Valkeinen7f6f3c42011-08-31 13:39:03 +030051#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
52#define DISPC_IRQ_FRAMEDONETV (1 << 24)
53#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
Chandrabhanu Mahapatra14d33d32012-08-27 14:23:19 +053054#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
55#define DISPC_IRQ_VSYNC3 (1 << 28)
56#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
57#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
Tomi Valkeinen559d6702009-11-03 11:23:50 +020058
59struct omap_dss_device;
60struct omap_overlay_manager;
Tomi Valkeinena97a9632012-10-24 13:52:40 +030061struct dss_lcd_mgr_config;
Ricardo Neri9c0b8422012-03-06 18:20:37 -060062struct snd_aes_iec958;
63struct snd_cea_861_aud_if;
Tomi Valkeinen8c071ca2014-06-18 12:04:29 +030064struct hdmi_avi_infoframe;
Tomi Valkeinen559d6702009-11-03 11:23:50 +020065
66enum omap_display_type {
67 OMAP_DISPLAY_TYPE_NONE = 0,
68 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
69 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
70 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
71 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
72 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
Mythri P Kb1196012011-03-08 17:15:54 +053073 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
Tomi Valkeinenbc24b8b2013-05-13 13:40:33 +030074 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
Tomi Valkeinen559d6702009-11-03 11:23:50 +020075};
76
77enum omap_plane {
78 OMAP_DSS_GFX = 0,
79 OMAP_DSS_VIDEO1 = 1,
Archit Tanejab8c095b2011-09-13 18:20:33 +053080 OMAP_DSS_VIDEO2 = 2,
81 OMAP_DSS_VIDEO3 = 3,
Tomi Valkeinen66a0f9e2012-08-22 16:57:02 +030082 OMAP_DSS_WB = 4,
Tomi Valkeinen559d6702009-11-03 11:23:50 +020083};
84
85enum omap_channel {
86 OMAP_DSS_CHANNEL_LCD = 0,
87 OMAP_DSS_CHANNEL_DIGIT = 1,
Sumit Semwal8613b002010-12-02 11:27:09 +000088 OMAP_DSS_CHANNEL_LCD2 = 2,
Chandrabhanu Mahapatraff6331e2012-06-19 15:08:16 +053089 OMAP_DSS_CHANNEL_LCD3 = 3,
Tomi Valkeinen559d6702009-11-03 11:23:50 +020090};
91
92enum omap_color_mode {
93 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
94 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
95 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
96 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
97 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
98 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
99 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
100 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
101 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
102 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
103 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
104 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
105 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
106 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
Amber Jainf20e4222011-05-19 19:47:50 +0530107 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
108 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
109 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
110 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
111 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200112};
113
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200114enum omap_dss_load_mode {
115 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
116 OMAP_DSS_LOAD_CLUT_ONLY = 1,
117 OMAP_DSS_LOAD_FRAME_ONLY = 2,
118 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
119};
120
121enum omap_dss_trans_key_type {
122 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
123 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
124};
125
126enum omap_rfbi_te_mode {
127 OMAP_DSS_RFBI_TE_MODE_1 = 1,
128 OMAP_DSS_RFBI_TE_MODE_2 = 2,
129};
130
Archit Tanejaa8d5e412012-06-25 12:26:38 +0530131enum omap_dss_signal_level {
132 OMAPDSS_SIG_ACTIVE_HIGH = 0,
133 OMAPDSS_SIG_ACTIVE_LOW = 1,
134};
135
136enum omap_dss_signal_edge {
137 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
138 OMAPDSS_DRIVE_SIG_RISING_EDGE,
139 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
140};
141
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200142enum omap_dss_venc_type {
143 OMAP_DSS_VENC_TYPE_COMPOSITE,
144 OMAP_DSS_VENC_TYPE_SVIDEO,
145};
146
Archit Tanejaa3b3cc22011-09-08 18:42:16 +0530147enum omap_dss_dsi_pixel_format {
148 OMAP_DSS_DSI_FMT_RGB888,
149 OMAP_DSS_DSI_FMT_RGB666,
150 OMAP_DSS_DSI_FMT_RGB666_PACKED,
151 OMAP_DSS_DSI_FMT_RGB565,
152};
153
Archit Taneja7e951ee2011-07-22 12:45:04 +0530154enum omap_dss_dsi_mode {
155 OMAP_DSS_DSI_CMD_MODE = 0,
156 OMAP_DSS_DSI_VIDEO_MODE,
157};
158
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200159enum omap_display_caps {
160 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
161 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
162};
163
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200164enum omap_dss_display_state {
165 OMAP_DSS_DISPLAY_DISABLED = 0,
166 OMAP_DSS_DISPLAY_ACTIVE,
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200167};
168
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300169struct omap_dss_audio {
170 struct snd_aes_iec958 *iec;
171 struct snd_cea_861_aud_if *cea;
172};
173
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200174enum omap_dss_rotation_type {
Chandrabhanu Mahapatra65e006f2012-05-11 19:19:55 +0530175 OMAP_DSS_ROT_DMA = 1 << 0,
176 OMAP_DSS_ROT_VRFB = 1 << 1,
177 OMAP_DSS_ROT_TILER = 1 << 2,
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200178};
179
180/* clockwise rotation angle */
181enum omap_dss_rotation_angle {
182 OMAP_DSS_ROT_0 = 0,
183 OMAP_DSS_ROT_90 = 1,
184 OMAP_DSS_ROT_180 = 2,
185 OMAP_DSS_ROT_270 = 3,
186};
187
188enum omap_overlay_caps {
189 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
Tomi Valkeinenf6dc8152011-08-15 15:18:20 +0300190 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
191 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
Archit Taneja11354dd2011-09-26 11:47:29 +0530192 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
Archit Tanejad79db852012-09-22 12:30:17 +0530193 OMAP_DSS_OVL_CAP_POS = 1 << 4,
194 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200195};
196
197enum omap_overlay_manager_caps {
Tomi Valkeinen4a9e78a2011-08-15 11:22:21 +0300198 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200199};
200
Archit Taneja89a35e52011-04-12 13:52:23 +0530201enum omap_dss_clk_source {
202 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
203 * OMAP4: DSS_FCLK */
204 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
205 * OMAP4: PLL1_CLK1 */
206 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
207 * OMAP4: PLL1_CLK2 */
Archit Taneja5a8b5722011-05-12 17:26:29 +0530208 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
209 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
Archit Taneja89a35e52011-04-12 13:52:23 +0530210};
211
Mythri P K9a901682012-01-02 14:02:38 +0530212enum omap_hdmi_flags {
213 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
214};
215
Archit Taneja484dc402012-09-07 17:38:00 +0530216enum omap_dss_output_id {
217 OMAP_DSS_OUTPUT_DPI = 1 << 0,
218 OMAP_DSS_OUTPUT_DBI = 1 << 1,
219 OMAP_DSS_OUTPUT_SDI = 1 << 2,
220 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
221 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
222 OMAP_DSS_OUTPUT_VENC = 1 << 5,
223 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
224};
225
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200226/* RFBI */
227
228struct rfbi_timings {
229 int cs_on_time;
230 int cs_off_time;
231 int we_on_time;
232 int we_off_time;
233 int re_on_time;
234 int re_off_time;
235 int we_cycle_time;
236 int re_cycle_time;
237 int cs_pulse_width;
238 int access_time;
239
240 int clk_div;
241
242 u32 tim[5]; /* set by rfbi_convert_timings() */
243
244 int converted;
245};
246
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200247/* DSI */
Archit Taneja8af6ff02011-09-05 16:48:27 +0530248
Tomi Valkeinen478d7df2013-03-05 16:29:36 +0200249enum omap_dss_dsi_trans_mode {
250 /* Sync Pulses: both sync start and end packets sent */
251 OMAP_DSS_DSI_PULSE_MODE,
252 /* Sync Events: only sync start packets sent */
253 OMAP_DSS_DSI_EVENT_MODE,
254 /* Burst: only sync start packets sent, pixels are time compressed */
255 OMAP_DSS_DSI_BURST_MODE,
256};
257
Archit Taneja6b8493752012-08-13 22:12:24 +0530258struct omap_dss_dsi_videomode_timings {
Tomi Valkeinenf1e00012013-03-05 17:21:35 +0200259 unsigned long hsclk;
260
261 unsigned ndl;
262 unsigned bitspp;
263
264 /* pixels */
265 u16 hact;
266 /* lines */
267 u16 vact;
268
Archit Taneja8af6ff02011-09-05 16:48:27 +0530269 /* DSI video mode blanking data */
270 /* Unit: byte clock cycles */
Tomi Valkeinenf1e00012013-03-05 17:21:35 +0200271 u16 hss;
Archit Taneja8af6ff02011-09-05 16:48:27 +0530272 u16 hsa;
Tomi Valkeinenf1e00012013-03-05 17:21:35 +0200273 u16 hse;
Archit Taneja8af6ff02011-09-05 16:48:27 +0530274 u16 hfp;
275 u16 hbp;
276 /* Unit: line clocks */
277 u16 vsa;
278 u16 vfp;
279 u16 vbp;
280
281 /* DSI blanking modes */
282 int blanking_mode;
283 int hsa_blanking_mode;
284 int hbp_blanking_mode;
285 int hfp_blanking_mode;
286
Tomi Valkeinen478d7df2013-03-05 16:29:36 +0200287 enum omap_dss_dsi_trans_mode trans_mode;
Archit Taneja8af6ff02011-09-05 16:48:27 +0530288
289 bool ddr_clk_always_on;
290 int window_sync;
291};
292
Tomi Valkeinen777f05c2013-03-06 11:10:29 +0200293struct omap_dss_dsi_config {
294 enum omap_dss_dsi_mode mode;
295 enum omap_dss_dsi_pixel_format pixel_format;
296 const struct omap_video_timings *timings;
Tomi Valkeinen777f05c2013-03-06 11:10:29 +0200297
Tomi Valkeinenf1e00012013-03-05 17:21:35 +0200298 unsigned long hs_clk_min, hs_clk_max;
299 unsigned long lp_clk_min, lp_clk_max;
300
301 bool ddr_clk_always_on;
302 enum omap_dss_dsi_trans_mode trans_mode;
Tomi Valkeinen777f05c2013-03-06 11:10:29 +0200303};
304
Tomi Valkeinenacd18af2012-09-28 12:42:28 +0300305enum omapdss_version {
306 OMAPDSS_VER_UNKNOWN = 0,
307 OMAPDSS_VER_OMAP24xx,
308 OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
309 OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
310 OMAPDSS_VER_OMAP3630,
311 OMAPDSS_VER_AM35xx,
312 OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
313 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
314 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
315 OMAPDSS_VER_OMAP5,
Sathya Prakash M Rd6279d42014-03-24 16:31:51 +0530316 OMAPDSS_VER_AM43xx,
Tomi Valkeinenacd18af2012-09-28 12:42:28 +0300317};
318
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200319/* Board specific data */
320struct omap_dss_board_info {
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200321 int num_devices;
322 struct omap_dss_device **devices;
323 struct omap_dss_device *default_device;
Tomi Valkeinen0a200122012-11-16 14:59:56 +0200324 const char *default_display_name;
Tomi Valkeinen5bc416c2011-06-15 15:21:12 +0300325 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
326 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
Tomi Valkeinen62c1dcf2012-03-08 12:37:58 +0200327 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
Tomi Valkeinenacd18af2012-09-28 12:42:28 +0300328 enum omapdss_version version;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200329};
330
Sumit Semwalb7ee79a2011-01-24 06:21:54 +0000331/* Init with the board info */
332extern int omap_display_init(struct omap_dss_board_info *board_data);
Mythri P Kee9dfd82012-01-02 14:02:37 +0530333/* HDMI mux init*/
Mythri P K9a901682012-01-02 14:02:38 +0530334extern int omap_hdmi_init(enum omap_hdmi_flags flags);
Sumit Semwalb7ee79a2011-01-24 06:21:54 +0000335
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200336struct omap_video_timings {
337 /* Unit: pixels */
338 u16 x_res;
339 /* Unit: pixels */
340 u16 y_res;
Tomi Valkeinend8d789412013-04-10 14:12:14 +0300341 /* Unit: Hz */
342 u32 pixelclock;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200343 /* Unit: pixel clocks */
344 u16 hsw; /* Horizontal synchronization pulse width */
345 /* Unit: pixel clocks */
346 u16 hfp; /* Horizontal front porch */
347 /* Unit: pixel clocks */
348 u16 hbp; /* Horizontal back porch */
349 /* Unit: line clocks */
350 u16 vsw; /* Vertical synchronization pulse width */
351 /* Unit: line clocks */
352 u16 vfp; /* Vertical front porch */
353 /* Unit: line clocks */
354 u16 vbp; /* Vertical back porch */
Archit Tanejaa8d5e412012-06-25 12:26:38 +0530355
356 /* Vsync logic level */
357 enum omap_dss_signal_level vsync_level;
358 /* Hsync logic level */
359 enum omap_dss_signal_level hsync_level;
Archit Taneja23c8f882012-06-28 11:15:51 +0530360 /* Interlaced or Progressive timings */
361 bool interlace;
Archit Tanejaa8d5e412012-06-25 12:26:38 +0530362 /* Pixel clock edge to drive LCD data */
363 enum omap_dss_signal_edge data_pclk_edge;
364 /* Data enable logic level */
365 enum omap_dss_signal_level de_level;
366 /* Pixel clock edges to drive HSYNC and VSYNC signals */
367 enum omap_dss_signal_edge sync_pclk_edge;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200368};
369
370#ifdef CONFIG_OMAP2_DSS_VENC
371/* Hardcoded timings for tv modes. Venc only uses these to
372 * identify the mode, and does not actually use the configs
373 * itself. However, the configs should be something that
374 * a normal monitor can also show */
Tobias Klauser5a1819e2010-05-20 17:12:52 +0200375extern const struct omap_video_timings omap_dss_pal_timings;
376extern const struct omap_video_timings omap_dss_ntsc_timings;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200377#endif
378
Tomi Valkeinen3c07cae2011-06-21 09:34:30 +0300379struct omap_dss_cpr_coefs {
380 s16 rr, rg, rb;
381 s16 gr, gg, gb;
382 s16 br, bg, bb;
383};
384
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200385struct omap_overlay_info {
Arnd Bergmann24f13a62014-04-24 13:28:18 +0100386 dma_addr_t paddr;
387 dma_addr_t p_uv_addr; /* for NV12 format */
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200388 u16 screen_width;
389 u16 width;
390 u16 height;
391 enum omap_color_mode color_mode;
392 u8 rotation;
393 enum omap_dss_rotation_type rotation_type;
394 bool mirror;
395
396 u16 pos_x;
397 u16 pos_y;
398 u16 out_width; /* if 0, out_width == width */
399 u16 out_height; /* if 0, out_height == height */
400 u8 global_alpha;
Rajkumar Nfd28a392010-11-04 12:28:42 +0100401 u8 pre_mult_alpha;
Archit Taneja54128702011-09-08 11:29:17 +0530402 u8 zorder;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200403};
404
405struct omap_overlay {
406 struct kobject kobj;
407 struct list_head list;
408
409 /* static fields */
410 const char *name;
Tomi Valkeinen4a9e78a2011-08-15 11:22:21 +0300411 enum omap_plane id;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200412 enum omap_color_mode supported_modes;
413 enum omap_overlay_caps caps;
414
415 /* dynamic fields */
416 struct omap_overlay_manager *manager;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200417
Tomi Valkeinen9d11c322011-11-18 12:38:38 +0200418 /*
419 * The following functions do not block:
420 *
421 * is_enabled
422 * set_overlay_info
423 * get_overlay_info
424 *
425 * The rest of the functions may block and cannot be called from
426 * interrupt context
427 */
428
Tomi Valkeinenaaa874a2011-11-15 16:37:53 +0200429 int (*enable)(struct omap_overlay *ovl);
430 int (*disable)(struct omap_overlay *ovl);
431 bool (*is_enabled)(struct omap_overlay *ovl);
432
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200433 int (*set_manager)(struct omap_overlay *ovl,
434 struct omap_overlay_manager *mgr);
435 int (*unset_manager)(struct omap_overlay *ovl);
436
437 int (*set_overlay_info)(struct omap_overlay *ovl,
438 struct omap_overlay_info *info);
439 void (*get_overlay_info)(struct omap_overlay *ovl,
440 struct omap_overlay_info *info);
441
442 int (*wait_for_go)(struct omap_overlay *ovl);
Archit Taneja794bc4e2012-09-07 17:44:51 +0530443
444 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200445};
446
447struct omap_overlay_manager_info {
448 u32 default_color;
449
450 enum omap_dss_trans_key_type trans_key_type;
451 u32 trans_key;
452 bool trans_enabled;
453
Archit Taneja11354dd2011-09-26 11:47:29 +0530454 bool partial_alpha_enabled;
Tomi Valkeinen3c07cae2011-06-21 09:34:30 +0300455
456 bool cpr_enable;
457 struct omap_dss_cpr_coefs cpr_coefs;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200458};
459
460struct omap_overlay_manager {
461 struct kobject kobj;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200462
463 /* static fields */
464 const char *name;
Tomi Valkeinen4a9e78a2011-08-15 11:22:21 +0300465 enum omap_channel id;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200466 enum omap_overlay_manager_caps caps;
Tomi Valkeinen07e327c2011-11-05 10:59:59 +0200467 struct list_head overlays;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200468 enum omap_display_type supported_displays;
Archit Taneja97f01b32012-09-26 16:42:39 +0530469 enum omap_dss_output_id supported_outputs;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200470
471 /* dynamic fields */
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300472 struct omap_dss_device *output;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200473
Tomi Valkeinen9d11c322011-11-18 12:38:38 +0200474 /*
475 * The following functions do not block:
476 *
477 * set_manager_info
478 * get_manager_info
479 * apply
480 *
481 * The rest of the functions may block and cannot be called from
482 * interrupt context
483 */
484
Archit Taneja97f01b32012-09-26 16:42:39 +0530485 int (*set_output)(struct omap_overlay_manager *mgr,
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300486 struct omap_dss_device *output);
Archit Taneja97f01b32012-09-26 16:42:39 +0530487 int (*unset_output)(struct omap_overlay_manager *mgr);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200488
489 int (*set_manager_info)(struct omap_overlay_manager *mgr,
490 struct omap_overlay_manager_info *info);
491 void (*get_manager_info)(struct omap_overlay_manager *mgr,
492 struct omap_overlay_manager_info *info);
493
494 int (*apply)(struct omap_overlay_manager *mgr);
495 int (*wait_for_go)(struct omap_overlay_manager *mgr);
Tomi Valkeinen3f71cbe2010-01-08 17:06:04 +0200496 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
Archit Taneja794bc4e2012-09-07 17:44:51 +0530497
498 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200499};
500
Tomi Valkeinene4a9e942012-03-28 15:58:56 +0300501/* 22 pins means 1 clk lane and 10 data lanes */
502#define OMAP_DSS_MAX_DSI_PINS 22
503
504struct omap_dsi_pin_config {
505 int num_pins;
506 /*
507 * pin numbers in the following order:
508 * clk+, clk-
509 * data1+, data1-
510 * data2+, data2-
511 * ...
512 */
513 int pins[OMAP_DSS_MAX_DSI_PINS];
514};
515
Archit Taneja749feff2012-08-31 12:32:52 +0530516struct omap_dss_writeback_info {
517 u32 paddr;
518 u32 p_uv_addr;
519 u16 buf_width;
520 u16 width;
521 u16 height;
522 enum omap_color_mode color_mode;
523 u8 rotation;
524 enum omap_dss_rotation_type rotation_type;
525 bool mirror;
526 u8 pre_mult_alpha;
527};
528
Tomi Valkeinen0b24edb2013-05-24 13:18:52 +0300529struct omapdss_dpi_ops {
530 int (*connect)(struct omap_dss_device *dssdev,
531 struct omap_dss_device *dst);
532 void (*disconnect)(struct omap_dss_device *dssdev,
533 struct omap_dss_device *dst);
534
535 int (*enable)(struct omap_dss_device *dssdev);
536 void (*disable)(struct omap_dss_device *dssdev);
537
538 int (*check_timings)(struct omap_dss_device *dssdev,
539 struct omap_video_timings *timings);
540 void (*set_timings)(struct omap_dss_device *dssdev,
541 struct omap_video_timings *timings);
542 void (*get_timings)(struct omap_dss_device *dssdev,
543 struct omap_video_timings *timings);
544
545 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
546};
547
Tomi Valkeinenb1082df2013-05-24 13:19:14 +0300548struct omapdss_sdi_ops {
549 int (*connect)(struct omap_dss_device *dssdev,
550 struct omap_dss_device *dst);
551 void (*disconnect)(struct omap_dss_device *dssdev,
552 struct omap_dss_device *dst);
553
554 int (*enable)(struct omap_dss_device *dssdev);
555 void (*disable)(struct omap_dss_device *dssdev);
556
557 int (*check_timings)(struct omap_dss_device *dssdev,
558 struct omap_video_timings *timings);
559 void (*set_timings)(struct omap_dss_device *dssdev,
560 struct omap_video_timings *timings);
561 void (*get_timings)(struct omap_dss_device *dssdev,
562 struct omap_video_timings *timings);
563
564 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
565};
566
Tomi Valkeinen7700c2d2013-05-24 13:19:30 +0300567struct omapdss_dvi_ops {
568 int (*connect)(struct omap_dss_device *dssdev,
569 struct omap_dss_device *dst);
570 void (*disconnect)(struct omap_dss_device *dssdev,
571 struct omap_dss_device *dst);
572
573 int (*enable)(struct omap_dss_device *dssdev);
574 void (*disable)(struct omap_dss_device *dssdev);
575
576 int (*check_timings)(struct omap_dss_device *dssdev,
577 struct omap_video_timings *timings);
578 void (*set_timings)(struct omap_dss_device *dssdev,
579 struct omap_video_timings *timings);
580 void (*get_timings)(struct omap_dss_device *dssdev,
581 struct omap_video_timings *timings);
582};
583
Tomi Valkeinenfb8efa42013-05-24 13:19:50 +0300584struct omapdss_atv_ops {
585 int (*connect)(struct omap_dss_device *dssdev,
586 struct omap_dss_device *dst);
587 void (*disconnect)(struct omap_dss_device *dssdev,
588 struct omap_dss_device *dst);
589
590 int (*enable)(struct omap_dss_device *dssdev);
591 void (*disable)(struct omap_dss_device *dssdev);
592
593 int (*check_timings)(struct omap_dss_device *dssdev,
594 struct omap_video_timings *timings);
595 void (*set_timings)(struct omap_dss_device *dssdev,
596 struct omap_video_timings *timings);
597 void (*get_timings)(struct omap_dss_device *dssdev,
598 struct omap_video_timings *timings);
599
600 void (*set_type)(struct omap_dss_device *dssdev,
601 enum omap_dss_venc_type type);
602 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
603 bool invert_polarity);
604
605 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
606 u32 (*get_wss)(struct omap_dss_device *dssdev);
607};
608
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300609struct omapdss_hdmi_ops {
610 int (*connect)(struct omap_dss_device *dssdev,
611 struct omap_dss_device *dst);
612 void (*disconnect)(struct omap_dss_device *dssdev,
613 struct omap_dss_device *dst);
614
615 int (*enable)(struct omap_dss_device *dssdev);
616 void (*disable)(struct omap_dss_device *dssdev);
617
618 int (*check_timings)(struct omap_dss_device *dssdev,
619 struct omap_video_timings *timings);
620 void (*set_timings)(struct omap_dss_device *dssdev,
621 struct omap_video_timings *timings);
622 void (*get_timings)(struct omap_dss_device *dssdev,
623 struct omap_video_timings *timings);
624
625 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
626 bool (*detect)(struct omap_dss_device *dssdev);
627
Tomi Valkeinen8c071ca2014-06-18 12:04:29 +0300628 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
629 int (*set_infoframe)(struct omap_dss_device *dssdev,
630 const struct hdmi_avi_infoframe *avi);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300631};
632
Tomi Valkeinendeb16df2013-05-24 13:20:27 +0300633struct omapdss_dsi_ops {
634 int (*connect)(struct omap_dss_device *dssdev,
635 struct omap_dss_device *dst);
636 void (*disconnect)(struct omap_dss_device *dssdev,
637 struct omap_dss_device *dst);
638
639 int (*enable)(struct omap_dss_device *dssdev);
640 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
641 bool enter_ulps);
642
643 /* bus configuration */
644 int (*set_config)(struct omap_dss_device *dssdev,
645 const struct omap_dss_dsi_config *cfg);
646 int (*configure_pins)(struct omap_dss_device *dssdev,
647 const struct omap_dsi_pin_config *pin_cfg);
648
649 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
650 bool enable);
651 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
652
653 int (*update)(struct omap_dss_device *dssdev, int channel,
654 void (*callback)(int, void *), void *data);
655
656 void (*bus_lock)(struct omap_dss_device *dssdev);
657 void (*bus_unlock)(struct omap_dss_device *dssdev);
658
659 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
660 void (*disable_video_output)(struct omap_dss_device *dssdev,
661 int channel);
662
663 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
664 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
665 int vc_id);
666 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
667
668 /* data transfer */
669 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
670 u8 *data, int len);
671 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
672 u8 *data, int len);
673 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
674 u8 *data, int len);
675
676 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
677 u8 *data, int len);
678 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
679 u8 *data, int len);
680 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
681 u8 *reqdata, int reqlen,
682 u8 *data, int len);
683
684 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
685
686 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
687 int channel, u16 plen);
688};
689
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200690struct omap_dss_device {
Tomi Valkeinenecc8b372013-02-14 14:17:28 +0200691 struct device *dev;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200692
Tomi Valkeinen4f3e44e2013-05-03 11:35:43 +0300693 struct module *owner;
694
Tomi Valkeinen2e7e3dc2012-11-16 15:45:26 +0200695 struct list_head panel_list;
696
697 /* alias in the form of "display%d" */
698 char alias[16];
699
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200700 enum omap_display_type type;
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300701 enum omap_display_type output_type;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200702
703 union {
704 struct {
705 u8 data_lines;
706 } dpi;
707
708 struct {
709 u8 channel;
710 u8 data_lines;
711 } rfbi;
712
713 struct {
714 u8 datapairs;
715 } sdi;
716
717 struct {
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530718 int module;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200719 } dsi;
720
721 struct {
722 enum omap_dss_venc_type type;
723 bool invert_polarity;
724 } venc;
725 } phy;
726
727 struct {
728 struct omap_video_timings timings;
729
Archit Tanejaa3b3cc22011-09-08 18:42:16 +0530730 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
Archit Taneja7e951ee2011-07-22 12:45:04 +0530731 enum omap_dss_dsi_mode dsi_mode;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200732 } panel;
733
734 struct {
735 u8 pixel_size;
736 struct rfbi_timings rfbi_timings;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200737 } ctrl;
738
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200739 const char *name;
740
741 /* used to match device to driver */
742 const char *driver_name;
743
744 void *data;
745
746 struct omap_dss_driver *driver;
747
Tomi Valkeinen0b24edb2013-05-24 13:18:52 +0300748 union {
749 const struct omapdss_dpi_ops *dpi;
Tomi Valkeinenb1082df2013-05-24 13:19:14 +0300750 const struct omapdss_sdi_ops *sdi;
Tomi Valkeinen7700c2d2013-05-24 13:19:30 +0300751 const struct omapdss_dvi_ops *dvi;
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300752 const struct omapdss_hdmi_ops *hdmi;
Tomi Valkeinenfb8efa42013-05-24 13:19:50 +0300753 const struct omapdss_atv_ops *atv;
Tomi Valkeinendeb16df2013-05-24 13:20:27 +0300754 const struct omapdss_dsi_ops *dsi;
Tomi Valkeinen0b24edb2013-05-24 13:18:52 +0300755 } ops;
756
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200757 /* helper variable for driver suspend/resume */
758 bool activate_after_resume;
759
760 enum omap_display_caps caps;
761
Tomi Valkeinena73fdc62013-07-24 13:01:34 +0300762 struct omap_dss_device *src;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200763
764 enum omap_dss_display_state state;
765
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300766 /* OMAP DSS output specific fields */
767
768 struct list_head list;
769
770 /* DISPC channel for this output */
771 enum omap_channel dispc_channel;
772
773 /* output instance */
774 enum omap_dss_output_id id;
775
Archit Tanejaef691ff2014-04-22 17:43:48 +0530776 /* the port number in the DT node */
777 int port_num;
778
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300779 /* dynamic fields */
780 struct omap_overlay_manager *manager;
781
Tomi Valkeinen9560dc102013-07-24 13:06:54 +0300782 struct omap_dss_device *dst;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200783};
784
Tomi Valkeinenc49d0052012-01-17 11:09:57 +0200785struct omap_dss_hdmi_data
786{
Tomi Valkeinencca35012012-04-26 14:48:32 +0300787 int ct_cp_hpd_gpio;
788 int ls_oe_gpio;
Tomi Valkeinenc49d0052012-01-17 11:09:57 +0200789 int hpd_gpio;
790};
791
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200792struct omap_dss_driver {
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200793 int (*probe)(struct omap_dss_device *);
794 void (*remove)(struct omap_dss_device *);
795
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300796 int (*connect)(struct omap_dss_device *dssdev);
797 void (*disconnect)(struct omap_dss_device *dssdev);
798
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200799 int (*enable)(struct omap_dss_device *display);
800 void (*disable)(struct omap_dss_device *display);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200801 int (*run_test)(struct omap_dss_device *display, int test);
802
Tomi Valkeinen18946f62010-01-12 14:16:41 +0200803 int (*update)(struct omap_dss_device *dssdev,
804 u16 x, u16 y, u16 w, u16 h);
805 int (*sync)(struct omap_dss_device *dssdev);
806
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200807 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
Tomi Valkeinen225b6502010-01-11 15:11:01 +0200808 int (*get_te)(struct omap_dss_device *dssdev);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200809
810 u8 (*get_rotate)(struct omap_dss_device *dssdev);
811 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
812
813 bool (*get_mirror)(struct omap_dss_device *dssdev);
814 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
815
816 int (*memory_read)(struct omap_dss_device *dssdev,
817 void *buf, size_t size,
818 u16 x, u16 y, u16 w, u16 h);
Tomi Valkeinen96adcec2010-01-11 13:54:33 +0200819
820 void (*get_resolution)(struct omap_dss_device *dssdev,
821 u16 *xres, u16 *yres);
Jani Nikula7a0987b2010-06-16 15:26:36 +0300822 void (*get_dimensions)(struct omap_dss_device *dssdev,
823 u32 *width, u32 *height);
Tomi Valkeinena2699502010-01-11 14:33:40 +0200824 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
Tomi Valkeinen36511312010-01-19 15:53:16 +0200825
Tomi Valkeinen69b20482010-01-20 12:11:25 +0200826 int (*check_timings)(struct omap_dss_device *dssdev,
827 struct omap_video_timings *timings);
828 void (*set_timings)(struct omap_dss_device *dssdev,
829 struct omap_video_timings *timings);
830 void (*get_timings)(struct omap_dss_device *dssdev,
831 struct omap_video_timings *timings);
832
Tomi Valkeinen36511312010-01-19 15:53:16 +0200833 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
834 u32 (*get_wss)(struct omap_dss_device *dssdev);
Tomi Valkeinen3d5e0ef2011-08-25 17:10:41 +0300835
836 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
Tomi Valkeinendf4769c2011-08-29 17:26:01 +0300837 bool (*detect)(struct omap_dss_device *dssdev);
Ricardo Neri9c0b8422012-03-06 18:20:37 -0600838
Tomi Valkeinen8c071ca2014-06-18 12:04:29 +0300839 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
840 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
841 const struct hdmi_avi_infoframe *avi);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200842};
843
Tomi Valkeinenb2c7d542012-10-18 13:46:29 +0300844enum omapdss_version omapdss_get_version(void);
Tomi Valkeinen591a0ac2013-05-23 12:07:50 +0300845bool omapdss_is_initialized(void);
Tomi Valkeinenb2c7d542012-10-18 13:46:29 +0300846
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200847int omap_dss_register_driver(struct omap_dss_driver *);
848void omap_dss_unregister_driver(struct omap_dss_driver *);
849
Tomi Valkeinen2e7e3dc2012-11-16 15:45:26 +0200850int omapdss_register_display(struct omap_dss_device *dssdev);
851void omapdss_unregister_display(struct omap_dss_device *dssdev);
852
Tomi Valkeinend35317a2013-05-03 11:40:54 +0300853struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200854void omap_dss_put_device(struct omap_dss_device *dssdev);
855#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
856struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
857struct omap_dss_device *omap_dss_find_device(void *data,
858 int (*match)(struct omap_dss_device *dssdev, void *data));
Tomi Valkeinen2bbcce52012-10-29 12:40:46 +0200859const char *omapdss_get_default_display_name(void);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200860
Tomi Valkeinen6fcd4852013-05-10 13:02:32 +0300861void videomode_to_omap_video_timings(const struct videomode *vm,
862 struct omap_video_timings *ovt);
863void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
864 struct videomode *vm);
865
Tomi Valkeineneda34272012-11-07 16:26:11 +0200866int dss_feat_get_num_mgrs(void);
867int dss_feat_get_num_ovls(void);
868enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
869enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
870enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
871
872
873
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200874int omap_dss_get_num_overlay_managers(void);
875struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
876
877int omap_dss_get_num_overlays(void);
878struct omap_overlay *omap_dss_get_overlay(int num);
879
Tomi Valkeinen5d47dbc2013-04-24 13:32:51 +0300880int omapdss_register_output(struct omap_dss_device *output);
881void omapdss_unregister_output(struct omap_dss_device *output);
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300882struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
883struct omap_dss_device *omap_dss_find_output(const char *name);
Archit Tanejaef691ff2014-04-22 17:43:48 +0530884struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300885int omapdss_output_set_device(struct omap_dss_device *out,
Archit Taneja6d71b922012-08-29 13:30:15 +0530886 struct omap_dss_device *dssdev);
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300887int omapdss_output_unset_device(struct omap_dss_device *out);
Archit Taneja484dc402012-09-07 17:38:00 +0530888
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300889struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
Tomi Valkeinenbe8e8e12013-04-23 15:35:35 +0300890struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
891
Tomi Valkeinen96adcec2010-01-11 13:54:33 +0200892void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
893 u16 *xres, u16 *yres);
Tomi Valkeinena2699502010-01-11 14:33:40 +0200894int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
Grazvydas Ignotas4b6430f2012-03-15 20:00:23 +0200895void omapdss_default_get_timings(struct omap_dss_device *dssdev,
896 struct omap_video_timings *timings);
Tomi Valkeinena2699502010-01-11 14:33:40 +0200897
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200898typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
899int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
900int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
901
Tomi Valkeinen348be692012-11-07 18:17:35 +0200902u32 dispc_read_irqstatus(void);
903void dispc_clear_irqstatus(u32 mask);
904u32 dispc_read_irqenable(void);
905void dispc_write_irqenable(u32 mask);
906
907int dispc_request_irq(irq_handler_t handler, void *dev_id);
908void dispc_free_irq(void *dev_id);
909
910int dispc_runtime_get(void);
911void dispc_runtime_put(void);
912
913void dispc_mgr_enable(enum omap_channel channel, bool enable);
914bool dispc_mgr_is_enabled(enum omap_channel channel);
915u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
916u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
917u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
918bool dispc_mgr_go_busy(enum omap_channel channel);
919void dispc_mgr_go(enum omap_channel channel);
920void dispc_mgr_set_lcd_config(enum omap_channel channel,
921 const struct dss_lcd_mgr_config *config);
922void dispc_mgr_set_timings(enum omap_channel channel,
923 const struct omap_video_timings *timings);
924void dispc_mgr_setup(enum omap_channel channel,
925 const struct omap_overlay_manager_info *info);
926
927int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
928 const struct omap_overlay_info *oi,
929 const struct omap_video_timings *timings,
930 int *x_predecim, int *y_predecim);
931
932int dispc_ovl_enable(enum omap_plane plane, bool enable);
933bool dispc_ovl_enabled(enum omap_plane plane);
934void dispc_ovl_set_channel_out(enum omap_plane plane,
935 enum omap_channel channel);
936int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
937 bool replication, const struct omap_video_timings *mgr_timings,
938 bool mem_to_mem);
939
Tomi Valkeinen8dd24912012-10-10 10:26:45 +0300940int omapdss_compat_init(void);
941void omapdss_compat_uninit(void);
942
Tomi Valkeinena97a9632012-10-24 13:52:40 +0300943struct dss_mgr_ops {
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300944 int (*connect)(struct omap_overlay_manager *mgr,
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300945 struct omap_dss_device *dst);
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300946 void (*disconnect)(struct omap_overlay_manager *mgr,
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300947 struct omap_dss_device *dst);
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300948
Tomi Valkeinena97a9632012-10-24 13:52:40 +0300949 void (*start_update)(struct omap_overlay_manager *mgr);
950 int (*enable)(struct omap_overlay_manager *mgr);
951 void (*disable)(struct omap_overlay_manager *mgr);
952 void (*set_timings)(struct omap_overlay_manager *mgr,
953 const struct omap_video_timings *timings);
954 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
955 const struct dss_lcd_mgr_config *config);
956 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
957 void (*handler)(void *), void *data);
958 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
959 void (*handler)(void *), void *data);
960};
961
962int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
963void dss_uninstall_mgr_ops(void);
964
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300965int dss_mgr_connect(struct omap_overlay_manager *mgr,
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300966 struct omap_dss_device *dst);
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300967void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300968 struct omap_dss_device *dst);
Tomi Valkeinena97a9632012-10-24 13:52:40 +0300969void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
970 const struct omap_video_timings *timings);
971void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
972 const struct dss_lcd_mgr_config *config);
973int dss_mgr_enable(struct omap_overlay_manager *mgr);
974void dss_mgr_disable(struct omap_overlay_manager *mgr);
975void dss_mgr_start_update(struct omap_overlay_manager *mgr);
976int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
977 void (*handler)(void *), void *data);
978void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
979 void (*handler)(void *), void *data);
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300980
981static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
982{
Tomi Valkeinena73fdc62013-07-24 13:01:34 +0300983 return dssdev->src;
Tomi Valkeinena7e71e72013-05-08 16:23:32 +0300984}
985
986static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
987{
988 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
989}
990
Tomi Valkeinen4e7470d2013-12-03 16:57:40 +0200991struct device_node *
992omapdss_of_get_next_port(const struct device_node *parent,
993 struct device_node *prev);
994
995struct device_node *
996omapdss_of_get_next_endpoint(const struct device_node *parent,
997 struct device_node *prev);
998
999struct device_node *
1000omapdss_of_get_first_endpoint(const struct device_node *parent);
1001
1002struct omap_dss_device *
1003omapdss_of_find_source_for_first_ep(struct device_node *node);
1004
Tomi Valkeinen559d6702009-11-03 11:23:50 +02001005#endif