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Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
Li Yange2c8e4252010-11-11 20:16:29 +08004 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
Zhang Wei173acc72008-03-01 07:42:48 -07005 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
Stefan Weilc2e07b32010-08-03 19:44:52 +020013 * The support for MPC8349 DMA controller is also added.
Zhang Wei173acc72008-03-01 07:42:48 -070014 *
Ira W. Snydera7aea372009-04-23 16:17:54 -070015 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
Zhang Wei173acc72008-03-01 07:42:48 -070020 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Zhang Wei173acc72008-03-01 07:42:48 -070031#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
Rob Herring5af50732013-09-17 14:28:33 -050036#include <linux/of_address.h>
37#include <linux/of_irq.h>
Zhang Wei173acc72008-03-01 07:42:48 -070038#include <linux/of_platform.h>
Vinod Koul0a5642b2014-10-11 21:16:44 +053039#include <linux/fsldma.h>
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000040#include "dmaengine.h"
Zhang Wei173acc72008-03-01 07:42:48 -070041#include "fsldma.h"
42
Ira Snyderb1584712011-03-03 07:54:55 +000043#define chan_dbg(chan, fmt, arg...) \
44 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
45#define chan_err(chan, fmt, arg...) \
46 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
Ira Snyderc14330412010-09-30 11:46:45 +000047
Ira Snyderb1584712011-03-03 07:54:55 +000048static const char msg_ld_oom[] = "No free memory for link descriptor";
Zhang Wei173acc72008-03-01 07:42:48 -070049
Ira Snydere8bd84d2011-03-03 07:54:54 +000050/*
51 * Register Helpers
52 */
Zhang Wei173acc72008-03-01 07:42:48 -070053
Ira Snydera1c03312010-01-06 13:34:05 +000054static void set_sr(struct fsldma_chan *chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070055{
Ira Snydera1c03312010-01-06 13:34:05 +000056 DMA_OUT(chan, &chan->regs->sr, val, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070057}
58
Ira Snydera1c03312010-01-06 13:34:05 +000059static u32 get_sr(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070060{
Ira Snydera1c03312010-01-06 13:34:05 +000061 return DMA_IN(chan, &chan->regs->sr, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070062}
63
Hongbo Zhangccdce9a2014-04-18 16:17:45 +080064static void set_mr(struct fsldma_chan *chan, u32 val)
65{
66 DMA_OUT(chan, &chan->regs->mr, val, 32);
67}
68
69static u32 get_mr(struct fsldma_chan *chan)
70{
71 return DMA_IN(chan, &chan->regs->mr, 32);
72}
73
Ira Snydera1c03312010-01-06 13:34:05 +000074static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
Zhang Wei173acc72008-03-01 07:42:48 -070075{
Ira Snydera1c03312010-01-06 13:34:05 +000076 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070077}
78
Ira Snydera1c03312010-01-06 13:34:05 +000079static dma_addr_t get_cdar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070080{
Ira Snydera1c03312010-01-06 13:34:05 +000081 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
Zhang Wei173acc72008-03-01 07:42:48 -070082}
83
Hongbo Zhangccdce9a2014-04-18 16:17:45 +080084static void set_bcr(struct fsldma_chan *chan, u32 val)
85{
86 DMA_OUT(chan, &chan->regs->bcr, val, 32);
87}
88
Ira Snydera1c03312010-01-06 13:34:05 +000089static u32 get_bcr(struct fsldma_chan *chan)
Zhang Weif79abb62008-03-18 18:45:00 -070090{
Ira Snydera1c03312010-01-06 13:34:05 +000091 return DMA_IN(chan, &chan->regs->bcr, 32);
Zhang Weif79abb62008-03-18 18:45:00 -070092}
93
Ira Snydere8bd84d2011-03-03 07:54:54 +000094/*
95 * Descriptor Helpers
96 */
97
Zhang Wei173acc72008-03-01 07:42:48 -070098static void set_desc_cnt(struct fsldma_chan *chan,
99 struct fsl_dma_ld_hw *hw, u32 count)
Zhang Wei173acc72008-03-01 07:42:48 -0700100{
Zhang Wei173acc72008-03-01 07:42:48 -0700101 hw->count = CPU_TO_DMA(chan, count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700102}
103
Zhang Wei173acc72008-03-01 07:42:48 -0700104static void set_desc_src(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000105 struct fsl_dma_ld_hw *hw, dma_addr_t src)
Zhang Wei173acc72008-03-01 07:42:48 -0700106{
Zhang Wei173acc72008-03-01 07:42:48 -0700107 u64 snoop_bits;
Dan Williams900325a2009-03-02 15:33:46 -0700108
Zhang Wei173acc72008-03-01 07:42:48 -0700109 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
110 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
111 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700112}
113
Zhang Wei173acc72008-03-01 07:42:48 -0700114static void set_desc_dst(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000115 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
Zhang Wei173acc72008-03-01 07:42:48 -0700116{
117 u64 snoop_bits;
118
119 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
120 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
121 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
122}
123
124static void set_desc_next(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000125 struct fsl_dma_ld_hw *hw, dma_addr_t next)
Zhang Wei173acc72008-03-01 07:42:48 -0700126{
127 u64 snoop_bits;
128
129 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
130 ? FSL_DMA_SNEN : 0;
131 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
132}
133
Ira Snyder31f43062011-03-03 07:54:57 +0000134static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Zhang Wei173acc72008-03-01 07:42:48 -0700135{
Ira Snyder776c8942009-05-15 11:33:20 -0700136 u64 snoop_bits;
137
Ira Snydera1c03312010-01-06 13:34:05 +0000138 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Ira Snyder776c8942009-05-15 11:33:20 -0700139 ? FSL_DMA_SNEN : 0;
140
Ira Snydera1c03312010-01-06 13:34:05 +0000141 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
142 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
Ira Snyder776c8942009-05-15 11:33:20 -0700143 | snoop_bits, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700144}
145
Ira Snydere8bd84d2011-03-03 07:54:54 +0000146/*
147 * DMA Engine Hardware Control Helpers
148 */
Zhang Wei173acc72008-03-01 07:42:48 -0700149
Ira Snydere8bd84d2011-03-03 07:54:54 +0000150static void dma_init(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700151{
Ira Snydere8bd84d2011-03-03 07:54:54 +0000152 /* Reset the channel */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800153 set_mr(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -0700154
Ira Snydere8bd84d2011-03-03 07:54:54 +0000155 switch (chan->feature & FSL_DMA_IP_MASK) {
156 case FSL_DMA_IP_85XX:
157 /* Set the channel to below modes:
158 * EIE - Error interrupt enable
Ira Snydere8bd84d2011-03-03 07:54:54 +0000159 * EOLNIE - End of links interrupt enable
160 * BWC - Bandwidth sharing among channels
161 */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800162 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
163 | FSL_DMA_MR_EOLNIE);
Ira Snydere8bd84d2011-03-03 07:54:54 +0000164 break;
165 case FSL_DMA_IP_83XX:
166 /* Set the channel to below modes:
167 * EOTIE - End-of-transfer interrupt enable
168 * PRC_RM - PCI read multiple
169 */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800170 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
Ira Snydere8bd84d2011-03-03 07:54:54 +0000171 break;
172 }
Zhang Wei173acc72008-03-01 07:42:48 -0700173}
174
175static int dma_is_idle(struct fsldma_chan *chan)
176{
177 u32 sr = get_sr(chan);
178 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
179}
180
Ira Snyderf04cd402011-03-03 07:54:58 +0000181/*
182 * Start the DMA controller
183 *
184 * Preconditions:
185 * - the CDAR register must point to the start descriptor
186 * - the MRn[CS] bit must be cleared
187 */
Zhang Wei173acc72008-03-01 07:42:48 -0700188static void dma_start(struct fsldma_chan *chan)
189{
190 u32 mode;
191
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800192 mode = get_mr(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700193
Ira Snyderf04cd402011-03-03 07:54:58 +0000194 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800195 set_bcr(chan, 0);
Ira Snyderf04cd402011-03-03 07:54:58 +0000196 mode |= FSL_DMA_MR_EMP_EN;
197 } else {
198 mode &= ~FSL_DMA_MR_EMP_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700199 }
200
Ira Snyderf04cd402011-03-03 07:54:58 +0000201 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
Zhang Wei173acc72008-03-01 07:42:48 -0700202 mode |= FSL_DMA_MR_EMS_EN;
Ira Snyderf04cd402011-03-03 07:54:58 +0000203 } else {
204 mode &= ~FSL_DMA_MR_EMS_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700205 mode |= FSL_DMA_MR_CS;
Ira Snyderf04cd402011-03-03 07:54:58 +0000206 }
Zhang Wei173acc72008-03-01 07:42:48 -0700207
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800208 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700209}
210
211static void dma_halt(struct fsldma_chan *chan)
212{
213 u32 mode;
214 int i;
215
Ira Snydera00ae342011-03-03 07:55:01 +0000216 /* read the mode register */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800217 mode = get_mr(chan);
Ira Snydera00ae342011-03-03 07:55:01 +0000218
219 /*
220 * The 85xx controller supports channel abort, which will stop
221 * the current transfer. On 83xx, this bit is the transfer error
222 * mask bit, which should not be changed.
223 */
224 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
225 mode |= FSL_DMA_MR_CA;
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800226 set_mr(chan, mode);
Ira Snydera00ae342011-03-03 07:55:01 +0000227
228 mode &= ~FSL_DMA_MR_CA;
229 }
230
231 /* stop the DMA controller */
232 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800233 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700234
Ira Snydera00ae342011-03-03 07:55:01 +0000235 /* wait for the DMA controller to become idle */
Zhang Wei173acc72008-03-01 07:42:48 -0700236 for (i = 0; i < 100; i++) {
237 if (dma_is_idle(chan))
238 return;
239
240 udelay(10);
241 }
242
243 if (!dma_is_idle(chan))
Ira Snyderb1584712011-03-03 07:54:55 +0000244 chan_err(chan, "DMA halt timeout!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700245}
246
Zhang Wei173acc72008-03-01 07:42:48 -0700247/**
248 * fsl_chan_set_src_loop_size - Set source address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000249 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700250 * @size : Address loop size, 0 for disable loop
251 *
252 * The set source address hold transfer size. The source
253 * address hold or loop transfer size is when the DMA transfer
254 * data from source address (SA), if the loop size is 4, the DMA will
255 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
256 * SA + 1 ... and so on.
257 */
Ira Snydera1c03312010-01-06 13:34:05 +0000258static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700259{
Ira Snyder272ca652010-01-06 13:33:59 +0000260 u32 mode;
261
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800262 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000263
Zhang Wei173acc72008-03-01 07:42:48 -0700264 switch (size) {
265 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000266 mode &= ~FSL_DMA_MR_SAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700267 break;
268 case 1:
269 case 2:
270 case 4:
271 case 8:
Thomas Breitungccc07722017-06-19 16:40:04 +0200272 mode &= ~FSL_DMA_MR_SAHTS_MASK;
Ira Snyder272ca652010-01-06 13:33:59 +0000273 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
Zhang Wei173acc72008-03-01 07:42:48 -0700274 break;
275 }
Ira Snyder272ca652010-01-06 13:33:59 +0000276
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800277 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700278}
279
280/**
Ira Snyder738f5f72010-01-06 13:34:02 +0000281 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000282 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700283 * @size : Address loop size, 0 for disable loop
284 *
285 * The set destination address hold transfer size. The destination
286 * address hold or loop transfer size is when the DMA transfer
287 * data to destination address (TA), if the loop size is 4, the DMA will
288 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
289 * TA + 1 ... and so on.
290 */
Ira Snydera1c03312010-01-06 13:34:05 +0000291static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700292{
Ira Snyder272ca652010-01-06 13:33:59 +0000293 u32 mode;
294
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800295 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000296
Zhang Wei173acc72008-03-01 07:42:48 -0700297 switch (size) {
298 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000299 mode &= ~FSL_DMA_MR_DAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700300 break;
301 case 1:
302 case 2:
303 case 4:
304 case 8:
Thomas Breitungccc07722017-06-19 16:40:04 +0200305 mode &= ~FSL_DMA_MR_DAHTS_MASK;
Ira Snyder272ca652010-01-06 13:33:59 +0000306 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
Zhang Wei173acc72008-03-01 07:42:48 -0700307 break;
308 }
Ira Snyder272ca652010-01-06 13:33:59 +0000309
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800310 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700311}
312
313/**
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700314 * fsl_chan_set_request_count - Set DMA Request Count for external control
Ira Snydera1c03312010-01-06 13:34:05 +0000315 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700316 * @size : Number of bytes to transfer in a single request
317 *
318 * The Freescale DMA channel can be controlled by the external signal DREQ#.
319 * The DMA request count is how many bytes are allowed to transfer before
320 * pausing the channel, after which a new assertion of DREQ# resumes channel
321 * operation.
322 *
323 * A size of 0 disables external pause control. The maximum size is 1024.
324 */
Ira Snydera1c03312010-01-06 13:34:05 +0000325static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700326{
Ira Snyder272ca652010-01-06 13:33:59 +0000327 u32 mode;
328
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700329 BUG_ON(size > 1024);
Ira Snyder272ca652010-01-06 13:33:59 +0000330
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800331 mode = get_mr(chan);
Thomas Breitungccc07722017-06-19 16:40:04 +0200332 mode &= ~FSL_DMA_MR_BWC_MASK;
333 mode |= (__ilog2(size) << 24) & FSL_DMA_MR_BWC_MASK;
Ira Snyder272ca652010-01-06 13:33:59 +0000334
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800335 set_mr(chan, mode);
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700336}
337
338/**
Zhang Wei173acc72008-03-01 07:42:48 -0700339 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
Ira Snydera1c03312010-01-06 13:34:05 +0000340 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700341 * @enable : 0 is disabled, 1 is enabled.
Zhang Wei173acc72008-03-01 07:42:48 -0700342 *
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700343 * The Freescale DMA channel can be controlled by the external signal DREQ#.
344 * The DMA Request Count feature should be used in addition to this feature
345 * to set the number of bytes to transfer before pausing the channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700346 */
Ira Snydera1c03312010-01-06 13:34:05 +0000347static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700348{
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700349 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000350 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700351 else
Ira Snydera1c03312010-01-06 13:34:05 +0000352 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700353}
354
355/**
356 * fsl_chan_toggle_ext_start - Toggle channel external start status
Ira Snydera1c03312010-01-06 13:34:05 +0000357 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700358 * @enable : 0 is disabled, 1 is enabled.
359 *
360 * If enable the external start, the channel can be started by an
361 * external DMA start pin. So the dma_start() does not start the
362 * transfer immediately. The DMA channel will wait for the
363 * control pin asserted.
364 */
Ira Snydera1c03312010-01-06 13:34:05 +0000365static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700366{
367 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000368 chan->feature |= FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700369 else
Ira Snydera1c03312010-01-06 13:34:05 +0000370 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700371}
372
Vinod Koul0a5642b2014-10-11 21:16:44 +0530373int fsl_dma_external_start(struct dma_chan *dchan, int enable)
374{
375 struct fsldma_chan *chan;
376
377 if (!dchan)
378 return -EINVAL;
379
380 chan = to_fsl_chan(dchan);
381
382 fsl_chan_toggle_ext_start(chan, enable);
383 return 0;
384}
385EXPORT_SYMBOL_GPL(fsl_dma_external_start);
386
Ira Snyder31f43062011-03-03 07:54:57 +0000387static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000388{
389 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
390
391 if (list_empty(&chan->ld_pending))
392 goto out_splice;
393
394 /*
395 * Add the hardware descriptor to the chain of hardware descriptors
396 * that already exists in memory.
397 *
398 * This will un-set the EOL bit of the existing transaction, and the
399 * last link in this transaction will become the EOL descriptor.
400 */
401 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
402
403 /*
404 * Add the software descriptor and all children to the list
405 * of pending transactions
406 */
407out_splice:
408 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
409}
410
Zhang Wei173acc72008-03-01 07:42:48 -0700411static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
412{
Ira Snydera1c03312010-01-06 13:34:05 +0000413 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
Dan Williamseda34232009-09-08 17:53:02 -0700414 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
415 struct fsl_desc_sw *child;
Dan Williamsbbc76562013-12-09 11:16:00 -0800416 dma_cookie_t cookie = -EINVAL;
Zhang Wei173acc72008-03-01 07:42:48 -0700417
Hongbo Zhang2baff572014-05-21 16:03:01 +0800418 spin_lock_bh(&chan->desc_lock);
Zhang Wei173acc72008-03-01 07:42:48 -0700419
Hongbo Zhang14c6a332014-05-21 16:03:02 +0800420#ifdef CONFIG_PM
421 if (unlikely(chan->pm_state != RUNNING)) {
422 chan_dbg(chan, "cannot submit due to suspend\n");
423 spin_unlock_bh(&chan->desc_lock);
424 return -1;
425 }
426#endif
427
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000428 /*
429 * assign cookies to all of the software descriptors
430 * that make up this transaction
431 */
Dan Williamseda34232009-09-08 17:53:02 -0700432 list_for_each_entry(child, &desc->tx_list, node) {
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000433 cookie = dma_cookie_assign(&child->async_tx);
Ira Snyderbcfb7462009-05-15 14:27:16 -0700434 }
435
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000436 /* put this transaction onto the tail of the pending queue */
Ira Snydera1c03312010-01-06 13:34:05 +0000437 append_ld_queue(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700438
Hongbo Zhang2baff572014-05-21 16:03:01 +0800439 spin_unlock_bh(&chan->desc_lock);
Zhang Wei173acc72008-03-01 07:42:48 -0700440
441 return cookie;
442}
443
444/**
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800445 * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
446 * @chan : Freescale DMA channel
447 * @desc: descriptor to be freed
448 */
449static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
450 struct fsl_desc_sw *desc)
451{
452 list_del(&desc->node);
453 chan_dbg(chan, "LD %p free\n", desc);
454 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
455}
456
457/**
Zhang Wei173acc72008-03-01 07:42:48 -0700458 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
Ira Snydera1c03312010-01-06 13:34:05 +0000459 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700460 *
461 * Return - The descriptor allocated. NULL for failed.
462 */
Ira Snyder31f43062011-03-03 07:54:57 +0000463static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700464{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000465 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700466 dma_addr_t pdesc;
Zhang Wei173acc72008-03-01 07:42:48 -0700467
Julia Lawall43764552016-04-29 22:09:12 +0200468 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000469 if (!desc) {
Ira Snyderb1584712011-03-03 07:54:55 +0000470 chan_dbg(chan, "out of memory for link descriptor\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000471 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700472 }
473
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000474 INIT_LIST_HEAD(&desc->tx_list);
475 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
476 desc->async_tx.tx_submit = fsl_dma_tx_submit;
477 desc->async_tx.phys = pdesc;
478
Ira Snyder0ab09c32011-03-03 07:54:56 +0000479 chan_dbg(chan, "LD %p allocated\n", desc);
Ira Snyder0ab09c32011-03-03 07:54:56 +0000480
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000481 return desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700482}
483
Zhang Wei173acc72008-03-01 07:42:48 -0700484/**
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800485 * fsldma_clean_completed_descriptor - free all descriptors which
486 * has been completed and acked
487 * @chan: Freescale DMA channel
488 *
489 * This function is used on all completed and acked descriptors.
490 * All descriptors should only be freed in this function.
491 */
492static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
493{
494 struct fsl_desc_sw *desc, *_desc;
495
496 /* Run the callback for each descriptor, in order */
497 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
498 if (async_tx_test_ack(&desc->async_tx))
499 fsl_dma_free_descriptor(chan, desc);
500}
501
502/**
503 * fsldma_run_tx_complete_actions - cleanup a single link descriptor
504 * @chan: Freescale DMA channel
505 * @desc: descriptor to cleanup and free
506 * @cookie: Freescale DMA transaction identifier
507 *
508 * This function is used on a descriptor which has been executed by the DMA
509 * controller. It will run any callbacks, submit any dependencies.
510 */
511static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
512 struct fsl_desc_sw *desc, dma_cookie_t cookie)
513{
514 struct dma_async_tx_descriptor *txd = &desc->async_tx;
515 dma_cookie_t ret = cookie;
516
517 BUG_ON(txd->cookie < 0);
518
519 if (txd->cookie > 0) {
520 ret = txd->cookie;
521
Dave Jiang9b335972016-07-25 10:33:57 -0700522 dma_descriptor_unmap(txd);
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800523 /* Run the link descriptor callback function */
Dave Jiangaf1a5a52016-07-20 13:11:17 -0700524 dmaengine_desc_get_callback_invoke(txd, NULL);
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800525 }
526
527 /* Run any dependencies */
528 dma_run_dependencies(txd);
529
530 return ret;
531}
532
533/**
534 * fsldma_clean_running_descriptor - move the completed descriptor from
535 * ld_running to ld_completed
536 * @chan: Freescale DMA channel
537 * @desc: the descriptor which is completed
538 *
539 * Free the descriptor directly if acked by async_tx api, or move it to
540 * queue ld_completed.
541 */
542static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
543 struct fsl_desc_sw *desc)
544{
545 /* Remove from the list of transactions */
546 list_del(&desc->node);
547
548 /*
549 * the client is allowed to attach dependent operations
550 * until 'ack' is set
551 */
552 if (!async_tx_test_ack(&desc->async_tx)) {
553 /*
554 * Move this descriptor to the list of descriptors which is
555 * completed, but still awaiting the 'ack' bit to be set.
556 */
557 list_add_tail(&desc->node, &chan->ld_completed);
558 return;
559 }
560
561 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
562}
563
564/**
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800565 * fsl_chan_xfer_ld_queue - transfer any pending transactions
566 * @chan : Freescale DMA channel
567 *
568 * HARDWARE STATE: idle
569 * LOCKING: must hold chan->desc_lock
570 */
571static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
572{
573 struct fsl_desc_sw *desc;
574
575 /*
576 * If the list of pending descriptors is empty, then we
577 * don't need to do any work at all
578 */
579 if (list_empty(&chan->ld_pending)) {
580 chan_dbg(chan, "no pending LDs\n");
581 return;
582 }
583
584 /*
585 * The DMA controller is not idle, which means that the interrupt
586 * handler will start any queued transactions when it runs after
587 * this transaction finishes
588 */
589 if (!chan->idle) {
590 chan_dbg(chan, "DMA controller still busy\n");
591 return;
592 }
593
594 /*
595 * If there are some link descriptors which have not been
596 * transferred, we need to start the controller
597 */
598
599 /*
600 * Move all elements from the queue of pending transactions
601 * onto the list of running transactions
602 */
603 chan_dbg(chan, "idle, starting controller\n");
604 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
605 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
606
607 /*
608 * The 85xx DMA controller doesn't clear the channel start bit
609 * automatically at the end of a transfer. Therefore we must clear
610 * it in software before starting the transfer.
611 */
612 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
613 u32 mode;
614
615 mode = get_mr(chan);
616 mode &= ~FSL_DMA_MR_CS;
617 set_mr(chan, mode);
618 }
619
620 /*
621 * Program the descriptor's address into the DMA controller,
622 * then start the DMA transaction
623 */
624 set_cdar(chan, desc->async_tx.phys);
625 get_cdar(chan);
626
627 dma_start(chan);
628 chan->idle = false;
629}
630
631/**
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800632 * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
633 * and move them to ld_completed to free until flag 'ack' is set
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800634 * @chan: Freescale DMA channel
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800635 *
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800636 * This function is used on descriptors which have been executed by the DMA
637 * controller. It will run any callbacks, submit any dependencies, then
638 * free these descriptors if flag 'ack' is set.
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800639 */
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800640static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800641{
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800642 struct fsl_desc_sw *desc, *_desc;
643 dma_cookie_t cookie = 0;
644 dma_addr_t curr_phys = get_cdar(chan);
645 int seen_current = 0;
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800646
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800647 fsldma_clean_completed_descriptor(chan);
648
649 /* Run the callback for each descriptor, in order */
650 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
651 /*
652 * do not advance past the current descriptor loaded into the
653 * hardware channel, subsequent descriptors are either in
654 * process or have not been submitted
655 */
656 if (seen_current)
657 break;
658
659 /*
660 * stop the search if we reach the current descriptor and the
661 * channel is busy
662 */
663 if (desc->async_tx.phys == curr_phys) {
664 seen_current = 1;
665 if (!dma_is_idle(chan))
666 break;
667 }
668
669 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
670
671 fsldma_clean_running_descriptor(chan, desc);
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800672 }
673
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800674 /*
675 * Start any pending transactions automatically
676 *
677 * In the ideal case, we keep the DMA controller busy while we go
678 * ahead and free the descriptors below.
679 */
680 fsl_chan_xfer_ld_queue(chan);
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800681
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800682 if (cookie > 0)
683 chan->common.completed_cookie = cookie;
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800684}
685
686/**
Zhang Wei173acc72008-03-01 07:42:48 -0700687 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000688 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700689 *
690 * This function will create a dma pool for descriptor allocation.
691 *
692 * Return - The number of descriptors allocated.
693 */
Ira Snydera1c03312010-01-06 13:34:05 +0000694static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700695{
Ira Snydera1c03312010-01-06 13:34:05 +0000696 struct fsldma_chan *chan = to_fsl_chan(dchan);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700697
698 /* Has this channel already been allocated? */
Ira Snydera1c03312010-01-06 13:34:05 +0000699 if (chan->desc_pool)
Timur Tabi77cd62e2008-09-26 17:00:11 -0700700 return 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700701
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000702 /*
703 * We need the descriptor to be aligned to 32bytes
Zhang Wei173acc72008-03-01 07:42:48 -0700704 * for meeting FSL DMA specification requirement.
705 */
Ira Snyderb1584712011-03-03 07:54:55 +0000706 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000707 sizeof(struct fsl_desc_sw),
708 __alignof__(struct fsl_desc_sw), 0);
Ira Snydera1c03312010-01-06 13:34:05 +0000709 if (!chan->desc_pool) {
Ira Snyderb1584712011-03-03 07:54:55 +0000710 chan_err(chan, "unable to allocate descriptor pool\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000711 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700712 }
713
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000714 /* there is at least one descriptor free to be allocated */
Zhang Wei173acc72008-03-01 07:42:48 -0700715 return 1;
716}
717
718/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000719 * fsldma_free_desc_list - Free all descriptors in a queue
720 * @chan: Freescae DMA channel
721 * @list: the list to free
722 *
723 * LOCKING: must hold chan->desc_lock
724 */
725static void fsldma_free_desc_list(struct fsldma_chan *chan,
726 struct list_head *list)
727{
728 struct fsl_desc_sw *desc, *_desc;
729
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800730 list_for_each_entry_safe(desc, _desc, list, node)
731 fsl_dma_free_descriptor(chan, desc);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000732}
733
734static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
735 struct list_head *list)
736{
737 struct fsl_desc_sw *desc, *_desc;
738
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800739 list_for_each_entry_safe_reverse(desc, _desc, list, node)
740 fsl_dma_free_descriptor(chan, desc);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000741}
742
743/**
Zhang Wei173acc72008-03-01 07:42:48 -0700744 * fsl_dma_free_chan_resources - Free all resources of the channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000745 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700746 */
Ira Snydera1c03312010-01-06 13:34:05 +0000747static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700748{
Ira Snydera1c03312010-01-06 13:34:05 +0000749 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700750
Ira Snyderb1584712011-03-03 07:54:55 +0000751 chan_dbg(chan, "free all channel resources\n");
Hongbo Zhang2baff572014-05-21 16:03:01 +0800752 spin_lock_bh(&chan->desc_lock);
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800753 fsldma_cleanup_descriptors(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000754 fsldma_free_desc_list(chan, &chan->ld_pending);
755 fsldma_free_desc_list(chan, &chan->ld_running);
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800756 fsldma_free_desc_list(chan, &chan->ld_completed);
Hongbo Zhang2baff572014-05-21 16:03:01 +0800757 spin_unlock_bh(&chan->desc_lock);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700758
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000759 dma_pool_destroy(chan->desc_pool);
Ira Snydera1c03312010-01-06 13:34:05 +0000760 chan->desc_pool = NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700761}
762
Zhang Wei2187c262008-03-13 17:45:28 -0700763static struct dma_async_tx_descriptor *
Ira Snyder31f43062011-03-03 07:54:57 +0000764fsl_dma_prep_memcpy(struct dma_chan *dchan,
765 dma_addr_t dma_dst, dma_addr_t dma_src,
Zhang Wei173acc72008-03-01 07:42:48 -0700766 size_t len, unsigned long flags)
767{
Ira Snydera1c03312010-01-06 13:34:05 +0000768 struct fsldma_chan *chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700769 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
770 size_t copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700771
Ira Snydera1c03312010-01-06 13:34:05 +0000772 if (!dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700773 return NULL;
774
775 if (!len)
776 return NULL;
777
Ira Snydera1c03312010-01-06 13:34:05 +0000778 chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700779
780 do {
781
782 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000783 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700784 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000785 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyder2e077f82009-05-15 09:59:46 -0700786 goto fail;
Zhang Wei173acc72008-03-01 07:42:48 -0700787 }
Zhang Wei173acc72008-03-01 07:42:48 -0700788
Zhang Wei56822842008-03-13 10:45:27 -0700789 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700790
Ira Snydera1c03312010-01-06 13:34:05 +0000791 set_desc_cnt(chan, &new->hw, copy);
792 set_desc_src(chan, &new->hw, dma_src);
793 set_desc_dst(chan, &new->hw, dma_dst);
Zhang Wei173acc72008-03-01 07:42:48 -0700794
795 if (!first)
796 first = new;
797 else
Ira Snydera1c03312010-01-06 13:34:05 +0000798 set_desc_next(chan, &prev->hw, new->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700799
800 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700801 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700802
803 prev = new;
804 len -= copy;
805 dma_src += copy;
Ira Snyder738f5f72010-01-06 13:34:02 +0000806 dma_dst += copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700807
808 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700809 list_add_tail(&new->node, &first->tx_list);
Zhang Wei173acc72008-03-01 07:42:48 -0700810 } while (len);
811
Dan Williams636bdea2008-04-17 20:17:26 -0700812 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700813 new->async_tx.cookie = -EBUSY;
814
Ira Snyder31f43062011-03-03 07:54:57 +0000815 /* Set End-of-link to the last link descriptor of new list */
Ira Snydera1c03312010-01-06 13:34:05 +0000816 set_ld_eol(chan, new);
Zhang Wei173acc72008-03-01 07:42:48 -0700817
Ira Snyder2e077f82009-05-15 09:59:46 -0700818 return &first->async_tx;
819
820fail:
821 if (!first)
822 return NULL;
823
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000824 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyder2e077f82009-05-15 09:59:46 -0700825 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700826}
827
Maxime Ripardb7f75522014-11-17 14:42:24 +0100828static int fsl_dma_device_terminate_all(struct dma_chan *dchan)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700829{
Ira Snydera1c03312010-01-06 13:34:05 +0000830 struct fsldma_chan *chan;
Linus Walleijc3635c72010-03-26 16:44:01 -0700831
Ira Snydera1c03312010-01-06 13:34:05 +0000832 if (!dchan)
Linus Walleijc3635c72010-03-26 16:44:01 -0700833 return -EINVAL;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700834
Ira Snydera1c03312010-01-06 13:34:05 +0000835 chan = to_fsl_chan(dchan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700836
Maxime Ripardb7f75522014-11-17 14:42:24 +0100837 spin_lock_bh(&chan->desc_lock);
Ira Snyderf04cd402011-03-03 07:54:58 +0000838
Maxime Ripardb7f75522014-11-17 14:42:24 +0100839 /* Halt the DMA engine */
840 dma_halt(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700841
Maxime Ripardb7f75522014-11-17 14:42:24 +0100842 /* Remove and free all of the descriptors in the LD queue */
843 fsldma_free_desc_list(chan, &chan->ld_pending);
844 fsldma_free_desc_list(chan, &chan->ld_running);
845 fsldma_free_desc_list(chan, &chan->ld_completed);
846 chan->idle = true;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700847
Maxime Ripardb7f75522014-11-17 14:42:24 +0100848 spin_unlock_bh(&chan->desc_lock);
Linus Walleijc3635c72010-03-26 16:44:01 -0700849 return 0;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700850}
851
Maxime Ripardb7f75522014-11-17 14:42:24 +0100852static int fsl_dma_device_config(struct dma_chan *dchan,
853 struct dma_slave_config *config)
854{
855 struct fsldma_chan *chan;
856 int size;
857
858 if (!dchan)
859 return -EINVAL;
860
861 chan = to_fsl_chan(dchan);
862
863 /* make sure the channel supports setting burst size */
864 if (!chan->set_request_count)
865 return -ENXIO;
866
867 /* we set the controller burst size depending on direction */
868 if (config->direction == DMA_MEM_TO_DEV)
869 size = config->dst_addr_width * config->dst_maxburst;
870 else
871 size = config->src_addr_width * config->src_maxburst;
872
873 chan->set_request_count(chan, size);
874 return 0;
875}
876
877
Ira Snyderbbea0b62009-09-08 17:53:04 -0700878/**
Zhang Wei173acc72008-03-01 07:42:48 -0700879 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
Ira Snydera1c03312010-01-06 13:34:05 +0000880 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700881 */
Ira Snydera1c03312010-01-06 13:34:05 +0000882static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700883{
Ira Snydera1c03312010-01-06 13:34:05 +0000884 struct fsldma_chan *chan = to_fsl_chan(dchan);
Ira Snyderdc8d4092011-03-03 07:55:00 +0000885
Hongbo Zhang2baff572014-05-21 16:03:01 +0800886 spin_lock_bh(&chan->desc_lock);
Ira Snydera1c03312010-01-06 13:34:05 +0000887 fsl_chan_xfer_ld_queue(chan);
Hongbo Zhang2baff572014-05-21 16:03:01 +0800888 spin_unlock_bh(&chan->desc_lock);
Zhang Wei173acc72008-03-01 07:42:48 -0700889}
890
Zhang Wei173acc72008-03-01 07:42:48 -0700891/**
Linus Walleij07934482010-03-26 16:50:49 -0700892 * fsl_tx_status - Determine the DMA status
Ira Snydera1c03312010-01-06 13:34:05 +0000893 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700894 */
Linus Walleij07934482010-03-26 16:50:49 -0700895static enum dma_status fsl_tx_status(struct dma_chan *dchan,
Zhang Wei173acc72008-03-01 07:42:48 -0700896 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -0700897 struct dma_tx_state *txstate)
Zhang Wei173acc72008-03-01 07:42:48 -0700898{
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800899 struct fsldma_chan *chan = to_fsl_chan(dchan);
900 enum dma_status ret;
901
902 ret = dma_cookie_status(dchan, cookie, txstate);
903 if (ret == DMA_COMPLETE)
904 return ret;
905
906 spin_lock_bh(&chan->desc_lock);
907 fsldma_cleanup_descriptors(chan);
908 spin_unlock_bh(&chan->desc_lock);
909
Andy Shevchenko9b0b0bd2013-05-27 15:14:35 +0300910 return dma_cookie_status(dchan, cookie, txstate);
Zhang Wei173acc72008-03-01 07:42:48 -0700911}
912
Ira Snyderd3f620b2010-01-06 13:34:04 +0000913/*----------------------------------------------------------------------------*/
914/* Interrupt Handling */
915/*----------------------------------------------------------------------------*/
916
Ira Snydere7a29152010-01-06 13:34:03 +0000917static irqreturn_t fsldma_chan_irq(int irq, void *data)
Zhang Wei173acc72008-03-01 07:42:48 -0700918{
Ira Snydera1c03312010-01-06 13:34:05 +0000919 struct fsldma_chan *chan = data;
Ira Snydera1c03312010-01-06 13:34:05 +0000920 u32 stat;
Zhang Wei173acc72008-03-01 07:42:48 -0700921
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000922 /* save and clear the status register */
Ira Snydera1c03312010-01-06 13:34:05 +0000923 stat = get_sr(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000924 set_sr(chan, stat);
Ira Snyderb1584712011-03-03 07:54:55 +0000925 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -0700926
Ira Snyderf04cd402011-03-03 07:54:58 +0000927 /* check that this was really our device */
Zhang Wei173acc72008-03-01 07:42:48 -0700928 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
929 if (!stat)
930 return IRQ_NONE;
931
932 if (stat & FSL_DMA_SR_TE)
Ira Snyderb1584712011-03-03 07:54:55 +0000933 chan_err(chan, "Transfer Error!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700934
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000935 /*
936 * Programming Error
Zhang Weif79abb62008-03-18 18:45:00 -0700937 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
Masanari Iidad73111c2012-08-04 23:37:53 +0900938 * trigger a PE interrupt.
Zhang Weif79abb62008-03-18 18:45:00 -0700939 */
940 if (stat & FSL_DMA_SR_PE) {
Ira Snyderb1584712011-03-03 07:54:55 +0000941 chan_dbg(chan, "irq: Programming Error INT\n");
Zhang Weif79abb62008-03-18 18:45:00 -0700942 stat &= ~FSL_DMA_SR_PE;
Ira Snyderf04cd402011-03-03 07:54:58 +0000943 if (get_bcr(chan) != 0)
944 chan_err(chan, "Programming Error!\n");
Zhang Wei1c629792008-04-17 20:17:25 -0700945 }
946
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000947 /*
948 * For MPC8349, EOCDI event need to update cookie
Zhang Wei1c629792008-04-17 20:17:25 -0700949 * and start the next transfer if it exist.
950 */
951 if (stat & FSL_DMA_SR_EOCDI) {
Ira Snyderb1584712011-03-03 07:54:55 +0000952 chan_dbg(chan, "irq: End-of-Chain link INT\n");
Zhang Wei1c629792008-04-17 20:17:25 -0700953 stat &= ~FSL_DMA_SR_EOCDI;
Zhang Wei173acc72008-03-01 07:42:48 -0700954 }
955
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000956 /*
957 * If it current transfer is the end-of-transfer,
Zhang Wei173acc72008-03-01 07:42:48 -0700958 * we should clear the Channel Start bit for
959 * prepare next transfer.
960 */
Zhang Wei1c629792008-04-17 20:17:25 -0700961 if (stat & FSL_DMA_SR_EOLNI) {
Ira Snyderb1584712011-03-03 07:54:55 +0000962 chan_dbg(chan, "irq: End-of-link INT\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700963 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei173acc72008-03-01 07:42:48 -0700964 }
965
Ira Snyderf04cd402011-03-03 07:54:58 +0000966 /* check that the DMA controller is really idle */
967 if (!dma_is_idle(chan))
968 chan_err(chan, "irq: controller not idle!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700969
Ira Snyderf04cd402011-03-03 07:54:58 +0000970 /* check that we handled all of the bits */
971 if (stat)
972 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
973
974 /*
975 * Schedule the tasklet to handle all cleanup of the current
976 * transaction. It will start a new transaction if there is
977 * one pending.
978 */
Ira Snydera1c03312010-01-06 13:34:05 +0000979 tasklet_schedule(&chan->tasklet);
Ira Snyderf04cd402011-03-03 07:54:58 +0000980 chan_dbg(chan, "irq: Exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700981 return IRQ_HANDLED;
982}
983
Zhang Wei173acc72008-03-01 07:42:48 -0700984static void dma_do_tasklet(unsigned long data)
985{
Ira Snydera1c03312010-01-06 13:34:05 +0000986 struct fsldma_chan *chan = (struct fsldma_chan *)data;
Ira Snyderf04cd402011-03-03 07:54:58 +0000987
988 chan_dbg(chan, "tasklet entry\n");
989
Hongbo Zhang2baff572014-05-21 16:03:01 +0800990 spin_lock_bh(&chan->desc_lock);
Ira Snyderdc8d4092011-03-03 07:55:00 +0000991
Ira Snyderdc8d4092011-03-03 07:55:00 +0000992 /* the hardware is now idle and ready for more */
Ira Snyderf04cd402011-03-03 07:54:58 +0000993 chan->idle = true;
Ira Snyderdc8d4092011-03-03 07:55:00 +0000994
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800995 /* Run all cleanup for descriptors which have been completed */
996 fsldma_cleanup_descriptors(chan);
997
Hongbo Zhang2baff572014-05-21 16:03:01 +0800998 spin_unlock_bh(&chan->desc_lock);
Ira Snyderf04cd402011-03-03 07:54:58 +0000999
Ira Snyderf04cd402011-03-03 07:54:58 +00001000 chan_dbg(chan, "tasklet exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001001}
1002
Ira Snyderd3f620b2010-01-06 13:34:04 +00001003static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1004{
1005 struct fsldma_device *fdev = data;
1006 struct fsldma_chan *chan;
1007 unsigned int handled = 0;
1008 u32 gsr, mask;
1009 int i;
1010
1011 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1012 : in_le32(fdev->regs);
1013 mask = 0xff000000;
1014 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1015
1016 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1017 chan = fdev->chan[i];
1018 if (!chan)
1019 continue;
1020
1021 if (gsr & mask) {
1022 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1023 fsldma_chan_irq(irq, chan);
1024 handled++;
1025 }
1026
1027 gsr &= ~mask;
1028 mask >>= 8;
1029 }
1030
1031 return IRQ_RETVAL(handled);
1032}
1033
1034static void fsldma_free_irqs(struct fsldma_device *fdev)
1035{
1036 struct fsldma_chan *chan;
1037 int i;
1038
Michael Ellermanaa570be2016-09-10 19:56:04 +10001039 if (fdev->irq) {
Ira Snyderd3f620b2010-01-06 13:34:04 +00001040 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1041 free_irq(fdev->irq, fdev);
1042 return;
1043 }
1044
1045 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1046 chan = fdev->chan[i];
Michael Ellermanaa570be2016-09-10 19:56:04 +10001047 if (chan && chan->irq) {
Ira Snyderb1584712011-03-03 07:54:55 +00001048 chan_dbg(chan, "free per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001049 free_irq(chan->irq, chan);
1050 }
1051 }
1052}
1053
1054static int fsldma_request_irqs(struct fsldma_device *fdev)
1055{
1056 struct fsldma_chan *chan;
1057 int ret;
1058 int i;
1059
1060 /* if we have a per-controller IRQ, use that */
Michael Ellermanaa570be2016-09-10 19:56:04 +10001061 if (fdev->irq) {
Ira Snyderd3f620b2010-01-06 13:34:04 +00001062 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1063 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1064 "fsldma-controller", fdev);
1065 return ret;
1066 }
1067
1068 /* no per-controller IRQ, use the per-channel IRQs */
1069 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1070 chan = fdev->chan[i];
1071 if (!chan)
1072 continue;
1073
Michael Ellermanaa570be2016-09-10 19:56:04 +10001074 if (!chan->irq) {
Ira Snyderb1584712011-03-03 07:54:55 +00001075 chan_err(chan, "interrupts property missing in device tree\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001076 ret = -ENODEV;
1077 goto out_unwind;
1078 }
1079
Ira Snyderb1584712011-03-03 07:54:55 +00001080 chan_dbg(chan, "request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001081 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1082 "fsldma-chan", chan);
1083 if (ret) {
Ira Snyderb1584712011-03-03 07:54:55 +00001084 chan_err(chan, "unable to request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001085 goto out_unwind;
1086 }
1087 }
1088
1089 return 0;
1090
1091out_unwind:
1092 for (/* none */; i >= 0; i--) {
1093 chan = fdev->chan[i];
1094 if (!chan)
1095 continue;
1096
Michael Ellermanaa570be2016-09-10 19:56:04 +10001097 if (!chan->irq)
Ira Snyderd3f620b2010-01-06 13:34:04 +00001098 continue;
1099
1100 free_irq(chan->irq, chan);
1101 }
1102
1103 return ret;
1104}
1105
Ira Snydera4f56d42010-01-06 13:34:01 +00001106/*----------------------------------------------------------------------------*/
1107/* OpenFirmware Subsystem */
1108/*----------------------------------------------------------------------------*/
1109
Bill Pemberton463a1f82012-11-19 13:22:55 -05001110static int fsl_dma_chan_probe(struct fsldma_device *fdev,
Timur Tabi77cd62e2008-09-26 17:00:11 -07001111 struct device_node *node, u32 feature, const char *compatible)
Zhang Wei173acc72008-03-01 07:42:48 -07001112{
Ira Snydera1c03312010-01-06 13:34:05 +00001113 struct fsldma_chan *chan;
Ira Snyder4ce0e952010-01-06 13:34:00 +00001114 struct resource res;
Zhang Wei173acc72008-03-01 07:42:48 -07001115 int err;
1116
Zhang Wei173acc72008-03-01 07:42:48 -07001117 /* alloc channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001118 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1119 if (!chan) {
Ira Snydere7a29152010-01-06 13:34:03 +00001120 err = -ENOMEM;
1121 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001122 }
1123
Ira Snydere7a29152010-01-06 13:34:03 +00001124 /* ioremap registers for use */
Ira Snydera1c03312010-01-06 13:34:05 +00001125 chan->regs = of_iomap(node, 0);
1126 if (!chan->regs) {
Ira Snydere7a29152010-01-06 13:34:03 +00001127 dev_err(fdev->dev, "unable to ioremap registers\n");
1128 err = -ENOMEM;
Ira Snydera1c03312010-01-06 13:34:05 +00001129 goto out_free_chan;
Ira Snydere7a29152010-01-06 13:34:03 +00001130 }
1131
Ira Snyder4ce0e952010-01-06 13:34:00 +00001132 err = of_address_to_resource(node, 0, &res);
Zhang Wei173acc72008-03-01 07:42:48 -07001133 if (err) {
Ira Snydere7a29152010-01-06 13:34:03 +00001134 dev_err(fdev->dev, "unable to find 'reg' property\n");
1135 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001136 }
1137
Ira Snydera1c03312010-01-06 13:34:05 +00001138 chan->feature = feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001139 if (!fdev->feature)
Ira Snydera1c03312010-01-06 13:34:05 +00001140 fdev->feature = chan->feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001141
Ira Snydere7a29152010-01-06 13:34:03 +00001142 /*
1143 * If the DMA device's feature is different than the feature
1144 * of its channels, report the bug
Zhang Wei173acc72008-03-01 07:42:48 -07001145 */
Ira Snydera1c03312010-01-06 13:34:05 +00001146 WARN_ON(fdev->feature != chan->feature);
Zhang Wei173acc72008-03-01 07:42:48 -07001147
Ira Snydera1c03312010-01-06 13:34:05 +00001148 chan->dev = fdev->dev;
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001149 chan->id = (res.start & 0xfff) < 0x300 ?
1150 ((res.start - 0x100) & 0xfff) >> 7 :
1151 ((res.start - 0x200) & 0xfff) >> 7;
Ira Snydera1c03312010-01-06 13:34:05 +00001152 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
Ira Snydere7a29152010-01-06 13:34:03 +00001153 dev_err(fdev->dev, "too many channels for device\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001154 err = -EINVAL;
Ira Snydere7a29152010-01-06 13:34:03 +00001155 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001156 }
Zhang Wei173acc72008-03-01 07:42:48 -07001157
Ira Snydera1c03312010-01-06 13:34:05 +00001158 fdev->chan[chan->id] = chan;
1159 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
Ira Snyderb1584712011-03-03 07:54:55 +00001160 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
Ira Snydere7a29152010-01-06 13:34:03 +00001161
1162 /* Initialize the channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001163 dma_init(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001164
1165 /* Clear cdar registers */
Ira Snydera1c03312010-01-06 13:34:05 +00001166 set_cdar(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -07001167
Ira Snydera1c03312010-01-06 13:34:05 +00001168 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -07001169 case FSL_DMA_IP_85XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001170 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
Zhang Wei173acc72008-03-01 07:42:48 -07001171 case FSL_DMA_IP_83XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001172 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1173 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1174 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1175 chan->set_request_count = fsl_chan_set_request_count;
Zhang Wei173acc72008-03-01 07:42:48 -07001176 }
1177
Ira Snydera1c03312010-01-06 13:34:05 +00001178 spin_lock_init(&chan->desc_lock);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001179 INIT_LIST_HEAD(&chan->ld_pending);
1180 INIT_LIST_HEAD(&chan->ld_running);
Hongbo Zhang43452fa2014-05-21 16:03:03 +08001181 INIT_LIST_HEAD(&chan->ld_completed);
Ira Snyderf04cd402011-03-03 07:54:58 +00001182 chan->idle = true;
Hongbo Zhang14c6a332014-05-21 16:03:02 +08001183#ifdef CONFIG_PM
1184 chan->pm_state = RUNNING;
1185#endif
Zhang Wei173acc72008-03-01 07:42:48 -07001186
Ira Snydera1c03312010-01-06 13:34:05 +00001187 chan->common.device = &fdev->common;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +00001188 dma_cookie_init(&chan->common);
Zhang Wei173acc72008-03-01 07:42:48 -07001189
Ira Snyderd3f620b2010-01-06 13:34:04 +00001190 /* find the IRQ line, if it exists in the device tree */
Ira Snydera1c03312010-01-06 13:34:05 +00001191 chan->irq = irq_of_parse_and_map(node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001192
Zhang Wei173acc72008-03-01 07:42:48 -07001193 /* Add the channel to DMA device channel list */
Ira Snydera1c03312010-01-06 13:34:05 +00001194 list_add_tail(&chan->common.device_node, &fdev->common.channels);
Zhang Wei173acc72008-03-01 07:42:48 -07001195
Ira Snydera1c03312010-01-06 13:34:05 +00001196 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
Michael Ellermanaa570be2016-09-10 19:56:04 +10001197 chan->irq ? chan->irq : fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001198
1199 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001200
Ira Snydere7a29152010-01-06 13:34:03 +00001201out_iounmap_regs:
Ira Snydera1c03312010-01-06 13:34:05 +00001202 iounmap(chan->regs);
1203out_free_chan:
1204 kfree(chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001205out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001206 return err;
1207}
1208
Ira Snydera1c03312010-01-06 13:34:05 +00001209static void fsl_dma_chan_remove(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -07001210{
Ira Snydera1c03312010-01-06 13:34:05 +00001211 irq_dispose_mapping(chan->irq);
1212 list_del(&chan->common.device_node);
1213 iounmap(chan->regs);
1214 kfree(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001215}
1216
Bill Pemberton463a1f82012-11-19 13:22:55 -05001217static int fsldma_of_probe(struct platform_device *op)
Zhang Wei173acc72008-03-01 07:42:48 -07001218{
Ira Snydera4f56d42010-01-06 13:34:01 +00001219 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001220 struct device_node *child;
Christophe JAILLETe165c112020-12-12 17:06:14 +01001221 unsigned int i;
Ira Snydere7a29152010-01-06 13:34:03 +00001222 int err;
Zhang Wei173acc72008-03-01 07:42:48 -07001223
Ira Snydera4f56d42010-01-06 13:34:01 +00001224 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
Zhang Wei173acc72008-03-01 07:42:48 -07001225 if (!fdev) {
Ira Snydere7a29152010-01-06 13:34:03 +00001226 err = -ENOMEM;
1227 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001228 }
Ira Snydere7a29152010-01-06 13:34:03 +00001229
1230 fdev->dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001231 INIT_LIST_HEAD(&fdev->common.channels);
1232
Ira Snydere7a29152010-01-06 13:34:03 +00001233 /* ioremap the registers for use */
Grant Likely61c7a082010-04-13 16:12:29 -07001234 fdev->regs = of_iomap(op->dev.of_node, 0);
Ira Snydere7a29152010-01-06 13:34:03 +00001235 if (!fdev->regs) {
1236 dev_err(&op->dev, "unable to ioremap registers\n");
1237 err = -ENOMEM;
Arvind Yadav585a1db2016-09-28 16:15:11 +05301238 goto out_free;
Zhang Wei173acc72008-03-01 07:42:48 -07001239 }
1240
Ira Snyderd3f620b2010-01-06 13:34:04 +00001241 /* map the channel IRQ if it exists, but don't hookup the handler yet */
Grant Likely61c7a082010-04-13 16:12:29 -07001242 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001243
Zhang Wei173acc72008-03-01 07:42:48 -07001244 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
Ira Snyderbbea0b62009-09-08 17:53:04 -07001245 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
Zhang Wei173acc72008-03-01 07:42:48 -07001246 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1247 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei173acc72008-03-01 07:42:48 -07001248 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
Linus Walleij07934482010-03-26 16:50:49 -07001249 fdev->common.device_tx_status = fsl_tx_status;
Zhang Wei173acc72008-03-01 07:42:48 -07001250 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Maxime Ripardb7f75522014-11-17 14:42:24 +01001251 fdev->common.device_config = fsl_dma_device_config;
1252 fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
Ira Snydere7a29152010-01-06 13:34:03 +00001253 fdev->common.dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001254
Kevin Hao75dc1772015-01-08 18:38:16 +08001255 fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS;
1256 fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS;
1257 fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1258 fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1259
Li Yange2c8e4252010-11-11 20:16:29 +08001260 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1261
Jingoo Handd3daca2013-05-24 10:10:13 +09001262 platform_set_drvdata(op, fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001263
Ira Snydere7a29152010-01-06 13:34:03 +00001264 /*
1265 * We cannot use of_platform_bus_probe() because there is no
1266 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -07001267 * channel object.
1268 */
Grant Likely61c7a082010-04-13 16:12:29 -07001269 for_each_child_of_node(op->dev.of_node, child) {
Ira Snydere7a29152010-01-06 13:34:03 +00001270 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001271 fsl_dma_chan_probe(fdev, child,
1272 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1273 "fsl,eloplus-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001274 }
1275
1276 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001277 fsl_dma_chan_probe(fdev, child,
1278 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1279 "fsl,elo-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001280 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001281 }
Zhang Wei173acc72008-03-01 07:42:48 -07001282
Ira Snyderd3f620b2010-01-06 13:34:04 +00001283 /*
1284 * Hookup the IRQ handler(s)
1285 *
1286 * If we have a per-controller interrupt, we prefer that to the
1287 * per-channel interrupts to reduce the number of shared interrupt
1288 * handlers on the same IRQ line
1289 */
1290 err = fsldma_request_irqs(fdev);
1291 if (err) {
1292 dev_err(fdev->dev, "unable to request IRQs\n");
1293 goto out_free_fdev;
1294 }
1295
Zhang Wei173acc72008-03-01 07:42:48 -07001296 dma_async_device_register(&fdev->common);
1297 return 0;
1298
Ira Snydere7a29152010-01-06 13:34:03 +00001299out_free_fdev:
Christophe JAILLETe165c112020-12-12 17:06:14 +01001300 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1301 if (fdev->chan[i])
1302 fsl_dma_chan_remove(fdev->chan[i]);
1303 }
Ira Snyderd3f620b2010-01-06 13:34:04 +00001304 irq_dispose_mapping(fdev->irq);
Arvind Yadav585a1db2016-09-28 16:15:11 +05301305 iounmap(fdev->regs);
1306out_free:
Zhang Wei173acc72008-03-01 07:42:48 -07001307 kfree(fdev);
Ira Snydere7a29152010-01-06 13:34:03 +00001308out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001309 return err;
1310}
1311
Grant Likely2dc11582010-08-06 09:25:50 -06001312static int fsldma_of_remove(struct platform_device *op)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001313{
Ira Snydera4f56d42010-01-06 13:34:01 +00001314 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001315 unsigned int i;
1316
Jingoo Handd3daca2013-05-24 10:10:13 +09001317 fdev = platform_get_drvdata(op);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001318 dma_async_device_unregister(&fdev->common);
1319
Ira Snyderd3f620b2010-01-06 13:34:04 +00001320 fsldma_free_irqs(fdev);
1321
Ira Snydere7a29152010-01-06 13:34:03 +00001322 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001323 if (fdev->chan[i])
1324 fsl_dma_chan_remove(fdev->chan[i]);
Ira Snydere7a29152010-01-06 13:34:03 +00001325 }
Christophe JAILLETa81149f2020-12-12 17:05:16 +01001326 irq_dispose_mapping(fdev->irq);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001327
Ira Snydere7a29152010-01-06 13:34:03 +00001328 iounmap(fdev->regs);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001329 kfree(fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001330
1331 return 0;
1332}
1333
Hongbo Zhang14c6a332014-05-21 16:03:02 +08001334#ifdef CONFIG_PM
1335static int fsldma_suspend_late(struct device *dev)
1336{
1337 struct platform_device *pdev = to_platform_device(dev);
1338 struct fsldma_device *fdev = platform_get_drvdata(pdev);
1339 struct fsldma_chan *chan;
1340 int i;
1341
1342 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1343 chan = fdev->chan[i];
1344 if (!chan)
1345 continue;
1346
1347 spin_lock_bh(&chan->desc_lock);
1348 if (unlikely(!chan->idle))
1349 goto out;
1350 chan->regs_save.mr = get_mr(chan);
1351 chan->pm_state = SUSPENDED;
1352 spin_unlock_bh(&chan->desc_lock);
1353 }
1354 return 0;
1355
1356out:
1357 for (; i >= 0; i--) {
1358 chan = fdev->chan[i];
1359 if (!chan)
1360 continue;
1361 chan->pm_state = RUNNING;
1362 spin_unlock_bh(&chan->desc_lock);
1363 }
1364 return -EBUSY;
1365}
1366
1367static int fsldma_resume_early(struct device *dev)
1368{
1369 struct platform_device *pdev = to_platform_device(dev);
1370 struct fsldma_device *fdev = platform_get_drvdata(pdev);
1371 struct fsldma_chan *chan;
1372 u32 mode;
1373 int i;
1374
1375 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1376 chan = fdev->chan[i];
1377 if (!chan)
1378 continue;
1379
1380 spin_lock_bh(&chan->desc_lock);
1381 mode = chan->regs_save.mr
1382 & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
1383 set_mr(chan, mode);
1384 chan->pm_state = RUNNING;
1385 spin_unlock_bh(&chan->desc_lock);
1386 }
1387
1388 return 0;
1389}
1390
1391static const struct dev_pm_ops fsldma_pm_ops = {
1392 .suspend_late = fsldma_suspend_late,
1393 .resume_early = fsldma_resume_early,
1394};
1395#endif
1396
Márton Németh4b1cf1f2010-02-02 23:41:06 -07001397static const struct of_device_id fsldma_of_ids[] = {
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001398 { .compatible = "fsl,elo3-dma", },
Kumar Gala049c9d42008-03-31 11:13:21 -05001399 { .compatible = "fsl,eloplus-dma", },
1400 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001401 {}
1402};
Luis de Bethencourt7522c242015-09-16 22:57:17 +02001403MODULE_DEVICE_TABLE(of, fsldma_of_ids);
Zhang Wei173acc72008-03-01 07:42:48 -07001404
Ira W. Snyder8faa7cf2011-04-07 10:33:03 -07001405static struct platform_driver fsldma_of_driver = {
Grant Likely40182942010-04-13 16:13:02 -07001406 .driver = {
1407 .name = "fsl-elo-dma",
Grant Likely40182942010-04-13 16:13:02 -07001408 .of_match_table = fsldma_of_ids,
Hongbo Zhang14c6a332014-05-21 16:03:02 +08001409#ifdef CONFIG_PM
1410 .pm = &fsldma_pm_ops,
1411#endif
Grant Likely40182942010-04-13 16:13:02 -07001412 },
1413 .probe = fsldma_of_probe,
1414 .remove = fsldma_of_remove,
Zhang Wei173acc72008-03-01 07:42:48 -07001415};
1416
Ira Snydera4f56d42010-01-06 13:34:01 +00001417/*----------------------------------------------------------------------------*/
1418/* Module Init / Exit */
1419/*----------------------------------------------------------------------------*/
1420
1421static __init int fsldma_init(void)
Zhang Wei173acc72008-03-01 07:42:48 -07001422{
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001423 pr_info("Freescale Elo series DMA driver\n");
Grant Likely00006122011-02-22 19:59:54 -07001424 return platform_driver_register(&fsldma_of_driver);
Zhang Wei173acc72008-03-01 07:42:48 -07001425}
1426
Ira Snydera4f56d42010-01-06 13:34:01 +00001427static void __exit fsldma_exit(void)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001428{
Grant Likely00006122011-02-22 19:59:54 -07001429 platform_driver_unregister(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001430}
1431
Ira Snydera4f56d42010-01-06 13:34:01 +00001432subsys_initcall(fsldma_init);
1433module_exit(fsldma_exit);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001434
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001435MODULE_DESCRIPTION("Freescale Elo series DMA driver");
Timur Tabi77cd62e2008-09-26 17:00:11 -07001436MODULE_LICENSE("GPL");