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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * include/asm-arm/arch-lh7a40x/entry-macro.S
3 *
4 * Low-level IRQ helper macros for LH7A40x platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
Russell King78ff18a2006-01-03 17:39:34 +000010#include <asm/hardware.h>
11#include <asm/arch/irqs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012
Marc Singer638b2662006-05-16 11:41:28 +010013/* In order to allow there to be support for both of the processor
14 classes at the same time, we make a hack here that isn't very
15 pretty. At startup, the link pointed to with the
16 branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
17 detected as a lh7a404.
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
Marc Singer638b2662006-05-16 11:41:28 +010019 *** FIXME: we should clean this up so that there is only one
20 implementation for each CPU's design.
21
22*/
23
24#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
25
26 .macro disable_fiq
27 .endm
28
Dan Williamsf80dff92007-02-16 22:16:32 +010029 .macro get_irqnr_preamble, base, tmp
30 .endm
31
32 .macro arch_ret_to_user, tmp1, tmp2
33 .endm
34
Marc Singer638b2662006-05-16 11:41:28 +010035 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
36
37branch_irq_lh7a400: b 1000f
38
39@ Implementation of the LH7A404 get_irqnr_and_base.
40
41 mov \irqnr, #0 @ VIC1 irq base
42 mov \base, #io_p2v(0x80000000) @ APB registers
43 add \base, \base, #0x8000
44 ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
45 tst \tmp, #VA_VECTORED @ Direct vectored
46 bne 1002f
47 tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
48 ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
49 bne 1001f
50 add \base, \base, #(0xa000 - 0x8000)
51 ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
52 tst \tmp, #VA_VECTORED @ Direct vectored
53 bne 1002f
54 ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
55 mov \irqnr, #32 @ VIC2 irq base
56
571001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
58 bcs 1008f @ Bit set; irq found
59 add \irqnr, \irqnr, #1
60 bne 1001b @ Until no bits
61 b 1009f @ Nothing? Hmm.
621002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
631008: movs \irqstat, #1 @ Force !Z
64 str \tmp, [\base, #0x0030] @ Clear vector
65 b 1009f
66
67@ Implementation of the LH7A400 get_irqnr_and_base.
68
691000: mov \irqnr, #0
70 mov \base, #io_p2v(0x80000000) @ APB registers
71 ldr \irqstat, [\base, #0x500] @ PIC INTSR
72
731001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
74 bcs 1008f @ Bit set; irq found
75 add \irqnr, \irqnr, #1
76 bne 1001b @ Until no bits
77 b 1009f @ Nothing? Hmm.
781008: movs \irqstat, #1 @ Force !Z
79
801009:
81 .endm
82
83
84
85#elif defined (CONFIG_ARCH_LH7A400)
Linus Torvalds1da177e2005-04-16 15:20:36 -070086 .macro disable_fiq
87 .endm
88
Dan Williams25613ca2007-03-06 23:46:36 +010089 .macro get_irqnr_preamble, base, tmp
90 .endm
91
92 .macro arch_ret_to_user, tmp1, tmp2
93 .endm
94
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
96 mov \irqnr, #0
97 mov \base, #io_p2v(0x80000000) @ APB registers
98 ldr \irqstat, [\base, #0x500] @ PIC INTSR
99
1001001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
101 bcs 1008f @ Bit set; irq found
102 add \irqnr, \irqnr, #1
103 bne 1001b @ Until no bits
104 b 1009f @ Nothing? Hmm.
1051008: movs \irqstat, #1 @ Force !Z
1061009:
107 .endm
108
109#elif defined(CONFIG_ARCH_LH7A404)
110
111 .macro disable_fiq
112 .endm
113
Dan Williams25613ca2007-03-06 23:46:36 +0100114 .macro get_irqnr_preamble, base, tmp
115 .endm
116
117 .macro arch_ret_to_user, tmp1, tmp2
118 .endm
119
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
121 mov \irqnr, #0 @ VIC1 irq base
122 mov \base, #io_p2v(0x80000000) @ APB registers
123 add \base, \base, #0x8000
124 ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
125 tst \tmp, #VA_VECTORED @ Direct vectored
126 bne 1002f
127 tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
128 ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
129 bne 1001f
130 add \base, \base, #(0xa000 - 0x8000)
131 ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
132 tst \tmp, #VA_VECTORED @ Direct vectored
133 bne 1002f
134 ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
135 mov \irqnr, #32 @ VIC2 irq base
136
1371001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
138 bcs 1008f @ Bit set; irq found
139 add \irqnr, \irqnr, #1
140 bne 1001b @ Until no bits
141 b 1009f @ Nothing? Hmm.
1421002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
1431008: movs \irqstat, #1 @ Force !Z
144 str \tmp, [\base, #0x0030] @ Clear vector
1451009:
146 .endm
147#endif
148
149