Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1 | /* |
| 2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers |
| 3 | * |
| 4 | * Copyright 2005 Tejun Heo |
| 5 | * |
| 6 | * Based on preview driver from Silicon Image. |
| 7 | * |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2, or (at your option) any |
| 11 | * later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/pci.h> |
| 23 | #include <linux/blkdev.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 27 | #include <linux/device.h> |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 28 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 29 | #include <scsi/scsi_cmnd.h> |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 30 | #include <linux/libata.h> |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 31 | |
| 32 | #define DRV_NAME "sata_sil24" |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 33 | #define DRV_VERSION "1.1" |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 34 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 35 | /* |
| 36 | * Port request block (PRB) 32 bytes |
| 37 | */ |
| 38 | struct sil24_prb { |
Alexey Dobriyan | b477257 | 2006-06-06 07:31:14 +0400 | [diff] [blame] | 39 | __le16 ctrl; |
| 40 | __le16 prot; |
| 41 | __le32 rx_cnt; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 42 | u8 fis[6 * 4]; |
| 43 | }; |
| 44 | |
| 45 | /* |
| 46 | * Scatter gather entry (SGE) 16 bytes |
| 47 | */ |
| 48 | struct sil24_sge { |
Alexey Dobriyan | b477257 | 2006-06-06 07:31:14 +0400 | [diff] [blame] | 49 | __le64 addr; |
| 50 | __le32 cnt; |
| 51 | __le32 flags; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 52 | }; |
| 53 | |
| 54 | /* |
| 55 | * Port multiplier |
| 56 | */ |
| 57 | struct sil24_port_multiplier { |
Alexey Dobriyan | b477257 | 2006-06-06 07:31:14 +0400 | [diff] [blame] | 58 | __le32 diag; |
| 59 | __le32 sactive; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 60 | }; |
| 61 | |
| 62 | enum { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 63 | SIL24_HOST_BAR = 0, |
| 64 | SIL24_PORT_BAR = 2, |
| 65 | |
Tejun Heo | 93e2618 | 2007-11-22 18:46:57 +0900 | [diff] [blame] | 66 | /* sil24 fetches in chunks of 64bytes. The first block |
| 67 | * contains the PRB and two SGEs. From the second block, it's |
| 68 | * consisted of four SGEs and called SGT. Calculate the |
| 69 | * number of SGTs that fit into one page. |
| 70 | */ |
| 71 | SIL24_PRB_SZ = sizeof(struct sil24_prb) |
| 72 | + 2 * sizeof(struct sil24_sge), |
| 73 | SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ) |
| 74 | / (4 * sizeof(struct sil24_sge)), |
| 75 | |
| 76 | /* This will give us one unused SGEs for ATA. This extra SGE |
| 77 | * will be used to store CDB for ATAPI devices. |
| 78 | */ |
| 79 | SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1, |
| 80 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 81 | /* |
| 82 | * Global controller registers (128 bytes @ BAR0) |
| 83 | */ |
| 84 | /* 32 bit regs */ |
| 85 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ |
| 86 | HOST_CTRL = 0x40, |
| 87 | HOST_IRQ_STAT = 0x44, |
| 88 | HOST_PHY_CFG = 0x48, |
| 89 | HOST_BIST_CTRL = 0x50, |
| 90 | HOST_BIST_PTRN = 0x54, |
| 91 | HOST_BIST_STAT = 0x58, |
| 92 | HOST_MEM_BIST_STAT = 0x5c, |
| 93 | HOST_FLASH_CMD = 0x70, |
| 94 | /* 8 bit regs */ |
| 95 | HOST_FLASH_DATA = 0x74, |
| 96 | HOST_TRANSITION_DETECT = 0x75, |
| 97 | HOST_GPIO_CTRL = 0x76, |
| 98 | HOST_I2C_ADDR = 0x78, /* 32 bit */ |
| 99 | HOST_I2C_DATA = 0x7c, |
| 100 | HOST_I2C_XFER_CNT = 0x7e, |
| 101 | HOST_I2C_CTRL = 0x7f, |
| 102 | |
| 103 | /* HOST_SLOT_STAT bits */ |
| 104 | HOST_SSTAT_ATTN = (1 << 31), |
| 105 | |
Tejun Heo | 7dafc3f | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 106 | /* HOST_CTRL bits */ |
| 107 | HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ |
| 108 | HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ |
| 109 | HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ |
| 110 | HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ |
| 111 | HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ |
Tejun Heo | d2298dc | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 112 | HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ |
Tejun Heo | 7dafc3f | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 113 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 114 | /* |
| 115 | * Port registers |
| 116 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) |
| 117 | */ |
| 118 | PORT_REGS_SIZE = 0x2000, |
Tejun Heo | 135da34 | 2006-05-31 18:27:57 +0900 | [diff] [blame] | 119 | |
Tejun Heo | 28c8f3b | 2006-10-16 08:47:18 +0900 | [diff] [blame] | 120 | PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ |
Tejun Heo | 135da34 | 2006-05-31 18:27:57 +0900 | [diff] [blame] | 121 | PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 122 | |
Tejun Heo | 28c8f3b | 2006-10-16 08:47:18 +0900 | [diff] [blame] | 123 | PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ |
Tejun Heo | c0c5590 | 2006-10-16 08:47:18 +0900 | [diff] [blame] | 124 | PORT_PMP_STATUS = 0x0000, /* port device status offset */ |
| 125 | PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ |
| 126 | PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ |
| 127 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 128 | /* 32 bit regs */ |
Tejun Heo | 83bbecc | 2005-08-17 13:09:18 +0900 | [diff] [blame] | 129 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
| 130 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ |
| 131 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ |
| 132 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ |
| 133 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 134 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
Tejun Heo | 83bbecc | 2005-08-17 13:09:18 +0900 | [diff] [blame] | 135 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
| 136 | PORT_CMD_ERR = 0x1024, /* command error number */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 137 | PORT_FIS_CFG = 0x1028, |
| 138 | PORT_FIFO_THRES = 0x102c, |
| 139 | /* 16 bit regs */ |
| 140 | PORT_DECODE_ERR_CNT = 0x1040, |
| 141 | PORT_DECODE_ERR_THRESH = 0x1042, |
| 142 | PORT_CRC_ERR_CNT = 0x1044, |
| 143 | PORT_CRC_ERR_THRESH = 0x1046, |
| 144 | PORT_HSHK_ERR_CNT = 0x1048, |
| 145 | PORT_HSHK_ERR_THRESH = 0x104a, |
| 146 | /* 32 bit regs */ |
| 147 | PORT_PHY_CFG = 0x1050, |
| 148 | PORT_SLOT_STAT = 0x1800, |
| 149 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ |
Tejun Heo | c0c5590 | 2006-10-16 08:47:18 +0900 | [diff] [blame] | 150 | PORT_CONTEXT = 0x1e04, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 151 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ |
| 152 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ |
| 153 | PORT_SCONTROL = 0x1f00, |
| 154 | PORT_SSTATUS = 0x1f04, |
| 155 | PORT_SERROR = 0x1f08, |
| 156 | PORT_SACTIVE = 0x1f0c, |
| 157 | |
| 158 | /* PORT_CTRL_STAT bits */ |
| 159 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ |
| 160 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ |
| 161 | PORT_CS_INIT = (1 << 2), /* port initialize */ |
| 162 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ |
Tejun Heo | d10cb35 | 2005-11-16 16:56:49 +0900 | [diff] [blame] | 163 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
Tejun Heo | 28c8f3b | 2006-10-16 08:47:18 +0900 | [diff] [blame] | 164 | PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ |
Tejun Heo | e382eb1 | 2005-08-17 13:09:13 +0900 | [diff] [blame] | 165 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ |
Tejun Heo | 28c8f3b | 2006-10-16 08:47:18 +0900 | [diff] [blame] | 166 | PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ |
Tejun Heo | e382eb1 | 2005-08-17 13:09:13 +0900 | [diff] [blame] | 167 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 168 | |
| 169 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ |
| 170 | /* bits[11:0] are masked */ |
| 171 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ |
| 172 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ |
| 173 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ |
| 174 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ |
| 175 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ |
| 176 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ |
Tejun Heo | 7dafc3f | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 177 | PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ |
| 178 | PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ |
| 179 | PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ |
| 180 | PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ |
| 181 | PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ |
Tejun Heo | 3b9f1d0 | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 182 | PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 183 | |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 184 | DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | |
Tejun Heo | 0542925 | 2006-05-31 18:28:20 +0900 | [diff] [blame] | 185 | PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | |
Tejun Heo | 854c73a | 2007-09-23 13:14:11 +0900 | [diff] [blame] | 186 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 187 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 188 | /* bits[27:16] are unmasked (raw) */ |
| 189 | PORT_IRQ_RAW_SHIFT = 16, |
| 190 | PORT_IRQ_MASKED_MASK = 0x7ff, |
| 191 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), |
| 192 | |
| 193 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ |
| 194 | PORT_IRQ_STEER_SHIFT = 30, |
| 195 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), |
| 196 | |
| 197 | /* PORT_CMD_ERR constants */ |
| 198 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ |
| 199 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ |
| 200 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ |
| 201 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ |
| 202 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ |
| 203 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ |
| 204 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ |
| 205 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ |
| 206 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ |
| 207 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ |
| 208 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ |
| 209 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ |
| 210 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ |
| 211 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ |
| 212 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ |
| 213 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ |
| 214 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ |
| 215 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ |
| 216 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ |
Tejun Heo | 6400880 | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 217 | PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 218 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ |
Tejun Heo | 83bbecc | 2005-08-17 13:09:18 +0900 | [diff] [blame] | 219 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 220 | |
Tejun Heo | d10cb35 | 2005-11-16 16:56:49 +0900 | [diff] [blame] | 221 | /* bits of PRB control field */ |
| 222 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ |
| 223 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ |
| 224 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ |
| 225 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ |
| 226 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ |
| 227 | |
| 228 | /* PRB protocol field */ |
| 229 | PRB_PROT_PACKET = (1 << 0), |
| 230 | PRB_PROT_TCQ = (1 << 1), |
| 231 | PRB_PROT_NCQ = (1 << 2), |
| 232 | PRB_PROT_READ = (1 << 3), |
| 233 | PRB_PROT_WRITE = (1 << 4), |
| 234 | PRB_PROT_TRANSPARENT = (1 << 5), |
| 235 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 236 | /* |
| 237 | * Other constants |
| 238 | */ |
| 239 | SGE_TRM = (1 << 31), /* Last SGE in chain */ |
Tejun Heo | d10cb35 | 2005-11-16 16:56:49 +0900 | [diff] [blame] | 240 | SGE_LNK = (1 << 30), /* linked list |
| 241 | Points to SGT, not SGE */ |
| 242 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) |
| 243 | data address ignored */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 244 | |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 245 | SIL24_MAX_CMDS = 31, |
| 246 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 247 | /* board id */ |
| 248 | BID_SIL3124 = 0, |
| 249 | BID_SIL3132 = 1, |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 250 | BID_SIL3131 = 2, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 251 | |
Tejun Heo | 9466d85 | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 252 | /* host flags */ |
| 253 | SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 254 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
Tejun Heo | 854c73a | 2007-09-23 13:14:11 +0900 | [diff] [blame] | 255 | ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA | |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 256 | ATA_FLAG_AN | ATA_FLAG_PMP, |
Tejun Heo | 37024e8 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 257 | SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ |
Tejun Heo | 9466d85 | 2006-04-11 22:32:18 +0900 | [diff] [blame] | 258 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 259 | IRQ_STAT_4PORTS = 0xf, |
| 260 | }; |
| 261 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 262 | struct sil24_ata_block { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 263 | struct sil24_prb prb; |
Tejun Heo | 93e2618 | 2007-11-22 18:46:57 +0900 | [diff] [blame] | 264 | struct sil24_sge sge[SIL24_MAX_SGE]; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 265 | }; |
| 266 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 267 | struct sil24_atapi_block { |
| 268 | struct sil24_prb prb; |
| 269 | u8 cdb[16]; |
Tejun Heo | 93e2618 | 2007-11-22 18:46:57 +0900 | [diff] [blame] | 270 | struct sil24_sge sge[SIL24_MAX_SGE]; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 271 | }; |
| 272 | |
| 273 | union sil24_cmd_block { |
| 274 | struct sil24_ata_block ata; |
| 275 | struct sil24_atapi_block atapi; |
| 276 | }; |
| 277 | |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 278 | static struct sil24_cerr_info { |
| 279 | unsigned int err_mask, action; |
| 280 | const char *desc; |
| 281 | } sil24_cerr_db[] = { |
Tejun Heo | f90f082 | 2007-10-26 16:12:41 +0900 | [diff] [blame] | 282 | [0] = { AC_ERR_DEV, 0, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 283 | "device error" }, |
Tejun Heo | f90f082 | 2007-10-26 16:12:41 +0900 | [diff] [blame] | 284 | [PORT_CERR_DEV] = { AC_ERR_DEV, 0, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 285 | "device error via D2H FIS" }, |
Tejun Heo | f90f082 | 2007-10-26 16:12:41 +0900 | [diff] [blame] | 286 | [PORT_CERR_SDB] = { AC_ERR_DEV, 0, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 287 | "device error via SDB FIS" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 288 | [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 289 | "error in data FIS" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 290 | [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 291 | "failed to transmit command FIS" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 292 | [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 293 | "protocol mismatch" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 294 | [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 295 | "data directon mismatch" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 296 | [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 297 | "ran out of SGEs while writing" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 298 | [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 299 | "ran out of SGEs while reading" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 300 | [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 301 | "invalid data directon for ATAPI CDB" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 302 | [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET, |
Tejun Heo | 7293fa8 | 2008-01-13 13:49:22 +0900 | [diff] [blame] | 303 | "SGT not on qword boundary" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 304 | [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 305 | "PCI target abort while fetching SGT" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 306 | [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 307 | "PCI master abort while fetching SGT" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 308 | [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 309 | "PCI parity error while fetching SGT" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 310 | [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 311 | "PRB not on qword boundary" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 312 | [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 313 | "PCI target abort while fetching PRB" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 314 | [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 315 | "PCI master abort while fetching PRB" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 316 | [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 317 | "PCI parity error while fetching PRB" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 318 | [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 319 | "undefined error while transferring data" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 320 | [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 321 | "PCI target abort while transferring data" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 322 | [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 323 | "PCI master abort while transferring data" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 324 | [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 325 | "PCI parity error while transferring data" }, |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 326 | [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 327 | "FIS received while sending service FIS" }, |
| 328 | }; |
| 329 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 330 | /* |
| 331 | * ap->private_data |
| 332 | * |
| 333 | * The preview driver always returned 0 for status. We emulate it |
| 334 | * here from the previous interrupt. |
| 335 | */ |
| 336 | struct sil24_port_priv { |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 337 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 338 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 339 | int do_port_rst; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 340 | }; |
| 341 | |
Alan | cd0d3bb | 2007-03-02 00:56:15 +0000 | [diff] [blame] | 342 | static void sil24_dev_config(struct ata_device *dev); |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 343 | static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val); |
| 344 | static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val); |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 345 | static int sil24_qc_defer(struct ata_queued_cmd *qc); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 346 | static void sil24_qc_prep(struct ata_queued_cmd *qc); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 347 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
Tejun Heo | 79f97da | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 348 | static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc); |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 349 | static void sil24_pmp_attach(struct ata_port *ap); |
| 350 | static void sil24_pmp_detach(struct ata_port *ap); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 351 | static void sil24_freeze(struct ata_port *ap); |
| 352 | static void sil24_thaw(struct ata_port *ap); |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 353 | static int sil24_softreset(struct ata_link *link, unsigned int *class, |
| 354 | unsigned long deadline); |
| 355 | static int sil24_hardreset(struct ata_link *link, unsigned int *class, |
| 356 | unsigned long deadline); |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 357 | static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, |
| 358 | unsigned long deadline); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 359 | static void sil24_error_handler(struct ata_port *ap); |
| 360 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 361 | static int sil24_port_start(struct ata_port *ap); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 362 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
Alexey Dobriyan | 281d426 | 2006-08-14 22:49:30 -0700 | [diff] [blame] | 363 | #ifdef CONFIG_PM |
Tejun Heo | d2298dc | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 364 | static int sil24_pci_device_resume(struct pci_dev *pdev); |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 365 | static int sil24_port_resume(struct ata_port *ap); |
Alexey Dobriyan | 281d426 | 2006-08-14 22:49:30 -0700 | [diff] [blame] | 366 | #endif |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 367 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 368 | static const struct pci_device_id sil24_pci_tbl[] = { |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 369 | { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, |
| 370 | { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, |
| 371 | { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, |
Jamie Clark | 722d67b | 2007-03-13 12:48:00 +0800 | [diff] [blame] | 372 | { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, |
Tejun Heo | 464b328 | 2008-07-02 17:50:23 +0900 | [diff] [blame] | 373 | { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 }, |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 374 | { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, |
| 375 | { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, |
| 376 | |
Tejun Heo | 1fcce839 | 2005-10-09 09:31:33 -0400 | [diff] [blame] | 377 | { } /* terminate list */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 378 | }; |
| 379 | |
| 380 | static struct pci_driver sil24_pci_driver = { |
| 381 | .name = DRV_NAME, |
| 382 | .id_table = sil24_pci_tbl, |
| 383 | .probe = sil24_init_one, |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 384 | .remove = ata_pci_remove_one, |
Alexey Dobriyan | 281d426 | 2006-08-14 22:49:30 -0700 | [diff] [blame] | 385 | #ifdef CONFIG_PM |
Tejun Heo | d2298dc | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 386 | .suspend = ata_pci_device_suspend, |
| 387 | .resume = sil24_pci_device_resume, |
Alexey Dobriyan | 281d426 | 2006-08-14 22:49:30 -0700 | [diff] [blame] | 388 | #endif |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 389 | }; |
| 390 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 391 | static struct scsi_host_template sil24_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 392 | ATA_NCQ_SHT(DRV_NAME), |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 393 | .can_queue = SIL24_MAX_CMDS, |
Tejun Heo | 93e2618 | 2007-11-22 18:46:57 +0900 | [diff] [blame] | 394 | .sg_tablesize = SIL24_MAX_SGE, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 395 | .dma_boundary = ATA_DMA_BOUNDARY, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 396 | }; |
| 397 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 398 | static struct ata_port_operations sil24_ops = { |
| 399 | .inherits = &sata_pmp_port_ops, |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 400 | |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 401 | .qc_defer = sil24_qc_defer, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 402 | .qc_prep = sil24_qc_prep, |
| 403 | .qc_issue = sil24_qc_issue, |
Tejun Heo | 79f97da | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 404 | .qc_fill_rtf = sil24_qc_fill_rtf, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 405 | |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 406 | .freeze = sil24_freeze, |
| 407 | .thaw = sil24_thaw, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 408 | .softreset = sil24_softreset, |
| 409 | .hardreset = sil24_hardreset, |
Tejun Heo | 071f44b | 2008-04-07 22:47:22 +0900 | [diff] [blame] | 410 | .pmp_softreset = sil24_softreset, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 411 | .pmp_hardreset = sil24_pmp_hardreset, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 412 | .error_handler = sil24_error_handler, |
| 413 | .post_internal_cmd = sil24_post_internal_cmd, |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 414 | .dev_config = sil24_dev_config, |
| 415 | |
| 416 | .scr_read = sil24_scr_read, |
| 417 | .scr_write = sil24_scr_write, |
| 418 | .pmp_attach = sil24_pmp_attach, |
| 419 | .pmp_detach = sil24_pmp_detach, |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 420 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 421 | .port_start = sil24_port_start, |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 422 | #ifdef CONFIG_PM |
| 423 | .port_resume = sil24_port_resume, |
| 424 | #endif |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 425 | }; |
| 426 | |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 427 | /* |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 428 | * Use bits 30-31 of port_flags to encode available port numbers. |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 429 | * Current maxium is 4. |
| 430 | */ |
| 431 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) |
| 432 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) |
| 433 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 434 | static const struct ata_port_info sil24_port_info[] = { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 435 | /* sil_3124 */ |
| 436 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 437 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | |
Tejun Heo | 37024e8 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 438 | SIL24_FLAG_PCIX_IRQ_WOC, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 439 | .pio_mask = 0x1f, /* pio0-4 */ |
| 440 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 441 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 442 | .port_ops = &sil24_ops, |
| 443 | }, |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 444 | /* sil_3132 */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 445 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 446 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 447 | .pio_mask = 0x1f, /* pio0-4 */ |
| 448 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 449 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 450 | .port_ops = &sil24_ops, |
| 451 | }, |
| 452 | /* sil_3131/sil_3531 */ |
| 453 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 454 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 455 | .pio_mask = 0x1f, /* pio0-4 */ |
| 456 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 457 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 458 | .port_ops = &sil24_ops, |
| 459 | }, |
| 460 | }; |
| 461 | |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 462 | static int sil24_tag(int tag) |
| 463 | { |
| 464 | if (unlikely(ata_tag_internal(tag))) |
| 465 | return 0; |
| 466 | return tag; |
| 467 | } |
| 468 | |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 469 | static unsigned long sil24_port_offset(struct ata_port *ap) |
| 470 | { |
| 471 | return ap->port_no * PORT_REGS_SIZE; |
| 472 | } |
| 473 | |
| 474 | static void __iomem *sil24_port_base(struct ata_port *ap) |
| 475 | { |
| 476 | return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap); |
| 477 | } |
| 478 | |
Alan | cd0d3bb | 2007-03-02 00:56:15 +0000 | [diff] [blame] | 479 | static void sil24_dev_config(struct ata_device *dev) |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 480 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 481 | void __iomem *port = sil24_port_base(dev->link->ap); |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 482 | |
Tejun Heo | 6e7846e | 2006-02-12 23:32:58 +0900 | [diff] [blame] | 483 | if (dev->cdb_len == 16) |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 484 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
| 485 | else |
| 486 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); |
| 487 | } |
| 488 | |
Tejun Heo | e59f0da | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 489 | static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf) |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 490 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 491 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | e59f0da | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 492 | struct sil24_prb __iomem *prb; |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 493 | u8 fis[6 * 4]; |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 494 | |
Tejun Heo | e59f0da | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 495 | prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ; |
| 496 | memcpy_fromio(fis, prb->fis, sizeof(fis)); |
| 497 | ata_tf_from_fis(fis, tf); |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 498 | } |
| 499 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 500 | static int sil24_scr_map[] = { |
| 501 | [SCR_CONTROL] = 0, |
| 502 | [SCR_STATUS] = 1, |
| 503 | [SCR_ERROR] = 2, |
| 504 | [SCR_ACTIVE] = 3, |
| 505 | }; |
| 506 | |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 507 | static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 508 | { |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 509 | void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 510 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 511 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 512 | void __iomem *addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 513 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 514 | *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4); |
| 515 | return 0; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 516 | } |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 517 | return -EINVAL; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 518 | } |
| 519 | |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 520 | static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 521 | { |
Tejun Heo | 82ef04f | 2008-07-31 17:02:40 +0900 | [diff] [blame] | 522 | void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 523 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 524 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 525 | void __iomem *addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 526 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
| 527 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 528 | return 0; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 529 | } |
Tejun Heo | da3dbb1 | 2007-07-16 14:29:40 +0900 | [diff] [blame] | 530 | return -EINVAL; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 531 | } |
| 532 | |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 533 | static void sil24_config_port(struct ata_port *ap) |
| 534 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 535 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 536 | |
| 537 | /* configure IRQ WoC */ |
| 538 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) |
| 539 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); |
| 540 | else |
| 541 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); |
| 542 | |
| 543 | /* zero error counters. */ |
| 544 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); |
| 545 | writel(0x8000, port + PORT_CRC_ERR_THRESH); |
| 546 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); |
| 547 | writel(0x0000, port + PORT_DECODE_ERR_CNT); |
| 548 | writel(0x0000, port + PORT_CRC_ERR_CNT); |
| 549 | writel(0x0000, port + PORT_HSHK_ERR_CNT); |
| 550 | |
| 551 | /* always use 64bit activation */ |
| 552 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); |
| 553 | |
| 554 | /* clear port multiplier enable and resume bits */ |
| 555 | writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); |
| 556 | } |
| 557 | |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 558 | static void sil24_config_pmp(struct ata_port *ap, int attached) |
| 559 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 560 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 561 | |
| 562 | if (attached) |
| 563 | writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT); |
| 564 | else |
| 565 | writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR); |
| 566 | } |
| 567 | |
| 568 | static void sil24_clear_pmp(struct ata_port *ap) |
| 569 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 570 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 571 | int i; |
| 572 | |
| 573 | writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); |
| 574 | |
| 575 | for (i = 0; i < SATA_PMP_MAX_PORTS; i++) { |
| 576 | void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE; |
| 577 | |
| 578 | writel(0, pmp_base + PORT_PMP_STATUS); |
| 579 | writel(0, pmp_base + PORT_PMP_QACTIVE); |
| 580 | } |
| 581 | } |
| 582 | |
Tejun Heo | b5bc421 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 583 | static int sil24_init_port(struct ata_port *ap) |
| 584 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 585 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 586 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | b5bc421 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 587 | u32 tmp; |
| 588 | |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 589 | /* clear PMP error status */ |
Tejun Heo | 071f44b | 2008-04-07 22:47:22 +0900 | [diff] [blame] | 590 | if (sata_pmp_attached(ap)) |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 591 | sil24_clear_pmp(ap); |
| 592 | |
Tejun Heo | b5bc421 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 593 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); |
| 594 | ata_wait_register(port + PORT_CTRL_STAT, |
| 595 | PORT_CS_INIT, PORT_CS_INIT, 10, 100); |
| 596 | tmp = ata_wait_register(port + PORT_CTRL_STAT, |
| 597 | PORT_CS_RDY, 0, 10, 100); |
| 598 | |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 599 | if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) { |
| 600 | pp->do_port_rst = 1; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 601 | ap->link.eh_context.i.action |= ATA_EH_RESET; |
Tejun Heo | b5bc421 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 602 | return -EIO; |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 603 | } |
| 604 | |
Tejun Heo | b5bc421 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 605 | return 0; |
| 606 | } |
| 607 | |
Tejun Heo | 37b99cb | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 608 | static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp, |
| 609 | const struct ata_taskfile *tf, |
| 610 | int is_cmd, u32 ctrl, |
| 611 | unsigned long timeout_msec) |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 612 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 613 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 614 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 615 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 616 | dma_addr_t paddr = pp->cmd_block_dma; |
Tejun Heo | 37b99cb | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 617 | u32 irq_enabled, irq_mask, irq_stat; |
| 618 | int rc; |
| 619 | |
| 620 | prb->ctrl = cpu_to_le16(ctrl); |
| 621 | ata_tf_to_fis(tf, pmp, is_cmd, prb->fis); |
| 622 | |
| 623 | /* temporarily plug completion and error interrupts */ |
| 624 | irq_enabled = readl(port + PORT_IRQ_ENABLE_SET); |
| 625 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR); |
| 626 | |
| 627 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
| 628 | writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); |
| 629 | |
| 630 | irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; |
| 631 | irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0, |
| 632 | 10, timeout_msec); |
| 633 | |
| 634 | writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */ |
| 635 | irq_stat >>= PORT_IRQ_RAW_SHIFT; |
| 636 | |
| 637 | if (irq_stat & PORT_IRQ_COMPLETE) |
| 638 | rc = 0; |
| 639 | else { |
| 640 | /* force port into known state */ |
| 641 | sil24_init_port(ap); |
| 642 | |
| 643 | if (irq_stat & PORT_IRQ_ERROR) |
| 644 | rc = -EIO; |
| 645 | else |
| 646 | rc = -EBUSY; |
| 647 | } |
| 648 | |
| 649 | /* restore IRQ enabled */ |
| 650 | writel(irq_enabled, port + PORT_IRQ_ENABLE_SET); |
| 651 | |
| 652 | return rc; |
| 653 | } |
| 654 | |
Tejun Heo | 071f44b | 2008-04-07 22:47:22 +0900 | [diff] [blame] | 655 | static int sil24_softreset(struct ata_link *link, unsigned int *class, |
| 656 | unsigned long deadline) |
Tejun Heo | 37b99cb | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 657 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 658 | struct ata_port *ap = link->ap; |
Tejun Heo | 071f44b | 2008-04-07 22:47:22 +0900 | [diff] [blame] | 659 | int pmp = sata_srst_pmp(link); |
Tejun Heo | 37b99cb | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 660 | unsigned long timeout_msec = 0; |
Tejun Heo | e59f0da | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 661 | struct ata_taskfile tf; |
Tejun Heo | 643be97 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 662 | const char *reason; |
Tejun Heo | 37b99cb | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 663 | int rc; |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 664 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 665 | DPRINTK("ENTER\n"); |
| 666 | |
Tejun Heo | 2555d6c | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 667 | /* put the port into known state */ |
| 668 | if (sil24_init_port(ap)) { |
Jeff Garzik | 5796d1c | 2007-10-26 00:03:37 -0400 | [diff] [blame] | 669 | reason = "port not ready"; |
Tejun Heo | 2555d6c | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 670 | goto err; |
| 671 | } |
| 672 | |
Tejun Heo | 0eaa605 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 673 | /* do SRST */ |
Tejun Heo | 37b99cb | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 674 | if (time_after(deadline, jiffies)) |
| 675 | timeout_msec = jiffies_to_msecs(deadline - jiffies); |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 676 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 677 | ata_tf_init(link->device, &tf); /* doesn't really matter */ |
Tejun Heo | 975530e | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 678 | rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST, |
| 679 | timeout_msec); |
Tejun Heo | 37b99cb | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 680 | if (rc == -EBUSY) { |
| 681 | reason = "timeout"; |
| 682 | goto err; |
| 683 | } else if (rc) { |
| 684 | reason = "SRST command error"; |
Tejun Heo | 643be97 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 685 | goto err; |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 686 | } |
Tejun Heo | 10d996a | 2006-03-11 11:42:34 +0900 | [diff] [blame] | 687 | |
Tejun Heo | e59f0da | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 688 | sil24_read_tf(ap, 0, &tf); |
| 689 | *class = ata_dev_classify(&tf); |
Tejun Heo | 10d996a | 2006-03-11 11:42:34 +0900 | [diff] [blame] | 690 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 691 | DPRINTK("EXIT, class=%u\n", *class); |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 692 | return 0; |
Tejun Heo | 643be97 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 693 | |
| 694 | err: |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 695 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
Tejun Heo | 643be97 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 696 | return -EIO; |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 697 | } |
| 698 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 699 | static int sil24_hardreset(struct ata_link *link, unsigned int *class, |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 700 | unsigned long deadline) |
Tejun Heo | 489ff4c | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 701 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 702 | struct ata_port *ap = link->ap; |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 703 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 704 | struct sil24_port_priv *pp = ap->private_data; |
| 705 | int did_port_rst = 0; |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 706 | const char *reason; |
Tejun Heo | e8e008e | 2006-05-31 18:27:59 +0900 | [diff] [blame] | 707 | int tout_msec, rc; |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 708 | u32 tmp; |
Tejun Heo | 489ff4c | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 709 | |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 710 | retry: |
| 711 | /* Sometimes, DEV_RST is not enough to recover the controller. |
| 712 | * This happens often after PM DMA CS errata. |
| 713 | */ |
| 714 | if (pp->do_port_rst) { |
| 715 | ata_port_printk(ap, KERN_WARNING, "controller in dubious " |
| 716 | "state, performing PORT_RST\n"); |
| 717 | |
| 718 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT); |
| 719 | msleep(10); |
| 720 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); |
| 721 | ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0, |
| 722 | 10, 5000); |
| 723 | |
| 724 | /* restore port configuration */ |
| 725 | sil24_config_port(ap); |
| 726 | sil24_config_pmp(ap, ap->nr_pmp_links); |
| 727 | |
| 728 | pp->do_port_rst = 0; |
| 729 | did_port_rst = 1; |
| 730 | } |
| 731 | |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 732 | /* sil24 does the right thing(tm) without any protection */ |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 733 | sata_set_spd(link); |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 734 | |
| 735 | tout_msec = 100; |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 736 | if (ata_link_online(link)) |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 737 | tout_msec = 5000; |
| 738 | |
| 739 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); |
| 740 | tmp = ata_wait_register(port + PORT_CTRL_STAT, |
Jeff Garzik | 5796d1c | 2007-10-26 00:03:37 -0400 | [diff] [blame] | 741 | PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, |
| 742 | tout_msec); |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 743 | |
Tejun Heo | e8e008e | 2006-05-31 18:27:59 +0900 | [diff] [blame] | 744 | /* SStatus oscillates between zero and valid status after |
| 745 | * DEV_RST, debounce it. |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 746 | */ |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 747 | rc = sata_link_debounce(link, sata_deb_timing_long, deadline); |
Tejun Heo | e8e008e | 2006-05-31 18:27:59 +0900 | [diff] [blame] | 748 | if (rc) { |
| 749 | reason = "PHY debouncing failed"; |
| 750 | goto err; |
| 751 | } |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 752 | |
| 753 | if (tmp & PORT_CS_DEV_RST) { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 754 | if (ata_link_offline(link)) |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 755 | return 0; |
| 756 | reason = "link not ready"; |
| 757 | goto err; |
| 758 | } |
| 759 | |
Tejun Heo | e8e008e | 2006-05-31 18:27:59 +0900 | [diff] [blame] | 760 | /* Sil24 doesn't store signature FIS after hardreset, so we |
| 761 | * can't wait for BSY to clear. Some devices take a long time |
| 762 | * to get ready and those devices will choke if we don't wait |
| 763 | * for BSY clearance here. Tell libata to perform follow-up |
| 764 | * softreset. |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 765 | */ |
Tejun Heo | e8e008e | 2006-05-31 18:27:59 +0900 | [diff] [blame] | 766 | return -EAGAIN; |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 767 | |
| 768 | err: |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 769 | if (!did_port_rst) { |
| 770 | pp->do_port_rst = 1; |
| 771 | goto retry; |
| 772 | } |
| 773 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 774 | ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason); |
Tejun Heo | ecc2e2b | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 775 | return -EIO; |
Tejun Heo | 489ff4c | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 776 | } |
| 777 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 778 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 779 | struct sil24_sge *sge) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 780 | { |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 781 | struct scatterlist *sg; |
Jeff Garzik | 3be6cbd | 2007-10-18 16:21:18 -0400 | [diff] [blame] | 782 | struct sil24_sge *last_sge = NULL; |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 783 | unsigned int si; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 784 | |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 785 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 786 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
| 787 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); |
Jeff Garzik | 3be6cbd | 2007-10-18 16:21:18 -0400 | [diff] [blame] | 788 | sge->flags = 0; |
| 789 | |
| 790 | last_sge = sge; |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 791 | sge++; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 792 | } |
Jeff Garzik | 3be6cbd | 2007-10-18 16:21:18 -0400 | [diff] [blame] | 793 | |
Tejun Heo | ff2aeb1 | 2007-12-05 16:43:11 +0900 | [diff] [blame] | 794 | last_sge->flags = cpu_to_le32(SGE_TRM); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 795 | } |
| 796 | |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 797 | static int sil24_qc_defer(struct ata_queued_cmd *qc) |
| 798 | { |
| 799 | struct ata_link *link = qc->dev->link; |
| 800 | struct ata_port *ap = link->ap; |
| 801 | u8 prot = qc->tf.protocol; |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 802 | |
Gwendal Grignou | 13cc546 | 2008-01-10 15:47:56 +0900 | [diff] [blame] | 803 | /* |
| 804 | * There is a bug in the chip: |
| 805 | * Port LRAM Causes the PRB/SGT Data to be Corrupted |
| 806 | * If the host issues a read request for LRAM and SActive registers |
| 807 | * while active commands are available in the port, PRB/SGT data in |
| 808 | * the LRAM can become corrupted. This issue applies only when |
| 809 | * reading from, but not writing to, the LRAM. |
| 810 | * |
| 811 | * Therefore, reading LRAM when there is no particular error [and |
| 812 | * other commands may be outstanding] is prohibited. |
| 813 | * |
| 814 | * To avoid this bug there are two situations where a command must run |
| 815 | * exclusive of any other commands on the port: |
| 816 | * |
| 817 | * - ATAPI commands which check the sense data |
| 818 | * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF |
| 819 | * set. |
| 820 | * |
| 821 | */ |
Tejun Heo | 405e66b | 2007-11-27 19:28:53 +0900 | [diff] [blame] | 822 | int is_excl = (ata_is_atapi(prot) || |
Gwendal Grignou | 13cc546 | 2008-01-10 15:47:56 +0900 | [diff] [blame] | 823 | (qc->flags & ATA_QCFLAG_RESULT_TF)); |
| 824 | |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 825 | if (unlikely(ap->excl_link)) { |
| 826 | if (link == ap->excl_link) { |
| 827 | if (ap->nr_active_links) |
| 828 | return ATA_DEFER_PORT; |
| 829 | qc->flags |= ATA_QCFLAG_CLEAR_EXCL; |
| 830 | } else |
| 831 | return ATA_DEFER_PORT; |
Gwendal Grignou | 13cc546 | 2008-01-10 15:47:56 +0900 | [diff] [blame] | 832 | } else if (unlikely(is_excl)) { |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 833 | ap->excl_link = link; |
| 834 | if (ap->nr_active_links) |
| 835 | return ATA_DEFER_PORT; |
| 836 | qc->flags |= ATA_QCFLAG_CLEAR_EXCL; |
| 837 | } |
| 838 | |
| 839 | return ata_std_qc_defer(qc); |
| 840 | } |
| 841 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 842 | static void sil24_qc_prep(struct ata_queued_cmd *qc) |
| 843 | { |
| 844 | struct ata_port *ap = qc->ap; |
| 845 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 846 | union sil24_cmd_block *cb; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 847 | struct sil24_prb *prb; |
| 848 | struct sil24_sge *sge; |
Tejun Heo | bad28a3 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 849 | u16 ctrl = 0; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 850 | |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 851 | cb = &pp->cmd_block[sil24_tag(qc->tag)]; |
| 852 | |
Tejun Heo | 405e66b | 2007-11-27 19:28:53 +0900 | [diff] [blame] | 853 | if (!ata_is_atapi(qc->tf.protocol)) { |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 854 | prb = &cb->ata.prb; |
| 855 | sge = cb->ata.sge; |
Tejun Heo | 405e66b | 2007-11-27 19:28:53 +0900 | [diff] [blame] | 856 | } else { |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 857 | prb = &cb->atapi.prb; |
| 858 | sge = cb->atapi.sge; |
| 859 | memset(cb->atapi.cdb, 0, 32); |
Tejun Heo | 6e7846e | 2006-02-12 23:32:58 +0900 | [diff] [blame] | 860 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 861 | |
Tejun Heo | 405e66b | 2007-11-27 19:28:53 +0900 | [diff] [blame] | 862 | if (ata_is_data(qc->tf.protocol)) { |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 863 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
Tejun Heo | bad28a3 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 864 | ctrl = PRB_CTRL_PACKET_WRITE; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 865 | else |
Tejun Heo | bad28a3 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 866 | ctrl = PRB_CTRL_PACKET_READ; |
| 867 | } |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 868 | } |
| 869 | |
Tejun Heo | bad28a3 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 870 | prb->ctrl = cpu_to_le16(ctrl); |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 871 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 872 | |
| 873 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 874 | sil24_fill_sg(qc, sge); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 875 | } |
| 876 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 877 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 878 | { |
| 879 | struct ata_port *ap = qc->ap; |
| 880 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 881 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 882 | unsigned int tag = sil24_tag(qc->tag); |
| 883 | dma_addr_t paddr; |
| 884 | void __iomem *activate; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 885 | |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 886 | paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); |
| 887 | activate = port + PORT_CMD_ACTIVATE + tag * 8; |
| 888 | |
| 889 | writel((u32)paddr, activate); |
| 890 | writel((u64)paddr >> 32, activate + 4); |
Tejun Heo | 26ec634 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 891 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 892 | return 0; |
| 893 | } |
| 894 | |
Tejun Heo | 79f97da | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 895 | static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc) |
| 896 | { |
| 897 | sil24_read_tf(qc->ap, qc->tag, &qc->result_tf); |
| 898 | return true; |
| 899 | } |
| 900 | |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 901 | static void sil24_pmp_attach(struct ata_port *ap) |
| 902 | { |
Tejun Heo | 906c1ff | 2008-05-19 01:15:13 +0900 | [diff] [blame] | 903 | u32 *gscr = ap->link.device->gscr; |
| 904 | |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 905 | sil24_config_pmp(ap, 1); |
| 906 | sil24_init_port(ap); |
Tejun Heo | 906c1ff | 2008-05-19 01:15:13 +0900 | [diff] [blame] | 907 | |
| 908 | if (sata_pmp_gscr_vendor(gscr) == 0x11ab && |
| 909 | sata_pmp_gscr_devid(gscr) == 0x4140) { |
| 910 | ata_port_printk(ap, KERN_INFO, |
| 911 | "disabling NCQ support due to sil24-mv4140 quirk\n"); |
| 912 | ap->flags &= ~ATA_FLAG_NCQ; |
| 913 | } |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 914 | } |
| 915 | |
| 916 | static void sil24_pmp_detach(struct ata_port *ap) |
| 917 | { |
| 918 | sil24_init_port(ap); |
| 919 | sil24_config_pmp(ap, 0); |
Tejun Heo | 906c1ff | 2008-05-19 01:15:13 +0900 | [diff] [blame] | 920 | |
| 921 | ap->flags |= ATA_FLAG_NCQ; |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 922 | } |
| 923 | |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 924 | static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, |
| 925 | unsigned long deadline) |
| 926 | { |
| 927 | int rc; |
| 928 | |
| 929 | rc = sil24_init_port(link->ap); |
| 930 | if (rc) { |
| 931 | ata_link_printk(link, KERN_ERR, |
| 932 | "hardreset failed (port not ready)\n"); |
| 933 | return rc; |
| 934 | } |
| 935 | |
Tejun Heo | 5958e30 | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 936 | return sata_std_hardreset(link, class, deadline); |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 937 | } |
| 938 | |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 939 | static void sil24_freeze(struct ata_port *ap) |
Tejun Heo | 7d1ce68 | 2005-11-18 14:09:05 +0900 | [diff] [blame] | 940 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 941 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 942 | |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 943 | /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear |
| 944 | * PORT_IRQ_ENABLE instead. |
Tejun Heo | c0ab424 | 2005-11-18 14:22:03 +0900 | [diff] [blame] | 945 | */ |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 946 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); |
| 947 | } |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 948 | |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 949 | static void sil24_thaw(struct ata_port *ap) |
| 950 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 951 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 952 | u32 tmp; |
| 953 | |
| 954 | /* clear IRQ */ |
| 955 | tmp = readl(port + PORT_IRQ_STAT); |
| 956 | writel(tmp, port + PORT_IRQ_STAT); |
| 957 | |
| 958 | /* turn IRQ back on */ |
| 959 | writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); |
| 960 | } |
| 961 | |
| 962 | static void sil24_error_intr(struct ata_port *ap) |
| 963 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 964 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | e59f0da | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 965 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 966 | struct ata_queued_cmd *qc = NULL; |
| 967 | struct ata_link *link; |
| 968 | struct ata_eh_info *ehi; |
| 969 | int abort = 0, freeze = 0; |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 970 | u32 irq_stat; |
| 971 | |
| 972 | /* on error, we need to clear IRQ explicitly */ |
| 973 | irq_stat = readl(port + PORT_IRQ_STAT); |
| 974 | writel(irq_stat, port + PORT_IRQ_STAT); |
| 975 | |
| 976 | /* first, analyze and record host port events */ |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 977 | link = &ap->link; |
| 978 | ehi = &link->eh_info; |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 979 | ata_ehi_clear_desc(ehi); |
| 980 | |
| 981 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); |
| 982 | |
Tejun Heo | 854c73a | 2007-09-23 13:14:11 +0900 | [diff] [blame] | 983 | if (irq_stat & PORT_IRQ_SDB_NOTIFY) { |
Tejun Heo | 854c73a | 2007-09-23 13:14:11 +0900 | [diff] [blame] | 984 | ata_ehi_push_desc(ehi, "SDB notify"); |
Tejun Heo | 7d77b24 | 2007-09-23 13:14:13 +0900 | [diff] [blame] | 985 | sata_async_notification(ap); |
Tejun Heo | 854c73a | 2007-09-23 13:14:11 +0900 | [diff] [blame] | 986 | } |
| 987 | |
Tejun Heo | 0542925 | 2006-05-31 18:28:20 +0900 | [diff] [blame] | 988 | if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { |
| 989 | ata_ehi_hotplugged(ehi); |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 990 | ata_ehi_push_desc(ehi, "%s", |
| 991 | irq_stat & PORT_IRQ_PHYRDY_CHG ? |
| 992 | "PHY RDY changed" : "device exchanged"); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 993 | freeze = 1; |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 994 | } |
| 995 | |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 996 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
| 997 | ehi->err_mask |= AC_ERR_HSM; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 998 | ehi->action |= ATA_EH_RESET; |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 999 | ata_ehi_push_desc(ehi, "unknown FIS"); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1000 | freeze = 1; |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 1001 | } |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1002 | |
| 1003 | /* deal with command error */ |
| 1004 | if (irq_stat & PORT_IRQ_ERROR) { |
| 1005 | struct sil24_cerr_info *ci = NULL; |
| 1006 | unsigned int err_mask = 0, action = 0; |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1007 | u32 context, cerr; |
| 1008 | int pmp; |
| 1009 | |
| 1010 | abort = 1; |
| 1011 | |
| 1012 | /* DMA Context Switch Failure in Port Multiplier Mode |
| 1013 | * errata. If we have active commands to 3 or more |
| 1014 | * devices, any error condition on active devices can |
| 1015 | * corrupt DMA context switching. |
| 1016 | */ |
| 1017 | if (ap->nr_active_links >= 3) { |
| 1018 | ehi->err_mask |= AC_ERR_OTHER; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1019 | ehi->action |= ATA_EH_RESET; |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1020 | ata_ehi_push_desc(ehi, "PMP DMA CS errata"); |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1021 | pp->do_port_rst = 1; |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1022 | freeze = 1; |
| 1023 | } |
| 1024 | |
| 1025 | /* find out the offending link and qc */ |
Tejun Heo | 071f44b | 2008-04-07 22:47:22 +0900 | [diff] [blame] | 1026 | if (sata_pmp_attached(ap)) { |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1027 | context = readl(port + PORT_CONTEXT); |
| 1028 | pmp = (context >> 5) & 0xf; |
| 1029 | |
| 1030 | if (pmp < ap->nr_pmp_links) { |
| 1031 | link = &ap->pmp_link[pmp]; |
| 1032 | ehi = &link->eh_info; |
| 1033 | qc = ata_qc_from_tag(ap, link->active_tag); |
| 1034 | |
| 1035 | ata_ehi_clear_desc(ehi); |
| 1036 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", |
| 1037 | irq_stat); |
| 1038 | } else { |
| 1039 | err_mask |= AC_ERR_HSM; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1040 | action |= ATA_EH_RESET; |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1041 | freeze = 1; |
| 1042 | } |
| 1043 | } else |
| 1044 | qc = ata_qc_from_tag(ap, link->active_tag); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1045 | |
| 1046 | /* analyze CMD_ERR */ |
| 1047 | cerr = readl(port + PORT_CMD_ERR); |
| 1048 | if (cerr < ARRAY_SIZE(sil24_cerr_db)) |
| 1049 | ci = &sil24_cerr_db[cerr]; |
| 1050 | |
| 1051 | if (ci && ci->desc) { |
| 1052 | err_mask |= ci->err_mask; |
| 1053 | action |= ci->action; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1054 | if (action & ATA_EH_RESET) |
Tejun Heo | c2e14f1 | 2008-01-13 14:04:16 +0900 | [diff] [blame] | 1055 | freeze = 1; |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1056 | ata_ehi_push_desc(ehi, "%s", ci->desc); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1057 | } else { |
| 1058 | err_mask |= AC_ERR_OTHER; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1059 | action |= ATA_EH_RESET; |
Tejun Heo | c2e14f1 | 2008-01-13 14:04:16 +0900 | [diff] [blame] | 1060 | freeze = 1; |
Tejun Heo | b64bbc3 | 2007-07-16 14:29:39 +0900 | [diff] [blame] | 1061 | ata_ehi_push_desc(ehi, "unknown command error %d", |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1062 | cerr); |
| 1063 | } |
| 1064 | |
| 1065 | /* record error info */ |
Tejun Heo | 520d06f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 1066 | if (qc) |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1067 | qc->err_mask |= err_mask; |
Tejun Heo | 520d06f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 1068 | else |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1069 | ehi->err_mask |= err_mask; |
| 1070 | |
| 1071 | ehi->action |= action; |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1072 | |
| 1073 | /* if PMP, resume */ |
Tejun Heo | 071f44b | 2008-04-07 22:47:22 +0900 | [diff] [blame] | 1074 | if (sata_pmp_attached(ap)) |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1075 | writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1076 | } |
| 1077 | |
| 1078 | /* freeze or abort */ |
| 1079 | if (freeze) |
| 1080 | ata_port_freeze(ap); |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1081 | else if (abort) { |
| 1082 | if (qc) |
| 1083 | ata_link_abort(qc->dev->link); |
| 1084 | else |
| 1085 | ata_port_abort(ap); |
| 1086 | } |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 1087 | } |
| 1088 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1089 | static inline void sil24_host_intr(struct ata_port *ap) |
| 1090 | { |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 1091 | void __iomem *port = sil24_port_base(ap); |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 1092 | u32 slot_stat, qc_active; |
| 1093 | int rc; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1094 | |
Tejun Heo | 228f47b | 2007-09-23 12:37:05 +0900 | [diff] [blame] | 1095 | /* If PCIX_IRQ_WOC, there's an inherent race window between |
| 1096 | * clearing IRQ pending status and reading PORT_SLOT_STAT |
| 1097 | * which may cause spurious interrupts afterwards. This is |
| 1098 | * unavoidable and much better than losing interrupts which |
| 1099 | * happens if IRQ pending is cleared after reading |
| 1100 | * PORT_SLOT_STAT. |
| 1101 | */ |
| 1102 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) |
| 1103 | writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); |
| 1104 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1105 | slot_stat = readl(port + PORT_SLOT_STAT); |
Tejun Heo | 37024e8 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 1106 | |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1107 | if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { |
| 1108 | sil24_error_intr(ap); |
| 1109 | return; |
| 1110 | } |
Tejun Heo | 37024e8 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 1111 | |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 1112 | qc_active = slot_stat & ~HOST_SSTAT_ATTN; |
Tejun Heo | 79f97da | 2008-04-07 22:47:20 +0900 | [diff] [blame] | 1113 | rc = ata_qc_complete_multiple(ap, qc_active); |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 1114 | if (rc > 0) |
| 1115 | return; |
| 1116 | if (rc < 0) { |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1117 | struct ata_eh_info *ehi = &ap->link.eh_info; |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 1118 | ehi->err_mask |= AC_ERR_HSM; |
Tejun Heo | cf48062 | 2008-01-24 00:05:14 +0900 | [diff] [blame] | 1119 | ehi->action |= ATA_EH_RESET; |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 1120 | ata_port_freeze(ap); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1121 | return; |
| 1122 | } |
| 1123 | |
Tejun Heo | 228f47b | 2007-09-23 12:37:05 +0900 | [diff] [blame] | 1124 | /* spurious interrupts are expected if PCIX_IRQ_WOC */ |
| 1125 | if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit()) |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1126 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 1127 | "(slot_stat 0x%x active_tag %d sactive 0x%x)\n", |
Tejun Heo | 9af5c9c | 2007-08-06 18:36:22 +0900 | [diff] [blame] | 1128 | slot_stat, ap->link.active_tag, ap->link.sactive); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1129 | } |
| 1130 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1131 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1132 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1133 | struct ata_host *host = dev_instance; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1134 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1135 | unsigned handled = 0; |
| 1136 | u32 status; |
| 1137 | int i; |
| 1138 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1139 | status = readl(host_base + HOST_IRQ_STAT); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1140 | |
Tejun Heo | 06460ae | 2005-08-17 13:08:52 +0900 | [diff] [blame] | 1141 | if (status == 0xffffffff) { |
| 1142 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " |
| 1143 | "PCI fault or device removal?\n"); |
| 1144 | goto out; |
| 1145 | } |
| 1146 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1147 | if (!(status & IRQ_STAT_4PORTS)) |
| 1148 | goto out; |
| 1149 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1150 | spin_lock(&host->lock); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1151 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1152 | for (i = 0; i < host->n_ports; i++) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1153 | if (status & (1 << i)) { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1154 | struct ata_port *ap = host->ports[i]; |
Tejun Heo | 198e0fe | 2006-04-02 18:51:52 +0900 | [diff] [blame] | 1155 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { |
Mikael Pettersson | 825cd6d | 2007-07-03 01:10:25 +0200 | [diff] [blame] | 1156 | sil24_host_intr(ap); |
Tejun Heo | 3cc4571 | 2005-08-17 13:08:47 +0900 | [diff] [blame] | 1157 | handled++; |
| 1158 | } else |
| 1159 | printk(KERN_ERR DRV_NAME |
| 1160 | ": interrupt from disabled port %d\n", i); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1161 | } |
| 1162 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1163 | spin_unlock(&host->lock); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1164 | out: |
| 1165 | return IRQ_RETVAL(handled); |
| 1166 | } |
| 1167 | |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1168 | static void sil24_error_handler(struct ata_port *ap) |
| 1169 | { |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1170 | struct sil24_port_priv *pp = ap->private_data; |
| 1171 | |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1172 | if (sil24_init_port(ap)) |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1173 | ata_eh_freeze_port(ap); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1174 | |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 1175 | sata_pmp_error_handler(ap); |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1176 | |
| 1177 | pp->do_port_rst = 0; |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1178 | } |
| 1179 | |
| 1180 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) |
| 1181 | { |
| 1182 | struct ata_port *ap = qc->ap; |
| 1183 | |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1184 | /* make DMA engine forget about the failed command */ |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1185 | if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap)) |
| 1186 | ata_eh_freeze_port(ap); |
Tejun Heo | 88ce755 | 2006-05-15 20:58:32 +0900 | [diff] [blame] | 1187 | } |
| 1188 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1189 | static int sil24_port_start(struct ata_port *ap) |
| 1190 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1191 | struct device *dev = ap->host->dev; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1192 | struct sil24_port_priv *pp; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 1193 | union sil24_cmd_block *cb; |
Tejun Heo | aee10a0 | 2006-05-15 21:03:56 +0900 | [diff] [blame] | 1194 | size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1195 | dma_addr_t cb_dma; |
| 1196 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1197 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1198 | if (!pp) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1199 | return -ENOMEM; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1200 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1201 | cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 1202 | if (!cb) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1203 | return -ENOMEM; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1204 | memset(cb, 0, cb_size); |
| 1205 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1206 | pp->cmd_block = cb; |
| 1207 | pp->cmd_block_dma = cb_dma; |
| 1208 | |
| 1209 | ap->private_data = pp; |
| 1210 | |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 1211 | ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host"); |
| 1212 | ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port"); |
| 1213 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1214 | return 0; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1215 | } |
| 1216 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1217 | static void sil24_init_controller(struct ata_host *host) |
Tejun Heo | 2a41a61 | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1218 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1219 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
Tejun Heo | 2a41a61 | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1220 | u32 tmp; |
| 1221 | int i; |
| 1222 | |
| 1223 | /* GPIO off */ |
| 1224 | writel(0, host_base + HOST_FLASH_CMD); |
| 1225 | |
| 1226 | /* clear global reset & mask interrupts during initialization */ |
| 1227 | writel(0, host_base + HOST_CTRL); |
| 1228 | |
| 1229 | /* init ports */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1230 | for (i = 0; i < host->n_ports; i++) { |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1231 | struct ata_port *ap = host->ports[i]; |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 1232 | void __iomem *port = sil24_port_base(ap); |
| 1233 | |
Tejun Heo | 2a41a61 | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1234 | |
| 1235 | /* Initial PHY setting */ |
| 1236 | writel(0x20c, port + PORT_PHY_CFG); |
| 1237 | |
| 1238 | /* Clear port RST */ |
| 1239 | tmp = readl(port + PORT_CTRL_STAT); |
| 1240 | if (tmp & PORT_CS_PORT_RST) { |
| 1241 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); |
| 1242 | tmp = ata_wait_register(port + PORT_CTRL_STAT, |
| 1243 | PORT_CS_PORT_RST, |
| 1244 | PORT_CS_PORT_RST, 10, 100); |
| 1245 | if (tmp & PORT_CS_PORT_RST) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1246 | dev_printk(KERN_ERR, host->dev, |
Jeff Garzik | 5796d1c | 2007-10-26 00:03:37 -0400 | [diff] [blame] | 1247 | "failed to clear port RST\n"); |
Tejun Heo | 2a41a61 | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1248 | } |
| 1249 | |
Tejun Heo | 2381803 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1250 | /* configure port */ |
| 1251 | sil24_config_port(ap); |
Tejun Heo | 2a41a61 | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1252 | } |
| 1253 | |
| 1254 | /* Turn on interrupts */ |
| 1255 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); |
| 1256 | } |
| 1257 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1258 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 1259 | { |
Tejun Heo | 93e2618 | 2007-11-22 18:46:57 +0900 | [diff] [blame] | 1260 | extern int __MARKER__sil24_cmd_block_is_sized_wrongly; |
Jeff Garzik | 5796d1c | 2007-10-26 00:03:37 -0400 | [diff] [blame] | 1261 | static int printed_version; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1262 | struct ata_port_info pi = sil24_port_info[ent->driver_data]; |
| 1263 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
| 1264 | void __iomem * const *iomap; |
| 1265 | struct ata_host *host; |
Tejun Heo | 350756f | 2008-04-07 22:47:21 +0900 | [diff] [blame] | 1266 | int rc; |
Tejun Heo | 37024e8 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 1267 | u32 tmp; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1268 | |
Tejun Heo | 93e2618 | 2007-11-22 18:46:57 +0900 | [diff] [blame] | 1269 | /* cause link error if sil24_cmd_block is sized wrongly */ |
| 1270 | if (sizeof(union sil24_cmd_block) != PAGE_SIZE) |
| 1271 | __MARKER__sil24_cmd_block_is_sized_wrongly = 1; |
| 1272 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1273 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1274 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1275 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1276 | /* acquire resources */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1277 | rc = pcim_enable_device(pdev); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1278 | if (rc) |
| 1279 | return rc; |
| 1280 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1281 | rc = pcim_iomap_regions(pdev, |
| 1282 | (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), |
| 1283 | DRV_NAME); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1284 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1285 | return rc; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1286 | iomap = pcim_iomap_table(pdev); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1287 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1288 | /* apply workaround for completion IRQ loss on PCI-X errata */ |
| 1289 | if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) { |
| 1290 | tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL); |
| 1291 | if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) |
| 1292 | dev_printk(KERN_INFO, &pdev->dev, |
| 1293 | "Applying completion IRQ loss on PCI-X " |
| 1294 | "errata fix\n"); |
| 1295 | else |
| 1296 | pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; |
| 1297 | } |
| 1298 | |
| 1299 | /* allocate and fill host */ |
| 1300 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, |
| 1301 | SIL24_FLAG2NPORTS(ppi[0]->flags)); |
| 1302 | if (!host) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1303 | return -ENOMEM; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1304 | host->iomap = iomap; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1305 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1306 | /* configure and activate the device */ |
Tejun Heo | 26ec634 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 1307 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 1308 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 1309 | if (rc) { |
| 1310 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1311 | if (rc) { |
| 1312 | dev_printk(KERN_ERR, &pdev->dev, |
| 1313 | "64-bit DMA enable failed\n"); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1314 | return rc; |
Tejun Heo | 26ec634 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 1315 | } |
| 1316 | } |
| 1317 | } else { |
| 1318 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 1319 | if (rc) { |
| 1320 | dev_printk(KERN_ERR, &pdev->dev, |
| 1321 | "32-bit DMA enable failed\n"); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1322 | return rc; |
Tejun Heo | 26ec634 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 1323 | } |
| 1324 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1325 | if (rc) { |
| 1326 | dev_printk(KERN_ERR, &pdev->dev, |
| 1327 | "32-bit consistent DMA enable failed\n"); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1328 | return rc; |
Tejun Heo | 26ec634 | 2006-04-11 22:32:19 +0900 | [diff] [blame] | 1329 | } |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1330 | } |
| 1331 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1332 | sil24_init_controller(host); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1333 | |
| 1334 | pci_set_master(pdev); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1335 | return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED, |
| 1336 | &sil24_sht); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1337 | } |
| 1338 | |
Alexey Dobriyan | 281d426 | 2006-08-14 22:49:30 -0700 | [diff] [blame] | 1339 | #ifdef CONFIG_PM |
Tejun Heo | d2298dc | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1340 | static int sil24_pci_device_resume(struct pci_dev *pdev) |
| 1341 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1342 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1343 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
Tejun Heo | 553c4aa | 2006-12-26 19:39:50 +0900 | [diff] [blame] | 1344 | int rc; |
Tejun Heo | d2298dc | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1345 | |
Tejun Heo | 553c4aa | 2006-12-26 19:39:50 +0900 | [diff] [blame] | 1346 | rc = ata_pci_device_do_resume(pdev); |
| 1347 | if (rc) |
| 1348 | return rc; |
Tejun Heo | d2298dc | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1349 | |
| 1350 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1351 | writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); |
Tejun Heo | d2298dc | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1352 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1353 | sil24_init_controller(host); |
Tejun Heo | d2298dc | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1354 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1355 | ata_host_resume(host); |
Tejun Heo | d2298dc | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1356 | |
| 1357 | return 0; |
| 1358 | } |
Tejun Heo | 3454dc6 | 2007-09-23 13:19:54 +0900 | [diff] [blame] | 1359 | |
| 1360 | static int sil24_port_resume(struct ata_port *ap) |
| 1361 | { |
| 1362 | sil24_config_pmp(ap, ap->nr_pmp_links); |
| 1363 | return 0; |
| 1364 | } |
Alexey Dobriyan | 281d426 | 2006-08-14 22:49:30 -0700 | [diff] [blame] | 1365 | #endif |
Tejun Heo | d2298dc | 2006-07-03 16:07:27 +0900 | [diff] [blame] | 1366 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1367 | static int __init sil24_init(void) |
| 1368 | { |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 1369 | return pci_register_driver(&sil24_pci_driver); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1370 | } |
| 1371 | |
| 1372 | static void __exit sil24_exit(void) |
| 1373 | { |
| 1374 | pci_unregister_driver(&sil24_pci_driver); |
| 1375 | } |
| 1376 | |
| 1377 | MODULE_AUTHOR("Tejun Heo"); |
| 1378 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); |
| 1379 | MODULE_LICENSE("GPL"); |
| 1380 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); |
| 1381 | |
| 1382 | module_init(sil24_init); |
| 1383 | module_exit(sil24_exit); |