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| author | 2017-06-17 19:57:27 -0700 | |
|---|---|---|
| committer | 2017-07-19 15:03:10 -0700 | |
| commit | 4147fcc43c2ee019a06e55384985e3eaf82dcb8c (patch) | |
| tree | 11ec92efbfddf7736bbc74ed35fcfb3756bfcfb0 /compiler/utils/mips64/assembler_mips64.h | |
| parent | e8f48da635c4d07bbe431e5819da8e1fad91a8ef (diff) | |
MIPS: Reduce Baker read barrier code size overhead
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: test-art-target-gtest
Test: testrunner.py --target --optimizing
Test: same tests as above on CI20
Test: booted MIPS32 and MIPS64 in QEMU with poisoning
in configurations:
- with Baker read barrier thunks
- without Baker read barrier thunks
- ART_READ_BARRIER_TYPE=TABLELOOKUP
Change-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2
Diffstat (limited to 'compiler/utils/mips64/assembler_mips64.h')
| -rw-r--r-- | compiler/utils/mips64/assembler_mips64.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h index 773db9b208..5e88033743 100644 --- a/compiler/utils/mips64/assembler_mips64.h +++ b/compiler/utils/mips64/assembler_mips64.h @@ -563,6 +563,7 @@ class Mips64Assembler FINAL : public Assembler, public JNIMacroAssembler<Pointer void Bnezc(GpuRegister rs, uint32_t imm21); void Bc1eqz(FpuRegister ft, uint16_t imm16); void Bc1nez(FpuRegister ft, uint16_t imm16); + void Beqz(GpuRegister rt, uint16_t imm16); void AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft); void SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft); |