From 4147fcc43c2ee019a06e55384985e3eaf82dcb8c Mon Sep 17 00:00:00 2001
From: Alexey Frunze <Alexey.Frunze@imgtec.com>
Date: Sat, 17 Jun 2017 19:57:27 -0700
Subject: MIPS: Reduce Baker read barrier code size overhead

Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: test-art-target-gtest
Test: testrunner.py --target --optimizing
Test: same tests as above on CI20
Test: booted MIPS32 and MIPS64 in QEMU with poisoning
      in configurations:
      - with Baker read barrier thunks
      - without Baker read barrier thunks
      - ART_READ_BARRIER_TYPE=TABLELOOKUP

Change-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2
---
 compiler/utils/mips64/assembler_mips64.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'compiler/utils/mips64/assembler_mips64.h')

diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h
index 773db9b208..5e88033743 100644
--- a/compiler/utils/mips64/assembler_mips64.h
+++ b/compiler/utils/mips64/assembler_mips64.h
@@ -563,6 +563,7 @@ class Mips64Assembler FINAL : public Assembler, public JNIMacroAssembler<Pointer
   void Bnezc(GpuRegister rs, uint32_t imm21);
   void Bc1eqz(FpuRegister ft, uint16_t imm16);
   void Bc1nez(FpuRegister ft, uint16_t imm16);
+  void Beqz(GpuRegister rt, uint16_t imm16);
 
   void AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
   void SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
-- 
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