diff options
| author | 2017-02-21 18:10:26 +0000 | |
|---|---|---|
| committer | 2017-07-18 20:19:58 +0100 | |
| commit | 420ee30f4c0f8a5bb6048df4fa27e5432ded893b (patch) | |
| tree | fd72cba9ed09cf78e9377677fd144821fd9f6743 /compiler/optimizing/scheduler_arm.cc | |
| parent | 2f0ac4fb4486e7d9e5c1545d45a2b9b818a80dc3 (diff) | |
ARM: VIXL32: Merge (un)signed extensions and integer additions
Test: m test-art-target-run-test-551-checker-shifter-operand
Change-Id: I041e80e51bf0954b38ab20dfa9b14aa7f6d6c53b
Diffstat (limited to 'compiler/optimizing/scheduler_arm.cc')
| -rw-r--r-- | compiler/optimizing/scheduler_arm.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/compiler/optimizing/scheduler_arm.cc b/compiler/optimizing/scheduler_arm.cc index e78cd78aa2..627ab4e2da 100644 --- a/compiler/optimizing/scheduler_arm.cc +++ b/compiler/optimizing/scheduler_arm.cc @@ -269,7 +269,6 @@ void SchedulingLatencyVisitorARM::VisitDataProcWithShifterOp(HDataProcWithShifte const HDataProcWithShifterOp::OpKind op_kind = instruction->GetOpKind(); if (instruction->GetType() == Primitive::kPrimInt) { - DCHECK(!HDataProcWithShifterOp::IsExtensionOp(op_kind)); HandleGenerateDataProcInstruction(); } else { DCHECK_EQ(instruction->GetType(), Primitive::kPrimLong); |