From 420ee30f4c0f8a5bb6048df4fa27e5432ded893b Mon Sep 17 00:00:00 2001
From: Anton Kirilov <anton.kirilov@linaro.org>
Date: Tue, 21 Feb 2017 18:10:26 +0000
Subject: ARM: VIXL32: Merge (un)signed extensions and integer additions

Test: m test-art-target-run-test-551-checker-shifter-operand
Change-Id: I041e80e51bf0954b38ab20dfa9b14aa7f6d6c53b
---
 compiler/optimizing/scheduler_arm.cc | 1 -
 1 file changed, 1 deletion(-)

(limited to 'compiler/optimizing/scheduler_arm.cc')

diff --git a/compiler/optimizing/scheduler_arm.cc b/compiler/optimizing/scheduler_arm.cc
index e78cd78aa2..627ab4e2da 100644
--- a/compiler/optimizing/scheduler_arm.cc
+++ b/compiler/optimizing/scheduler_arm.cc
@@ -269,7 +269,6 @@ void SchedulingLatencyVisitorARM::VisitDataProcWithShifterOp(HDataProcWithShifte
   const HDataProcWithShifterOp::OpKind op_kind = instruction->GetOpKind();
 
   if (instruction->GetType() == Primitive::kPrimInt) {
-    DCHECK(!HDataProcWithShifterOp::IsExtensionOp(op_kind));
     HandleGenerateDataProcInstruction();
   } else {
     DCHECK_EQ(instruction->GetType(), Primitive::kPrimLong);
-- 
cgit v1.2.3-59-g8ed1b