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| author | 2017-02-09 19:08:30 -0800 | |
|---|---|---|
| committer | 2017-03-28 23:35:34 -0700 | |
| commit | 1595815c2a914a78df7dfb6f0082f47d4e82bb36 (patch) | |
| tree | 8fd53c3c91158b33e744e43cc655b2e2a180a3fc /compiler/optimizing/optimizing_compiler.cc | |
| parent | 4ba18fdfc2581a2328ab745c2707e3ed375d9e64 (diff) | |
MIPS: Implement read barriers.
This is the core functionality. Further improvements
will be done separately.
This also adds/moves memory barriers where they belong and
removes the UnsafeGetLongVolatile and UnsafePutLongVolatile
MIPS32 intrinsics as they need to load/store a pair of
registers atomically, which is not supported directly by
the CPU.
Test: booted MIPS32R2 in QEMU
Test: test-art-target-run-test
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: "testrunner.py --target --optimizing -j1"
Test: same MIPS64 boot/test with ART_READ_BARRIER_TYPE=TABLELOOKUP
Test: "testrunner.py --target --optimizing --32 -j2" on CI20
Test: same CI20 test with ART_READ_BARRIER_TYPE=TABLELOOKUP
Change-Id: I0ff91525fefba3ec1cc019f50316478a888acced
Diffstat (limited to 'compiler/optimizing/optimizing_compiler.cc')
| -rw-r--r-- | compiler/optimizing/optimizing_compiler.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/compiler/optimizing/optimizing_compiler.cc b/compiler/optimizing/optimizing_compiler.cc index 3c6d2d64a9..eb88fdee84 100644 --- a/compiler/optimizing/optimizing_compiler.cc +++ b/compiler/optimizing/optimizing_compiler.cc @@ -454,6 +454,8 @@ static bool IsInstructionSetSupported(InstructionSet instruction_set) { static bool InstructionSetSupportsReadBarrier(InstructionSet instruction_set) { return instruction_set == kArm64 || instruction_set == kThumb2 + || instruction_set == kMips + || instruction_set == kMips64 || instruction_set == kX86 || instruction_set == kX86_64; } |