From 1595815c2a914a78df7dfb6f0082f47d4e82bb36 Mon Sep 17 00:00:00 2001 From: Alexey Frunze Date: Thu, 9 Feb 2017 19:08:30 -0800 Subject: MIPS: Implement read barriers. This is the core functionality. Further improvements will be done separately. This also adds/moves memory barriers where they belong and removes the UnsafeGetLongVolatile and UnsafePutLongVolatile MIPS32 intrinsics as they need to load/store a pair of registers atomically, which is not supported directly by the CPU. Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: "testrunner.py --target --optimizing -j1" Test: same MIPS64 boot/test with ART_READ_BARRIER_TYPE=TABLELOOKUP Test: "testrunner.py --target --optimizing --32 -j2" on CI20 Test: same CI20 test with ART_READ_BARRIER_TYPE=TABLELOOKUP Change-Id: I0ff91525fefba3ec1cc019f50316478a888acced --- compiler/optimizing/optimizing_compiler.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'compiler/optimizing/optimizing_compiler.cc') diff --git a/compiler/optimizing/optimizing_compiler.cc b/compiler/optimizing/optimizing_compiler.cc index 3c6d2d64a9..eb88fdee84 100644 --- a/compiler/optimizing/optimizing_compiler.cc +++ b/compiler/optimizing/optimizing_compiler.cc @@ -454,6 +454,8 @@ static bool IsInstructionSetSupported(InstructionSet instruction_set) { static bool InstructionSetSupportsReadBarrier(InstructionSet instruction_set) { return instruction_set == kArm64 || instruction_set == kThumb2 + || instruction_set == kMips + || instruction_set == kMips64 || instruction_set == kX86 || instruction_set == kX86_64; } -- cgit v1.2.3-59-g8ed1b