summaryrefslogtreecommitdiff
path: root/compiler/optimizing/instruction_simplifier_shared.cc
diff options
context:
space:
mode:
author Anton Romanov <anton.romanov@syntacore.com> 2024-05-30 17:05:54 +0500
committer VladimĂ­r Marko <vmarko@google.com> 2024-06-12 10:42:45 +0000
commitb658a268e2e76e429702c2929d24ebbbf909e947 (patch)
tree2366f34aecd290dcc988dbb3d1923e9471d8370e /compiler/optimizing/instruction_simplifier_shared.cc
parent05e428dacb0b4877960e3b1c0d50cb9c90f378d5 (diff)
riscv: Expand BitwiseNegatedRight to riscv64, optimize
Add BitwiseNegatedRight optimization for riscv: And + Not -> AndNot Or + Not -> OrNot Xor + Not -> XorNot By compiling facebook app using dex2oat I got: 169 cases of And + Not pattern 9 cases of Or + Not pattern 1 case of Xor + Not pattern. Test: art/test/testrunner/testrunner.py --target --64 --ndebug --optimizing Change-Id: Icc2db96770378005d2fb01176298a067e1a0e4ad
Diffstat (limited to 'compiler/optimizing/instruction_simplifier_shared.cc')
-rw-r--r--compiler/optimizing/instruction_simplifier_shared.cc73
1 files changed, 0 insertions, 73 deletions
diff --git a/compiler/optimizing/instruction_simplifier_shared.cc b/compiler/optimizing/instruction_simplifier_shared.cc
index deb8f93492..b7d76da548 100644
--- a/compiler/optimizing/instruction_simplifier_shared.cc
+++ b/compiler/optimizing/instruction_simplifier_shared.cc
@@ -187,79 +187,6 @@ bool TryCombineMultiplyAccumulate(HMul* mul, InstructionSet isa) {
return false;
}
-
-bool TryMergeNegatedInput(HBinaryOperation* op) {
- DCHECK(op->IsAnd() || op->IsOr() || op->IsXor()) << op->DebugName();
- HInstruction* left = op->GetLeft();
- HInstruction* right = op->GetRight();
-
- // Only consider the case where there is exactly one Not, with 2 Not's De
- // Morgan's laws should be applied instead.
- if (left->IsNot() ^ right->IsNot()) {
- HInstruction* hnot = (left->IsNot() ? left : right);
- HInstruction* hother = (left->IsNot() ? right : left);
-
- // Only do the simplification if the Not has only one use and can thus be
- // safely removed. Even though ARM64 negated bitwise operations do not have
- // an immediate variant (only register), we still do the simplification when
- // `hother` is a constant, because it removes an instruction if the constant
- // cannot be encoded as an immediate:
- // mov r0, #large_constant
- // neg r2, r1
- // and r0, r0, r2
- // becomes:
- // mov r0, #large_constant
- // bic r0, r0, r1
- if (hnot->HasOnlyOneNonEnvironmentUse()) {
- // Replace code looking like
- // NOT tmp, mask
- // AND dst, src, tmp (respectively ORR, EOR)
- // with
- // BIC dst, src, mask (respectively ORN, EON)
- HInstruction* src = hnot->AsNot()->GetInput();
-
- HBitwiseNegatedRight* neg_op = new (hnot->GetBlock()->GetGraph()->GetAllocator())
- HBitwiseNegatedRight(op->GetType(), op->GetKind(), hother, src, op->GetDexPc());
-
- op->GetBlock()->ReplaceAndRemoveInstructionWith(op, neg_op);
- hnot->GetBlock()->RemoveInstruction(hnot);
- return true;
- }
- }
-
- return false;
-}
-
-bool TryMergeWithAnd(HSub* instruction) {
- HAnd* and_instr = instruction->GetRight()->AsAndOrNull();
- if (and_instr == nullptr) {
- return false;
- }
-
- HInstruction* value = instruction->GetLeft();
-
- HInstruction* left = and_instr->GetLeft();
- const bool left_is_equal = left == value;
- HInstruction* right = and_instr->GetRight();
- const bool right_is_equal = right == value;
- if (!left_is_equal && !right_is_equal) {
- return false;
- }
-
- HBitwiseNegatedRight* bnr = new (instruction->GetBlock()->GetGraph()->GetAllocator())
- HBitwiseNegatedRight(instruction->GetType(),
- HInstruction::InstructionKind::kAnd,
- value,
- left_is_equal ? right : left,
- instruction->GetDexPc());
- instruction->GetBlock()->ReplaceAndRemoveInstructionWith(instruction, bnr);
- // Since we don't run DCE after this phase, try to manually remove the And instruction.
- if (!and_instr->HasUses()) {
- and_instr->GetBlock()->RemoveInstruction(and_instr);
- }
- return true;
-}
-
bool TryExtractArrayAccessAddress(CodeGenerator* codegen,
HInstruction* access,
HInstruction* array,