diff options
| author | 2017-04-03 18:47:32 +0100 | |
|---|---|---|
| committer | 2017-04-10 11:43:33 +0100 | |
| commit | d4bccf1ece319a3a99e03ecbcbbf40bb82b9e331 (patch) | |
| tree | 2890740d9cab3eee2be223666f528c6707b89f90 /compiler/optimizing/common_arm64.h | |
| parent | 903b8169074c01590ab3f5ad9190d9c7e3fe795b (diff) | |
ARM64: Support 128-bit registers for SIMD.
Test: test-art-host, test-art-target
Change-Id: Ifb931a99d34ea77602a0e0781040ed092de9faaa
Diffstat (limited to 'compiler/optimizing/common_arm64.h')
| -rw-r--r-- | compiler/optimizing/common_arm64.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/compiler/optimizing/common_arm64.h b/compiler/optimizing/common_arm64.h index d3f431e327..5372b97247 100644 --- a/compiler/optimizing/common_arm64.h +++ b/compiler/optimizing/common_arm64.h @@ -92,6 +92,11 @@ inline vixl::aarch64::FPRegister DRegisterFrom(Location location) { return vixl::aarch64::FPRegister::GetDRegFromCode(location.reg()); } +inline vixl::aarch64::FPRegister QRegisterFrom(Location location) { + DCHECK(location.IsFpuRegister()) << location; + return vixl::aarch64::FPRegister::GetQRegFromCode(location.reg()); +} + inline vixl::aarch64::FPRegister SRegisterFrom(Location location) { DCHECK(location.IsFpuRegister()) << location; return vixl::aarch64::FPRegister::GetSRegFromCode(location.reg()); |