From d4bccf1ece319a3a99e03ecbcbbf40bb82b9e331 Mon Sep 17 00:00:00 2001 From: Artem Serov Date: Mon, 3 Apr 2017 18:47:32 +0100 Subject: ARM64: Support 128-bit registers for SIMD. Test: test-art-host, test-art-target Change-Id: Ifb931a99d34ea77602a0e0781040ed092de9faaa --- compiler/optimizing/common_arm64.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'compiler/optimizing/common_arm64.h') diff --git a/compiler/optimizing/common_arm64.h b/compiler/optimizing/common_arm64.h index d3f431e327..5372b97247 100644 --- a/compiler/optimizing/common_arm64.h +++ b/compiler/optimizing/common_arm64.h @@ -92,6 +92,11 @@ inline vixl::aarch64::FPRegister DRegisterFrom(Location location) { return vixl::aarch64::FPRegister::GetDRegFromCode(location.reg()); } +inline vixl::aarch64::FPRegister QRegisterFrom(Location location) { + DCHECK(location.IsFpuRegister()) << location; + return vixl::aarch64::FPRegister::GetQRegFromCode(location.reg()); +} + inline vixl::aarch64::FPRegister SRegisterFrom(Location location) { DCHECK(location.IsFpuRegister()) << location; return vixl::aarch64::FPRegister::GetSRegFromCode(location.reg()); -- cgit v1.2.3-59-g8ed1b