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author Roman Artemev <roman.artemev@syntacore.com> 2025-03-06 09:05:16 +0000
committer Treehugger Robot <android-test-infra-autosubmit@system.gserviceaccount.com> 2025-03-20 04:43:51 -0700
commitb67aed38aae437ee6861b35253bc533a9ff99846 (patch)
tree073f72f498cb9e069bad40268e6022512d908a31 /compiler/jit/jit_logger.cc
parente966e271e8714558f7cda9ef1cb1500aa747f7ea (diff)
riscv64: Support RISC-V in JitLogger
Return correct constant value `EM_RISCV` for RISC-V to generate perf jit header Test: Compile. Change-Id: Ia92a656dd87e1a106c35564583e0600274233377
Diffstat (limited to 'compiler/jit/jit_logger.cc')
-rw-r--r--compiler/jit/jit_logger.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/compiler/jit/jit_logger.cc b/compiler/jit/jit_logger.cc
index f192ce7139..29fd2b3e80 100644
--- a/compiler/jit/jit_logger.cc
+++ b/compiler/jit/jit_logger.cc
@@ -201,6 +201,9 @@ static uint32_t GetElfMach() {
#elif defined(__x86_64__)
static const uint32_t kElfMachX64 = 0x3E;
return kElfMachX64;
+#elif defined(__riscv__) || defined(__riscv)
+ static const uint32_t kElfMachRISCV = 0xF3;
+ return kElfMachRISCV;
#else
UNIMPLEMENTED(WARNING) << "Unsupported architecture in JitLogger";
return 0;