From b67aed38aae437ee6861b35253bc533a9ff99846 Mon Sep 17 00:00:00 2001
From: Roman Artemev <roman.artemev@syntacore.com>
Date: Thu, 6 Mar 2025 09:05:16 +0000
Subject: riscv64: Support RISC-V in JitLogger

Return correct constant value `EM_RISCV` for RISC-V to generate
perf jit header

Test: Compile.
Change-Id: Ia92a656dd87e1a106c35564583e0600274233377
---
 compiler/jit/jit_logger.cc | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'compiler/jit/jit_logger.cc')

diff --git a/compiler/jit/jit_logger.cc b/compiler/jit/jit_logger.cc
index f192ce7139..29fd2b3e80 100644
--- a/compiler/jit/jit_logger.cc
+++ b/compiler/jit/jit_logger.cc
@@ -201,6 +201,9 @@ static uint32_t GetElfMach() {
 #elif defined(__x86_64__)
   static const uint32_t kElfMachX64 = 0x3E;
   return kElfMachX64;
+#elif defined(__riscv__) || defined(__riscv)
+  static const uint32_t kElfMachRISCV = 0xF3;
+  return kElfMachRISCV;
 #else
   UNIMPLEMENTED(WARNING) << "Unsupported architecture in JitLogger";
   return 0;
-- 
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