blob: b7bf34b2f10aaf1409d743d986884aabad94e220 [file] [log] [blame]
David Ngee7c4c52018-03-22 23:49:12 -07001/* Copyright (c) 2012, 2014, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34#define FAILED -1
35#define SUCCESS 0
36#define INDEFINITE_DURATION 0
37
38/* Hints sent to perf HAL from power HAL
39 * These have to be kept in sync with Perf HAL side definitions
40 */
41#define VENDOR_HINT_DISPLAY_OFF 0x00001040
42#define VENDOR_HINT_DISPLAY_ON 0x00001041
43
44enum SCREEN_DISPLAY_TYPE {
45 DISPLAY_OFF = 0x00FF,
46};
47
48enum PWR_CLSP_TYPE {
49 ALL_CPUS_PWR_CLPS_DIS = 0x101,
50};
51
52/* For CPUx min freq, the leftmost byte
53 * represents the CPU and the
54 * rightmost byte represents the frequency
55 * All intermediate frequencies on the
56 * device are supported. The hex value
57 * passed into PerfLock will be multiplied
58 * by 10^5. This frequency or the next
59 * highest frequency available will be set
60 *
61 * For example, if 1.4 Ghz is required on
62 * CPU0, use 0x20E
63 *
64 * If the highest available frequency
65 * on the device is required, use
66 * CPUx_MIN_FREQ_TURBO_MAX
67 * where x represents the CPU
68 */
69enum CPU0_MIN_FREQ_LVL {
70 CPU0_MIN_FREQ_NONTURBO_MAX = 0x20A,
71 CPU0_MIN_FREQ_TURBO_MAX = 0x2FE,
72};
73
74enum CPU1_MIN_FREQ_LVL {
75 CPU1_MIN_FREQ_NONTURBO_MAX = 0x30A,
76 CPU1_MIN_FREQ_TURBO_MAX = 0x3FE,
77};
78
79enum CPU2_MIN_FREQ_LVL {
80 CPU2_MIN_FREQ_NONTURBO_MAX = 0x40A,
81 CPU2_MIN_FREQ_TURBO_MAX = 0x4FE,
82};
83
84enum CPU3_MIN_FREQ_LVL {
85 CPU3_MIN_FREQ_NONTURBO_MAX = 0x50A,
86 CPU3_MIN_FREQ_TURBO_MAX = 0x5FE,
87};
88
89enum CPU0_MAX_FREQ_LVL {
90 CPU0_MAX_FREQ_NONTURBO_MAX = 0x150A,
91};
92
93enum CPU1_MAX_FREQ_LVL {
94 CPU1_MAX_FREQ_NONTURBO_MAX = 0x160A,
95};
96
97enum CPU2_MAX_FREQ_LVL {
98 CPU2_MAX_FREQ_NONTURBO_MAX = 0x170A,
99};
100
101enum CPU3_MAX_FREQ_LVL {
102 CPU3_MAX_FREQ_NONTURBO_MAX = 0x180A,
103};
104
105enum MIN_CPUS_ONLINE_LVL {
106 CPUS_ONLINE_MIN_2 = 0x702,
107 CPUS_ONLINE_MIN_3 = 0x703,
108 CPUS_ONLINE_MIN_4 = 0x704,
109 CPUS_ONLINE_MPD_OVERRIDE = 0x777,
110 CPUS_ONLINE_MAX = 0x7FF,
111};
112
113enum MAX_CPUS_ONLINE_LVL {
114 CPUS_ONLINE_MAX_LIMIT_1 = 0x8FE,
115 CPUS_ONLINE_MAX_LIMIT_2 = 0x8FD,
116 CPUS_ONLINE_MAX_LIMIT_3 = 0x8FC,
117 CPUS_ONLINE_MAX_LIMIT_4 = 0x8FB,
118 CPUS_ONLINE_MAX_LIMIT_MAX = 0x8FB,
119};
120
121enum SAMPLING_RATE_LVL {
122 MS_500 = 0xBCD,
123 MS_50 = 0xBFA,
124 MS_20 = 0xBFD,
125};
126
127enum ONDEMAND_IO_BUSY_LVL {
128 IO_BUSY_OFF = 0xC00,
129 IO_BUSY_ON = 0xC01,
130};
131
132enum ONDEMAND_SAMPLING_DOWN_FACTOR_LVL {
133 SAMPLING_DOWN_FACTOR_1 = 0xD01,
134 SAMPLING_DOWN_FACTOR_4 = 0xD04,
135};
136
137enum INTERACTIVE_TIMER_RATE_LVL {
138 TR_MS_500 = 0xECD,
139 TR_MS_100 = 0xEF5,
140 TR_MS_50 = 0xEFA,
141 TR_MS_30 = 0xEFC,
142 TR_MS_20 = 0xEFD,
143};
144
145/* This timer rate applicable to cpu0
146 across 8939 series chipset */
147enum INTERACTIVE_TIMER_RATE_LVL_CPU0_8939 {
148 TR_MS_CPU0_500 = 0x30CD,
149 TR_MS_CPU0_100 = 0x30F5,
150 TR_MS_CPU0_50 = 0x30FA,
151 TR_MS_CPU0_30 = 0x30FC,
152 TR_MS_CPU0_20 = 0x30FD,
153};
154
155/* This timer rate applicable to cpu4
156 across 8939 series chipset */
157enum INTERACTIVE_TIMER_RATE_LVL_CPU4_8939 {
158 TR_MS_CPU4_500 = 0x3BCD,
159 TR_MS_CPU4_100 = 0x3BF5,
160 TR_MS_CPU4_50 = 0x3BFA,
161 TR_MS_CPU4_30 = 0x3BFC,
162 TR_MS_CPU4_20 = 0x3BFD,
163};
164
165/* This timer rate applicable to big.little arch */
166enum INTERACTIVE_TIMER_RATE_LVL_BIG_LITTLE {
167 BIG_LITTLE_TR_MS_100 = 0x64,
168 BIG_LITTLE_TR_MS_50 = 0x32,
169 BIG_LITTLE_TR_MS_40 = 0x28,
170 BIG_LITTLE_TR_MS_30 = 0x1E,
171 BIG_LITTLE_TR_MS_20 = 0x14,
172};
173
174/* INTERACTIVE opcodes */
175enum INTERACTIVE_OPCODES {
176 INT_OP_CLUSTER0_TIMER_RATE = 0x41424000,
177 INT_OP_CLUSTER1_TIMER_RATE = 0x41424100,
178 INT_OP_CLUSTER0_USE_SCHED_LOAD = 0x41430000,
179 INT_OP_CLUSTER1_USE_SCHED_LOAD = 0x41430100,
180 INT_OP_CLUSTER0_USE_MIGRATION_NOTIF = 0x41434000,
181 INT_OP_CLUSTER1_USE_MIGRATION_NOTIF = 0x41434100,
182 INT_OP_NOTIFY_ON_MIGRATE = 0x4241C000
183};
184
185enum INTERACTIVE_HISPEED_FREQ_LVL {
186 HS_FREQ_1026 = 0xF0A,
187};
188
189enum INTERACTIVE_HISPEED_LOAD_LVL {
190 HISPEED_LOAD_90 = 0x105A,
191};
192
193enum SYNC_FREQ_LVL {
194 SYNC_FREQ_300 = 0x1103,
195 SYNC_FREQ_600 = 0X1106,
196 SYNC_FREQ_384 = 0x1103,
197 SYNC_FREQ_NONTURBO_MAX = 0x110A,
198 SYNC_FREQ_TURBO = 0x110F,
199};
200
201enum OPTIMAL_FREQ_LVL {
202 OPTIMAL_FREQ_300 = 0x1203,
203 OPTIMAL_FREQ_600 = 0x1206,
204 OPTIMAL_FREQ_384 = 0x1203,
205 OPTIMAL_FREQ_NONTURBO_MAX = 0x120A,
206 OPTIMAL_FREQ_TURBO = 0x120F,
207};
208
209enum SCREEN_PWR_CLPS_LVL {
210 PWR_CLPS_DIS = 0x1300,
211 PWR_CLPS_ENA = 0x1301,
212};
213
214enum THREAD_MIGRATION_LVL {
215 THREAD_MIGRATION_SYNC_OFF = 0x1400,
216};
217
218enum INTERACTIVE_IO_BUSY_LVL {
219 INTERACTIVE_IO_BUSY_OFF = 0x1B00,
220 INTERACTIVE_IO_BUSY_ON = 0x1B01,
221};
222
223enum SCHED_BOOST_LVL {
224 SCHED_BOOST_ON = 0x1E01,
225};
226
227enum CPU4_MIN_FREQ_LVL {
228 CPU4_MIN_FREQ_NONTURBO_MAX = 0x1F0A,
229 CPU4_MIN_FREQ_TURBO_MAX = 0x1FFE,
230};
231
232enum CPU5_MIN_FREQ_LVL {
233 CPU5_MIN_FREQ_NONTURBO_MAX = 0x200A,
234 CPU5_MIN_FREQ_TURBO_MAX = 0x20FE,
235};
236
237enum CPU6_MIN_FREQ_LVL {
238 CPU6_MIN_FREQ_NONTURBO_MAX = 0x210A,
239 CPU6_MIN_FREQ_TURBO_MAX = 0x21FE,
240};
241
242enum CPU7_MIN_FREQ_LVL {
243 CPU7_MIN_FREQ_NONTURBO_MAX = 0x220A,
244 CPU7_MIN_FREQ_TURBO_MAX = 0x22FE,
245};
246
247enum CPU4_MAX_FREQ_LVL {
248 CPU4_MAX_FREQ_NONTURBO_MAX = 0x230A,
249};
250
251enum CPU5_MAX_FREQ_LVL {
252 CPU5_MAX_FREQ_NONTURBO_MAX = 0x240A,
253};
254
255enum CPU6_MAX_FREQ_LVL {
256 CPU6_MAX_FREQ_NONTURBO_MAX = 0x250A,
257};
258
259enum CPU7_MAX_FREQ_LVL {
260 CPU7_MAX_FREQ_NONTURBO_MAX = 0x260A,
261};
262
263#ifdef __cplusplus
264}
265#endif