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LeafOS / LeafOS-Project / android_art / eda6df7374bf61c933d4a36635e2a9a30c9892a0 / . / compiler / dex / quick / arm / codegen_arm.h
blob: 0a3bfc10ee22b9074322bc657c7730855274e3d7 [file] [log] [blame]
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
Brian Carlstromfc0e3212013-07-17 14:40:12 -0700[diff] [blame]17#ifndef ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
18#define ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]19
20#include "dex/compiler_internals.h"
21
22namespace art {
23
24class ArmMir2Lir : public Mir2Lir {
25 public:
26 ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
27
28 // Required for target - codegen helpers.
buzbee11b63d12013-08-27 07:34:17 -0700[diff] [blame]29 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]30 RegLocation rl_dest, int lit);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame]31 int LoadHelper(ThreadOffset offset);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]32 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
33 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
34 int s_reg);
35 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
36 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
37 int r_dest, int r_dest_hi, OpSize size, int s_reg);
38 LIR* LoadConstantNoClobber(int r_dest, int value);
39 LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value);
40 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
41 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
42 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
43 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
44 int r_src, int r_src_hi, OpSize size, int s_reg);
45 void MarkGCCard(int val_reg, int tgt_addr_reg);
46
47 // Required for target - register utilities.
48 bool IsFpReg(int reg);
49 bool SameRegType(int reg1, int reg2);
50 int AllocTypedTemp(bool fp_hint, int reg_class);
51 int AllocTypedTempPair(bool fp_hint, int reg_class);
52 int S2d(int low_reg, int high_reg);
53 int TargetReg(SpecialTargetRegister reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]54 RegLocation GetReturnAlt();
55 RegLocation GetReturnWideAlt();
56 RegLocation LocCReturn();
57 RegLocation LocCReturnDouble();
58 RegLocation LocCReturnFloat();
59 RegLocation LocCReturnWide();
60 uint32_t FpRegMask();
61 uint64_t GetRegMaskCommon(int reg);
62 void AdjustSpillMask();
63 void ClobberCalleeSave();
64 void FlushReg(int reg);
65 void FlushRegWide(int reg1, int reg2);
66 void FreeCallTemps();
67 void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
68 void LockCallTemps();
69 void MarkPreservedSingle(int v_reg, int reg);
70 void CompilerInitializeRegAlloc();
71
72 // Required for target - miscellaneous.
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]73 void AssembleLIR();
74 uint32_t EncodeRange(LIR* head_lir, LIR* tail_lir, uint32_t starting_offset);
75 int AssignInsnOffsets();
76 void AssignOffsets();
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]77 void EncodeLIR(LIR* lir);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]78 void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]79 void SetupTargetResourceMasks(LIR* lir, uint64_t flags);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]80 const char* GetTargetInstFmt(int opcode);
81 const char* GetTargetInstName(int opcode);
82 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
83 uint64_t GetPCUseDefEncoding();
84 uint64_t GetTargetInstFlags(int opcode);
85 int GetInsnSize(LIR* lir);
86 bool IsUnconditionalBranch(LIR* lir);
87
88 // Required for target - Dalvik-level generators.
89 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
90 RegLocation rl_src1, RegLocation rl_src2);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]91 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
92 RegLocation rl_index, RegLocation rl_dest, int scale);
Ian Rogersa9a82542013-10-04 11:17:26 -0700[diff] [blame]93 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
94 RegLocation rl_src, int scale, bool card_mark);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]95 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
96 RegLocation rl_src1, RegLocation rl_shift);
97 void GenMulLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
98 void GenAddLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
99 void GenAndLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
100 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
101 RegLocation rl_src1, RegLocation rl_src2);
102 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
103 RegLocation rl_src1, RegLocation rl_src2);
104 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105 RegLocation rl_src2);
106 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
107 bool GenInlinedCas32(CallInfo* info, bool need_write_barrier);
108 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
109 bool GenInlinedSqrt(CallInfo* info);
110 void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
111 void GenOrLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
112 void GenSubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
113 void GenXorLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
114 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
115 ThrowKind kind);
116 RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div);
117 RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div);
118 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
119 void GenDivZeroCheck(int reg_lo, int reg_hi);
120 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
121 void GenExitSequence();
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]122 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]123 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
124 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
125 void GenSelect(BasicBlock* bb, MIR* mir);
126 void GenMemBarrier(MemBarrierKind barrier_kind);
127 void GenMonitorEnter(int opt_flags, RegLocation rl_src);
128 void GenMonitorExit(int opt_flags, RegLocation rl_src);
129 void GenMoveException(RegLocation rl_dest);
130 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
131 int first_bit, int second_bit);
132 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
133 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]134 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
135 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]136 void GenSpecialCase(BasicBlock* bb, MIR* mir, SpecialCaseHandler special_case);
137
138 // Required for target - single operation generators.
139 LIR* OpUnconditionalBranch(LIR* target);
140 LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
141 LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
142 LIR* OpCondBranch(ConditionCode cc, LIR* target);
143 LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
144 LIR* OpFpRegCopy(int r_dest, int r_src);
145 LIR* OpIT(ConditionCode cond, const char* guide);
146 LIR* OpMem(OpKind op, int rBase, int disp);
147 LIR* OpPcRelLoad(int reg, LIR* target);
148 LIR* OpReg(OpKind op, int r_dest_src);
149 LIR* OpRegCopy(int r_dest, int r_src);
150 LIR* OpRegCopyNoInsert(int r_dest, int r_src);
151 LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
152 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
153 LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
154 LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
155 LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2);
156 LIR* OpTestSuspend(LIR* target);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame]157 LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]158 LIR* OpVldm(int rBase, int count);
159 LIR* OpVstm(int rBase, int count);
160 void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
161 void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame]162 void OpTlsCmp(ThreadOffset offset, int val);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]163
164 RegLocation ArgLoc(RegLocation loc);
165 LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
166 int s_reg);
167 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size);
168 void GenPrintLabel(MIR* mir);
169 LIR* OpRegRegRegShift(OpKind op, int r_dest, int r_src1, int r_src2, int shift);
170 LIR* OpRegRegShift(OpKind op, int r_dest_src1, int r_src2, int shift);
171 static const ArmEncodingMap EncodingMap[kArmLast];
172 int EncodeShift(int code, int amount);
173 int ModifiedImmediate(uint32_t value);
174 ArmConditionCode ArmConditionEncoding(ConditionCode code);
175 bool InexpensiveConstantInt(int32_t value);
176 bool InexpensiveConstantFloat(int32_t value);
177 bool InexpensiveConstantLong(int64_t value);
178 bool InexpensiveConstantDouble(int64_t value);
179
180 private:
181 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val,
182 ConditionCode ccode);
183 int InPosition(int s_reg);
184 RegLocation LoadArg(RegLocation loc);
185 void LockLiveArgs(MIR* mir);
186 MIR* GetNextMir(BasicBlock** p_bb, MIR* mir);
187 MIR* SpecialIGet(BasicBlock** bb, MIR* mir, OpSize size, bool long_or_double, bool is_object);
188 MIR* SpecialIPut(BasicBlock** bb, MIR* mir, OpSize size, bool long_or_double, bool is_object);
189 MIR* SpecialIdentity(MIR* mir);
190 LIR* LoadFPConstantValue(int r_dest, int value);
191 bool BadOverlap(RegLocation rl_src, RegLocation rl_dest);
buzbeeb48819d2013-09-14 16:15:25 -0700[diff] [blame]192 void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
193 void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
194 void AssignDataOffsets();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]195};
196
197} // namespace art
198
Brian Carlstromfc0e3212013-07-17 14:40:12 -0700[diff] [blame]199#endif // ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_