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jeffhao7fbee072012-08-24 17:56:54 -07001/*
jeffhaoc0228b82012-08-29 18:15:05 -07002 * Copyright (C) 2012 The Android Open Source Project
jeffhao7fbee072012-08-24 17:56:54 -07003 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
Ian Rogers166db042013-07-26 12:05:57 -070017#ifndef ART_COMPILER_UTILS_MIPS_CONSTANTS_MIPS_H_
18#define ART_COMPILER_UTILS_MIPS_CONSTANTS_MIPS_H_
jeffhao7fbee072012-08-24 17:56:54 -070019
20#include <iosfwd>
Elliott Hughes07ed66b2012-12-12 18:34:25 -080021
Ian Rogers166db042013-07-26 12:05:57 -070022#include "arch/mips/registers_mips.h"
Elliott Hughes07ed66b2012-12-12 18:34:25 -080023#include "base/logging.h"
Elliott Hughes76160052012-12-12 16:31:20 -080024#include "base/macros.h"
jeffhao7fbee072012-08-24 17:56:54 -070025#include "globals.h"
jeffhao7fbee072012-08-24 17:56:54 -070026
27namespace art {
28namespace mips {
29
jeffhao7fbee072012-08-24 17:56:54 -070030// Values for double-precision floating point registers.
31enum DRegister {
32 D0 = 0,
33 D1 = 1,
34 D2 = 2,
35 D3 = 3,
36 D4 = 4,
37 D5 = 5,
38 D6 = 6,
39 D7 = 7,
40 D8 = 8,
41 D9 = 9,
42 D10 = 10,
43 D11 = 11,
44 D12 = 12,
45 D13 = 13,
46 D14 = 14,
47 D15 = 15,
48 kNumberOfDRegisters = 16,
49 kNumberOfOverlappingDRegisters = 16,
50 kNoDRegister = -1,
51};
52std::ostream& operator<<(std::ostream& os, const DRegister& rhs);
53
54// Constants used for the decoding or encoding of the individual fields of instructions.
55enum InstructionFields {
56 kOpcodeShift = 26,
57 kOpcodeBits = 6,
58 kRsShift = 21,
59 kRsBits = 5,
60 kRtShift = 16,
61 kRtBits = 5,
62 kRdShift = 11,
63 kRdBits = 5,
64 kShamtShift = 6,
65 kShamtBits = 5,
66 kFunctShift = 0,
67 kFunctBits = 6,
68
69 kFmtShift = 21,
70 kFmtBits = 5,
71 kFtShift = 16,
72 kFtBits = 5,
73 kFsShift = 11,
74 kFsBits = 5,
75 kFdShift = 6,
76 kFdBits = 5,
77
78 kBranchOffsetMask = 0x0000ffff,
79 kJumpOffsetMask = 0x03ffffff,
80};
81
82enum ScaleFactor {
83 TIMES_1 = 0,
84 TIMES_2 = 1,
85 TIMES_4 = 2,
86 TIMES_8 = 3
87};
88
89class Instr {
90 public:
91 static const uint32_t kBreakPointInstruction = 0x0000000D;
92
93 bool IsBreakPoint() {
94 return ((*reinterpret_cast<const uint32_t*>(this)) & 0xFC0000CF) == kBreakPointInstruction;
95 }
96
97 // Instructions are read out of a code stream. The only way to get a
98 // reference to an instruction is to convert a pointer. There is no way
99 // to allocate or create instances of class Instr.
100 // Use the At(pc) function to create references to Instr.
101 static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); }
102
103 private:
104 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
105};
106
107} // namespace mips
108} // namespace art
109
Ian Rogers166db042013-07-26 12:05:57 -0700110#endif // ART_COMPILER_UTILS_MIPS_CONSTANTS_MIPS_H_