| buzbee | 1452bee | 2015-03-06 14:43:04 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Long integer shift. This is different from the generic 32/64-bit |
| 3 | * binary operations because vAA/vBB are 64-bit but vCC (the shift |
| 4 | * distance) is 32-bit. Also, Dalvik requires us to mask off the low |
| 5 | * 6 bits of the shift distance. |
| 6 | */ |
| 7 | /* shr-long vAA, vBB, vCC */ |
| 8 | FETCH r0, 1 @ r0<- CCBB |
| 9 | mov r9, rINST, lsr #8 @ r9<- AA |
| 10 | and r3, r0, #255 @ r3<- BB |
| 11 | mov r0, r0, lsr #8 @ r0<- CC |
| buzbee | ace690f | 2016-03-11 09:51:11 -0800 | [diff] [blame] | 12 | VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] |
| buzbee | 1452bee | 2015-03-06 14:43:04 -0800 | [diff] [blame] | 13 | GET_VREG r2, r0 @ r2<- vCC |
| 14 | ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 |
| buzbee | c3b4c6e | 2016-02-19 10:10:20 -0800 | [diff] [blame] | 15 | CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs |
| buzbee | 1452bee | 2015-03-06 14:43:04 -0800 | [diff] [blame] | 16 | and r2, r2, #63 @ r0<- r0 & 0x3f |
| buzbee | ace690f | 2016-03-11 09:51:11 -0800 | [diff] [blame] | 17 | VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] |
| buzbee | c3b4c6e | 2016-02-19 10:10:20 -0800 | [diff] [blame] | 18 | mov r0, r0, lsr r2 @ r0<- r2 >> r2 |
| 19 | rsb r3, r2, #32 @ r3<- 32 - r2 |
| 20 | orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) |
| 21 | subs ip, r2, #32 @ ip<- r2 - 32 |
| 22 | movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) |
| buzbee | 1452bee | 2015-03-06 14:43:04 -0800 | [diff] [blame] | 23 | FETCH_ADVANCE_INST 2 @ advance rPC, load rINST |
| buzbee | c3b4c6e | 2016-02-19 10:10:20 -0800 | [diff] [blame] | 24 | mov r1, r1, asr r2 @ r1<- r1 >> r2 |
| buzbee | 1452bee | 2015-03-06 14:43:04 -0800 | [diff] [blame] | 25 | GET_INST_OPCODE ip @ extract opcode from rINST |
| 26 | stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 |
| 27 | GOTO_OPCODE ip @ jump to next instruction |