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Elliott Hughes2faa5f12012-01-30 14:42:07 -08001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070016
Ian Rogers166db042013-07-26 12:05:57 -070017#ifndef ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
18#define ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070019
Ian Rogers0d666d82011-08-14 16:03:46 -070020#include <vector>
Vladimir Marko80afd022015-05-19 18:08:00 +010021#include "base/bit_utils.h"
Elliott Hughes76160052012-12-12 16:31:20 -080022#include "base/macros.h"
Elliott Hughes0f3c5532012-03-30 14:51:51 -070023#include "constants_x86.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070024#include "globals.h"
Ian Rogers2c8f6532011-09-02 17:16:34 -070025#include "managed_register_x86.h"
Brian Carlstrom578bbdc2011-07-21 14:07:47 -070026#include "offsets.h"
Ian Rogers166db042013-07-26 12:05:57 -070027#include "utils/assembler.h"
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070028
Carl Shapiro6b6b5f02011-06-21 15:05:09 -070029namespace art {
Ian Rogers2c8f6532011-09-02 17:16:34 -070030namespace x86 {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070031
Ian Rogerscf7f1912014-10-22 22:06:39 -070032class Immediate : public ValueObject {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070033 public:
Andreas Gampe277ccbd2014-11-03 21:36:10 -080034 explicit Immediate(int32_t value_in) : value_(value_in) {}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070035
36 int32_t value() const { return value_; }
37
Andreas Gampeab1eb0d2015-02-13 19:23:55 -080038 bool is_int8() const { return IsInt<8>(value_); }
39 bool is_uint8() const { return IsUint<8>(value_); }
40 bool is_int16() const { return IsInt<16>(value_); }
41 bool is_uint16() const { return IsUint<16>(value_); }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070042
43 private:
44 const int32_t value_;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070045};
46
47
Ian Rogerscf7f1912014-10-22 22:06:39 -070048class Operand : public ValueObject {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070049 public:
50 uint8_t mod() const {
51 return (encoding_at(0) >> 6) & 3;
52 }
53
54 Register rm() const {
55 return static_cast<Register>(encoding_at(0) & 7);
56 }
57
58 ScaleFactor scale() const {
59 return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
60 }
61
62 Register index() const {
63 return static_cast<Register>((encoding_at(1) >> 3) & 7);
64 }
65
66 Register base() const {
67 return static_cast<Register>(encoding_at(1) & 7);
68 }
69
70 int8_t disp8() const {
71 CHECK_GE(length_, 2);
72 return static_cast<int8_t>(encoding_[length_ - 1]);
73 }
74
75 int32_t disp32() const {
76 CHECK_GE(length_, 5);
77 int32_t value;
78 memcpy(&value, &encoding_[length_ - 4], sizeof(value));
79 return value;
80 }
81
82 bool IsRegister(Register reg) const {
83 return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only.
84 && ((encoding_[0] & 0x07) == reg); // Register codes match.
85 }
86
87 protected:
88 // Operand can be sub classed (e.g: Address).
Mark Mendell0616ae02015-04-17 12:49:27 -040089 Operand() : length_(0), fixup_(nullptr) { }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070090
Andreas Gampe277ccbd2014-11-03 21:36:10 -080091 void SetModRM(int mod_in, Register rm_in) {
92 CHECK_EQ(mod_in & ~3, 0);
93 encoding_[0] = (mod_in << 6) | rm_in;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070094 length_ = 1;
95 }
96
Andreas Gampe277ccbd2014-11-03 21:36:10 -080097 void SetSIB(ScaleFactor scale_in, Register index_in, Register base_in) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -070098 CHECK_EQ(length_, 1);
Andreas Gampe277ccbd2014-11-03 21:36:10 -080099 CHECK_EQ(scale_in & ~3, 0);
100 encoding_[1] = (scale_in << 6) | (index_in << 3) | base_in;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700101 length_ = 2;
102 }
103
104 void SetDisp8(int8_t disp) {
105 CHECK(length_ == 1 || length_ == 2);
106 encoding_[length_++] = static_cast<uint8_t>(disp);
107 }
108
109 void SetDisp32(int32_t disp) {
110 CHECK(length_ == 1 || length_ == 2);
111 int disp_size = sizeof(disp);
112 memmove(&encoding_[length_], &disp, disp_size);
113 length_ += disp_size;
114 }
115
Mark Mendell0616ae02015-04-17 12:49:27 -0400116 AssemblerFixup* GetFixup() const {
117 return fixup_;
118 }
119
120 void SetFixup(AssemblerFixup* fixup) {
121 fixup_ = fixup;
122 }
123
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700124 private:
Ian Rogers13735952014-10-08 12:43:28 -0700125 uint8_t length_;
126 uint8_t encoding_[6];
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700127
Mark Mendell0616ae02015-04-17 12:49:27 -0400128 // A fixup can be associated with the operand, in order to be applied after the
129 // code has been generated. This is used for constant area fixups.
130 AssemblerFixup* fixup_;
131
132 explicit Operand(Register reg) : fixup_(nullptr) { SetModRM(3, reg); }
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700133
134 // Get the operand encoding byte at the given index.
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800135 uint8_t encoding_at(int index_in) const {
136 CHECK_GE(index_in, 0);
137 CHECK_LT(index_in, length_);
138 return encoding_[index_in];
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700139 }
140
Ian Rogers2c8f6532011-09-02 17:16:34 -0700141 friend class X86Assembler;
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700142};
143
144
145class Address : public Operand {
146 public:
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800147 Address(Register base_in, int32_t disp) {
148 Init(base_in, disp);
Ian Rogersb033c752011-07-20 12:22:35 -0700149 }
150
Mark Mendell0616ae02015-04-17 12:49:27 -0400151 Address(Register base_in, int32_t disp, AssemblerFixup *fixup) {
152 Init(base_in, disp);
153 SetFixup(fixup);
154 }
155
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800156 Address(Register base_in, Offset disp) {
157 Init(base_in, disp.Int32Value());
Ian Rogersa04d3972011-08-17 11:33:44 -0700158 }
159
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800160 Address(Register base_in, FrameOffset disp) {
161 CHECK_EQ(base_in, ESP);
Ian Rogersb033c752011-07-20 12:22:35 -0700162 Init(ESP, disp.Int32Value());
163 }
164
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800165 Address(Register base_in, MemberOffset disp) {
166 Init(base_in, disp.Int32Value());
Ian Rogersb033c752011-07-20 12:22:35 -0700167 }
168
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800169 void Init(Register base_in, int32_t disp) {
170 if (disp == 0 && base_in != EBP) {
171 SetModRM(0, base_in);
172 if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700173 } else if (disp >= -128 && disp <= 127) {
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800174 SetModRM(1, base_in);
175 if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700176 SetDisp8(disp);
177 } else {
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800178 SetModRM(2, base_in);
179 if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700180 SetDisp32(disp);
181 }
182 }
183
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800184 Address(Register index_in, ScaleFactor scale_in, int32_t disp) {
185 CHECK_NE(index_in, ESP); // Illegal addressing mode.
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700186 SetModRM(0, ESP);
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800187 SetSIB(scale_in, index_in, EBP);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700188 SetDisp32(disp);
189 }
190
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800191 Address(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp) {
192 CHECK_NE(index_in, ESP); // Illegal addressing mode.
193 if (disp == 0 && base_in != EBP) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700194 SetModRM(0, ESP);
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800195 SetSIB(scale_in, index_in, base_in);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700196 } else if (disp >= -128 && disp <= 127) {
197 SetModRM(1, ESP);
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800198 SetSIB(scale_in, index_in, base_in);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700199 SetDisp8(disp);
200 } else {
201 SetModRM(2, ESP);
Andreas Gampe277ccbd2014-11-03 21:36:10 -0800202 SetSIB(scale_in, index_in, base_in);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700203 SetDisp32(disp);
204 }
205 }
206
Ian Rogers13735952014-10-08 12:43:28 -0700207 static Address Absolute(uintptr_t addr) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700208 Address result;
Ian Rogersdd7624d2014-03-14 17:43:00 -0700209 result.SetModRM(0, EBP);
210 result.SetDisp32(addr);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700211 return result;
212 }
213
Ian Rogersdd7624d2014-03-14 17:43:00 -0700214 static Address Absolute(ThreadOffset<4> addr) {
215 return Absolute(addr.Int32Value());
Ian Rogersb033c752011-07-20 12:22:35 -0700216 }
217
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700218 private:
219 Address() {}
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700220};
221
222
Mark Mendell73f455e2015-08-21 09:30:05 -0400223// This is equivalent to the Label class, used in a slightly different context. We
224// inherit the functionality of the Label class, but prevent unintended
225// derived-to-base conversions by making the base class private.
226class NearLabel : private Label {
227 public:
228 NearLabel() : Label() {}
229
230 // Expose the Label routines that we need.
231 using Label::Position;
232 using Label::LinkPosition;
233 using Label::IsBound;
234 using Label::IsUnused;
235 using Label::IsLinked;
236
237 private:
238 using Label::BindTo;
239 using Label::LinkTo;
240
241 friend class x86::X86Assembler;
242
243 DISALLOW_COPY_AND_ASSIGN(NearLabel);
244};
245
Mark Mendell0616ae02015-04-17 12:49:27 -0400246/**
247 * Class to handle constant area values.
248 */
249class ConstantArea {
250 public:
251 ConstantArea() {}
252
253 // Add a double to the constant area, returning the offset into
254 // the constant area where the literal resides.
255 int AddDouble(double v);
256
257 // Add a float to the constant area, returning the offset into
258 // the constant area where the literal resides.
259 int AddFloat(float v);
260
261 // Add an int32_t to the constant area, returning the offset into
262 // the constant area where the literal resides.
263 int AddInt32(int32_t v);
264
265 // Add an int64_t to the constant area, returning the offset into
266 // the constant area where the literal resides.
267 int AddInt64(int64_t v);
268
269 bool IsEmpty() const {
270 return buffer_.size() == 0;
271 }
272
273 const std::vector<int32_t>& GetBuffer() const {
274 return buffer_;
275 }
276
277 void AddFixup(AssemblerFixup* fixup) {
278 fixups_.push_back(fixup);
279 }
280
281 const std::vector<AssemblerFixup*>& GetFixups() const {
282 return fixups_;
283 }
284
285 private:
286 static constexpr size_t kEntrySize = sizeof(int32_t);
287 std::vector<int32_t> buffer_;
288 std::vector<AssemblerFixup*> fixups_;
289};
Mark Mendell73f455e2015-08-21 09:30:05 -0400290
Ian Rogersbefbd572014-03-06 01:13:39 -0800291class X86Assembler FINAL : public Assembler {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700292 public:
Roland Levillain3887c462015-08-12 18:15:42 +0100293 X86Assembler() {}
Ian Rogers2c8f6532011-09-02 17:16:34 -0700294 virtual ~X86Assembler() {}
buzbeec143c552011-08-20 17:38:58 -0700295
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700296 /*
297 * Emit Machine Instructions.
298 */
299 void call(Register reg);
300 void call(const Address& address);
301 void call(Label* label);
Nicolas Geoffray8ccc3f52014-03-19 10:34:11 +0000302 void call(const ExternalLabel& label);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700303
304 void pushl(Register reg);
305 void pushl(const Address& address);
306 void pushl(const Immediate& imm);
307
308 void popl(Register reg);
309 void popl(const Address& address);
310
311 void movl(Register dst, const Immediate& src);
312 void movl(Register dst, Register src);
313
314 void movl(Register dst, const Address& src);
315 void movl(const Address& dst, Register src);
316 void movl(const Address& dst, const Immediate& imm);
Ian Rogersbdb03912011-09-14 00:55:44 -0700317 void movl(const Address& dst, Label* lbl);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700318
Mark Mendell7a08fb52015-07-15 14:09:35 -0400319 void movntl(const Address& dst, Register src);
320
Mark Mendell09ed1a32015-03-25 08:30:06 -0400321 void bswapl(Register dst);
Mark Mendellbcee0922015-09-15 21:45:01 -0400322 void bsfl(Register dst, Register src);
323 void bsfl(Register dst, const Address& src);
Mark Mendell8ae3ffb2015-08-12 21:16:41 -0400324 void bsrl(Register dst, Register src);
325 void bsrl(Register dst, const Address& src);
Mark Mendell09ed1a32015-03-25 08:30:06 -0400326
Mark Mendellbcee0922015-09-15 21:45:01 -0400327 void rorl(Register reg, const Immediate& imm);
328 void rorl(Register operand, Register shifter);
329 void roll(Register reg, const Immediate& imm);
330 void roll(Register operand, Register shifter);
331
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700332 void movzxb(Register dst, ByteRegister src);
333 void movzxb(Register dst, const Address& src);
334 void movsxb(Register dst, ByteRegister src);
335 void movsxb(Register dst, const Address& src);
336 void movb(Register dst, const Address& src);
337 void movb(const Address& dst, ByteRegister src);
338 void movb(const Address& dst, const Immediate& imm);
339
340 void movzxw(Register dst, Register src);
341 void movzxw(Register dst, const Address& src);
342 void movsxw(Register dst, Register src);
343 void movsxw(Register dst, const Address& src);
344 void movw(Register dst, const Address& src);
345 void movw(const Address& dst, Register src);
Nicolas Geoffray26a25ef2014-09-30 13:54:09 +0100346 void movw(const Address& dst, const Immediate& imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700347
348 void leal(Register dst, const Address& src);
349
Ian Rogersb033c752011-07-20 12:22:35 -0700350 void cmovl(Condition condition, Register dst, Register src);
351
Nicolas Geoffray5b4b8982014-12-18 17:45:56 +0000352 void setb(Condition condition, Register dst);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700353
Nicolas Geoffray7fb49da2014-10-06 09:12:41 +0100354 void movaps(XmmRegister dst, XmmRegister src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700355 void movss(XmmRegister dst, const Address& src);
356 void movss(const Address& dst, XmmRegister src);
357 void movss(XmmRegister dst, XmmRegister src);
358
359 void movd(XmmRegister dst, Register src);
360 void movd(Register dst, XmmRegister src);
361
362 void addss(XmmRegister dst, XmmRegister src);
363 void addss(XmmRegister dst, const Address& src);
364 void subss(XmmRegister dst, XmmRegister src);
365 void subss(XmmRegister dst, const Address& src);
366 void mulss(XmmRegister dst, XmmRegister src);
367 void mulss(XmmRegister dst, const Address& src);
368 void divss(XmmRegister dst, XmmRegister src);
369 void divss(XmmRegister dst, const Address& src);
370
371 void movsd(XmmRegister dst, const Address& src);
372 void movsd(const Address& dst, XmmRegister src);
373 void movsd(XmmRegister dst, XmmRegister src);
374
Calin Juravle52c48962014-12-16 17:02:57 +0000375 void psrlq(XmmRegister reg, const Immediate& shift_count);
376 void punpckldq(XmmRegister dst, XmmRegister src);
377
Nicolas Geoffray234d69d2015-03-09 10:28:50 +0000378 void movhpd(XmmRegister dst, const Address& src);
379 void movhpd(const Address& dst, XmmRegister src);
380
381 void psrldq(XmmRegister reg, const Immediate& shift_count);
382
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700383 void addsd(XmmRegister dst, XmmRegister src);
384 void addsd(XmmRegister dst, const Address& src);
385 void subsd(XmmRegister dst, XmmRegister src);
386 void subsd(XmmRegister dst, const Address& src);
387 void mulsd(XmmRegister dst, XmmRegister src);
388 void mulsd(XmmRegister dst, const Address& src);
389 void divsd(XmmRegister dst, XmmRegister src);
390 void divsd(XmmRegister dst, const Address& src);
391
392 void cvtsi2ss(XmmRegister dst, Register src);
393 void cvtsi2sd(XmmRegister dst, Register src);
394
395 void cvtss2si(Register dst, XmmRegister src);
396 void cvtss2sd(XmmRegister dst, XmmRegister src);
397
398 void cvtsd2si(Register dst, XmmRegister src);
399 void cvtsd2ss(XmmRegister dst, XmmRegister src);
400
401 void cvttss2si(Register dst, XmmRegister src);
402 void cvttsd2si(Register dst, XmmRegister src);
403
404 void cvtdq2pd(XmmRegister dst, XmmRegister src);
405
406 void comiss(XmmRegister a, XmmRegister b);
407 void comisd(XmmRegister a, XmmRegister b);
Calin Juravleddb7df22014-11-25 20:56:51 +0000408 void ucomiss(XmmRegister a, XmmRegister b);
409 void ucomisd(XmmRegister a, XmmRegister b);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700410
Mark Mendellfb8d2792015-03-31 22:16:59 -0400411 void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm);
412 void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm);
413
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700414 void sqrtsd(XmmRegister dst, XmmRegister src);
415 void sqrtss(XmmRegister dst, XmmRegister src);
416
417 void xorpd(XmmRegister dst, const Address& src);
418 void xorpd(XmmRegister dst, XmmRegister src);
419 void xorps(XmmRegister dst, const Address& src);
420 void xorps(XmmRegister dst, XmmRegister src);
421
Mark Mendell09ed1a32015-03-25 08:30:06 -0400422 void andpd(XmmRegister dst, XmmRegister src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700423 void andpd(XmmRegister dst, const Address& src);
Mark Mendell09ed1a32015-03-25 08:30:06 -0400424 void andps(XmmRegister dst, XmmRegister src);
425 void andps(XmmRegister dst, const Address& src);
426
427 void orpd(XmmRegister dst, XmmRegister src);
428 void orps(XmmRegister dst, XmmRegister src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700429
430 void flds(const Address& src);
431 void fstps(const Address& dst);
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500432 void fsts(const Address& dst);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700433
434 void fldl(const Address& src);
435 void fstpl(const Address& dst);
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500436 void fstl(const Address& dst);
437
438 void fstsw();
439
440 void fucompp();
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700441
442 void fnstcw(const Address& dst);
443 void fldcw(const Address& src);
444
445 void fistpl(const Address& dst);
446 void fistps(const Address& dst);
447 void fildl(const Address& src);
Roland Levillain0a186012015-04-13 17:00:20 +0100448 void filds(const Address& src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700449
450 void fincstp();
451 void ffree(const Immediate& index);
452
453 void fsin();
454 void fcos();
455 void fptan();
Mark Mendell24f2dfa2015-01-14 19:51:45 -0500456 void fprem();
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700457
458 void xchgl(Register dst, Register src);
Ian Rogers7caad772012-03-30 01:07:54 -0700459 void xchgl(Register reg, const Address& address);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700460
Nicolas Geoffray3c049742014-09-24 18:10:46 +0100461 void cmpw(const Address& address, const Immediate& imm);
462
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700463 void cmpl(Register reg, const Immediate& imm);
464 void cmpl(Register reg0, Register reg1);
465 void cmpl(Register reg, const Address& address);
466
467 void cmpl(const Address& address, Register reg);
468 void cmpl(const Address& address, const Immediate& imm);
469
470 void testl(Register reg1, Register reg2);
471 void testl(Register reg, const Immediate& imm);
Nicolas Geoffrayf12feb82014-07-17 18:32:41 +0100472 void testl(Register reg1, const Address& address);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700473
474 void andl(Register dst, const Immediate& imm);
475 void andl(Register dst, Register src);
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +0000476 void andl(Register dst, const Address& address);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700477
478 void orl(Register dst, const Immediate& imm);
479 void orl(Register dst, Register src);
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +0000480 void orl(Register dst, const Address& address);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700481
482 void xorl(Register dst, Register src);
Nicolas Geoffrayb55f8352014-04-07 15:26:35 +0100483 void xorl(Register dst, const Immediate& imm);
Nicolas Geoffray9574c4b2014-11-12 13:19:37 +0000484 void xorl(Register dst, const Address& address);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700485
486 void addl(Register dst, Register src);
487 void addl(Register reg, const Immediate& imm);
488 void addl(Register reg, const Address& address);
489
490 void addl(const Address& address, Register reg);
491 void addl(const Address& address, const Immediate& imm);
492
493 void adcl(Register dst, Register src);
494 void adcl(Register reg, const Immediate& imm);
495 void adcl(Register dst, const Address& address);
496
497 void subl(Register dst, Register src);
498 void subl(Register reg, const Immediate& imm);
499 void subl(Register reg, const Address& address);
Mark Mendell09ed1a32015-03-25 08:30:06 -0400500 void subl(const Address& address, Register src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700501
502 void cdq();
503
504 void idivl(Register reg);
505
506 void imull(Register dst, Register src);
507 void imull(Register reg, const Immediate& imm);
Mark Mendell4a2aa4a2015-07-27 16:13:10 -0400508 void imull(Register dst, Register src, const Immediate& imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700509 void imull(Register reg, const Address& address);
510
511 void imull(Register reg);
512 void imull(const Address& address);
513
514 void mull(Register reg);
515 void mull(const Address& address);
516
517 void sbbl(Register dst, Register src);
518 void sbbl(Register reg, const Immediate& imm);
519 void sbbl(Register reg, const Address& address);
Mark Mendell09ed1a32015-03-25 08:30:06 -0400520 void sbbl(const Address& address, Register src);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700521
522 void incl(Register reg);
523 void incl(const Address& address);
524
525 void decl(Register reg);
526 void decl(const Address& address);
527
528 void shll(Register reg, const Immediate& imm);
529 void shll(Register operand, Register shifter);
Mark P Mendell73945692015-04-29 14:56:17 +0000530 void shll(const Address& address, const Immediate& imm);
531 void shll(const Address& address, Register shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700532 void shrl(Register reg, const Immediate& imm);
533 void shrl(Register operand, Register shifter);
Mark P Mendell73945692015-04-29 14:56:17 +0000534 void shrl(const Address& address, const Immediate& imm);
535 void shrl(const Address& address, Register shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700536 void sarl(Register reg, const Immediate& imm);
537 void sarl(Register operand, Register shifter);
Mark P Mendell73945692015-04-29 14:56:17 +0000538 void sarl(const Address& address, const Immediate& imm);
539 void sarl(const Address& address, Register shifter);
Calin Juravle9aec02f2014-11-18 23:06:35 +0000540 void shld(Register dst, Register src, Register shifter);
Mark P Mendell73945692015-04-29 14:56:17 +0000541 void shld(Register dst, Register src, const Immediate& imm);
Calin Juravle9aec02f2014-11-18 23:06:35 +0000542 void shrd(Register dst, Register src, Register shifter);
Mark P Mendell73945692015-04-29 14:56:17 +0000543 void shrd(Register dst, Register src, const Immediate& imm);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700544
545 void negl(Register reg);
546 void notl(Register reg);
547
548 void enter(const Immediate& imm);
549 void leave();
550
551 void ret();
552 void ret(const Immediate& imm);
553
554 void nop();
555 void int3();
556 void hlt();
557
558 void j(Condition condition, Label* label);
Mark Mendell73f455e2015-08-21 09:30:05 -0400559 void j(Condition condition, NearLabel* label);
560 void jecxz(NearLabel* label);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700561
562 void jmp(Register reg);
Ian Rogers7caad772012-03-30 01:07:54 -0700563 void jmp(const Address& address);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700564 void jmp(Label* label);
Mark Mendell73f455e2015-08-21 09:30:05 -0400565 void jmp(NearLabel* label);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700566
Andreas Gampe21030dd2015-05-07 14:46:15 -0700567 void repne_scasw();
agicsaki71311f82015-07-27 11:34:13 -0700568 void repe_cmpsw();
agicsaki970abfb2015-07-31 10:31:14 -0700569 void repe_cmpsl();
Mark Mendellb9c4bbe2015-07-01 14:26:52 -0400570 void rep_movsw();
Andreas Gampe21030dd2015-05-07 14:46:15 -0700571
Ian Rogers2c8f6532011-09-02 17:16:34 -0700572 X86Assembler* lock();
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700573 void cmpxchgl(const Address& address, Register reg);
Mark Mendell58d25fd2015-04-03 14:52:31 -0400574 void cmpxchg8b(const Address& address);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700575
Elliott Hughes79ab9e32012-03-12 15:41:35 -0700576 void mfence();
577
Ian Rogers2c8f6532011-09-02 17:16:34 -0700578 X86Assembler* fs();
Ian Rogersbefbd572014-03-06 01:13:39 -0800579 X86Assembler* gs();
Ian Rogersb033c752011-07-20 12:22:35 -0700580
581 //
582 // Macros for High-level operations.
583 //
584
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700585 void AddImmediate(Register reg, const Immediate& imm);
586
Roland Levillain647b9ed2014-11-27 12:06:00 +0000587 void LoadLongConstant(XmmRegister dst, int64_t value);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700588 void LoadDoubleConstant(XmmRegister dst, double value);
589
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700590 void LockCmpxchgl(const Address& address, Register reg) {
Ian Rogers0d666d82011-08-14 16:03:46 -0700591 lock()->cmpxchgl(address, reg);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700592 }
593
Mark Mendell58d25fd2015-04-03 14:52:31 -0400594 void LockCmpxchg8b(const Address& address) {
595 lock()->cmpxchg8b(address);
596 }
597
Ian Rogersb033c752011-07-20 12:22:35 -0700598 //
599 // Misc. functionality
600 //
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700601 int PreferredLoopAlignment() { return 16; }
602 void Align(int alignment, int offset);
603 void Bind(Label* label);
Mark Mendell73f455e2015-08-21 09:30:05 -0400604 void Bind(NearLabel* label);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700605
Ian Rogers2c8f6532011-09-02 17:16:34 -0700606 //
607 // Overridden common assembler high-level functionality
608 //
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700609
Ian Rogers2c8f6532011-09-02 17:16:34 -0700610 // Emit code that will create an activation on the stack
Ian Rogersdd7624d2014-03-14 17:43:00 -0700611 void BuildFrame(size_t frame_size, ManagedRegister method_reg,
612 const std::vector<ManagedRegister>& callee_save_regs,
613 const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700614
615 // Emit code that will remove an activation from the stack
Ian Rogersdd7624d2014-03-14 17:43:00 -0700616 void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
617 OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700618
Ian Rogersdd7624d2014-03-14 17:43:00 -0700619 void IncreaseFrameSize(size_t adjust) OVERRIDE;
620 void DecreaseFrameSize(size_t adjust) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700621
622 // Store routines
Ian Rogersdd7624d2014-03-14 17:43:00 -0700623 void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE;
624 void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE;
625 void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700626
Ian Rogersdd7624d2014-03-14 17:43:00 -0700627 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700628
Ian Rogersdd7624d2014-03-14 17:43:00 -0700629 void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister scratch)
630 OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700631
Ian Rogersdd7624d2014-03-14 17:43:00 -0700632 void StoreStackOffsetToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
633 ManagedRegister scratch) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700634
Ian Rogersdd7624d2014-03-14 17:43:00 -0700635 void StoreStackPointerToThread32(ThreadOffset<4> thr_offs) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700636
Ian Rogersdd7624d2014-03-14 17:43:00 -0700637 void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
638 ManagedRegister scratch) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700639
640 // Load routines
Ian Rogersdd7624d2014-03-14 17:43:00 -0700641 void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700642
Ian Rogersdd7624d2014-03-14 17:43:00 -0700643 void LoadFromThread32(ManagedRegister dest, ThreadOffset<4> src, size_t size) OVERRIDE;
Ian Rogers5a7a74a2011-09-26 16:32:29 -0700644
Mathieu Chartiere401d142015-04-22 13:56:20 -0700645 void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700646
Mathieu Chartiere401d142015-04-22 13:56:20 -0700647 void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs,
Roland Levillain4d027112015-07-01 15:41:14 +0100648 bool unpoison_reference) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700649
Ian Rogersdd7624d2014-03-14 17:43:00 -0700650 void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700651
Ian Rogersdd7624d2014-03-14 17:43:00 -0700652 void LoadRawPtrFromThread32(ManagedRegister dest, ThreadOffset<4> offs) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700653
654 // Copying routines
Ian Rogersdd7624d2014-03-14 17:43:00 -0700655 void Move(ManagedRegister dest, ManagedRegister src, size_t size) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700656
Ian Rogersdd7624d2014-03-14 17:43:00 -0700657 void CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs,
658 ManagedRegister scratch) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700659
Ian Rogersdd7624d2014-03-14 17:43:00 -0700660 void CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs, ManagedRegister scratch)
661 OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700662
Ian Rogersdd7624d2014-03-14 17:43:00 -0700663 void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700664
Ian Rogersdd7624d2014-03-14 17:43:00 -0700665 void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700666
Ian Rogersdd7624d2014-03-14 17:43:00 -0700667 void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch,
668 size_t size) OVERRIDE;
Ian Rogersdc51b792011-09-22 20:41:37 -0700669
Ian Rogersdd7624d2014-03-14 17:43:00 -0700670 void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch,
671 size_t size) OVERRIDE;
Ian Rogers5a7a74a2011-09-26 16:32:29 -0700672
Ian Rogersdd7624d2014-03-14 17:43:00 -0700673 void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch,
674 size_t size) OVERRIDE;
Ian Rogersdc51b792011-09-22 20:41:37 -0700675
Ian Rogersdd7624d2014-03-14 17:43:00 -0700676 void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
677 ManagedRegister scratch, size_t size) OVERRIDE;
Ian Rogers5a7a74a2011-09-26 16:32:29 -0700678
Ian Rogersdd7624d2014-03-14 17:43:00 -0700679 void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
680 ManagedRegister scratch, size_t size) OVERRIDE;
Ian Rogersdc51b792011-09-22 20:41:37 -0700681
Ian Rogersdd7624d2014-03-14 17:43:00 -0700682 void MemoryBarrier(ManagedRegister) OVERRIDE;
Ian Rogerse5de95b2011-09-18 20:31:38 -0700683
jeffhao58136ca2012-05-24 13:40:11 -0700684 // Sign extension
Ian Rogersdd7624d2014-03-14 17:43:00 -0700685 void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
jeffhao58136ca2012-05-24 13:40:11 -0700686
jeffhaocee4d0c2012-06-15 14:42:01 -0700687 // Zero extension
Ian Rogersdd7624d2014-03-14 17:43:00 -0700688 void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
jeffhaocee4d0c2012-06-15 14:42:01 -0700689
Ian Rogers2c8f6532011-09-02 17:16:34 -0700690 // Exploit fast access in managed code to Thread::Current()
Ian Rogersdd7624d2014-03-14 17:43:00 -0700691 void GetCurrentThread(ManagedRegister tr) OVERRIDE;
692 void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700693
Mathieu Chartier2cebb242015-04-21 16:50:40 -0700694 // Set up out_reg to hold a Object** into the handle scope, or to be null if the
Ian Rogers2c8f6532011-09-02 17:16:34 -0700695 // value is null and null_allowed. in_reg holds a possibly stale reference
Mathieu Chartiereb8167a2014-05-07 15:43:14 -0700696 // that can be used to avoid loading the handle scope entry to see if the value is
Mathieu Chartier2cebb242015-04-21 16:50:40 -0700697 // null.
698 void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset,
699 ManagedRegister in_reg, bool null_allowed) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700700
Mathieu Chartier2cebb242015-04-21 16:50:40 -0700701 // Set up out_off to hold a Object** into the handle scope, or to be null if the
Ian Rogers2c8f6532011-09-02 17:16:34 -0700702 // value is null and null_allowed.
Mathieu Chartier2cebb242015-04-21 16:50:40 -0700703 void CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handlescope_offset,
704 ManagedRegister scratch, bool null_allowed) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700705
Mathieu Chartiereb8167a2014-05-07 15:43:14 -0700706 // src holds a handle scope entry (Object**) load this into dst
707 void LoadReferenceFromHandleScope(ManagedRegister dst, ManagedRegister src) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700708
709 // Heap::VerifyObject on src. In some cases (such as a reference to this) we
710 // know that src may not be null.
Ian Rogersdd7624d2014-03-14 17:43:00 -0700711 void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
712 void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700713
714 // Call to address held at [base+offset]
Ian Rogersdd7624d2014-03-14 17:43:00 -0700715 void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
716 void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
717 void CallFromThread32(ThreadOffset<4> offset, ManagedRegister scratch) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700718
Ian Rogers2c8f6532011-09-02 17:16:34 -0700719 // Generate code to check if Thread::Current()->exception_ is non-null
720 // and branch to a ExceptionSlowPath if it is.
Ian Rogersdd7624d2014-03-14 17:43:00 -0700721 void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700722
Roland Levillain4d027112015-07-01 15:41:14 +0100723 //
724 // Heap poisoning.
725 //
726
727 // Poison a heap reference contained in `reg`.
728 void PoisonHeapReference(Register reg) { negl(reg); }
729 // Unpoison a heap reference contained in `reg`.
730 void UnpoisonHeapReference(Register reg) { negl(reg); }
731 // Unpoison a heap reference contained in `reg` if heap poisoning is enabled.
732 void MaybeUnpoisonHeapReference(Register reg) {
733 if (kPoisonHeapReferences) {
734 UnpoisonHeapReference(reg);
735 }
736 }
737
Mark Mendell0616ae02015-04-17 12:49:27 -0400738 // Add a double to the constant area, returning the offset into
739 // the constant area where the literal resides.
740 int AddDouble(double v) { return constant_area_.AddDouble(v); }
741
742 // Add a float to the constant area, returning the offset into
743 // the constant area where the literal resides.
744 int AddFloat(float v) { return constant_area_.AddFloat(v); }
745
746 // Add an int32_t to the constant area, returning the offset into
747 // the constant area where the literal resides.
748 int AddInt32(int32_t v) { return constant_area_.AddInt32(v); }
749
750 // Add an int64_t to the constant area, returning the offset into
751 // the constant area where the literal resides.
752 int AddInt64(int64_t v) { return constant_area_.AddInt64(v); }
753
754 // Add the contents of the constant area to the assembler buffer.
755 void AddConstantArea();
756
757 // Is the constant area empty? Return true if there are no literals in the constant area.
758 bool IsConstantAreaEmpty() const { return constant_area_.IsEmpty(); }
759 void AddConstantAreaFixup(AssemblerFixup* fixup) { constant_area_.AddFixup(fixup); }
760
Ian Rogers2c8f6532011-09-02 17:16:34 -0700761 private:
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700762 inline void EmitUint8(uint8_t value);
763 inline void EmitInt32(int32_t value);
764 inline void EmitRegisterOperand(int rm, int reg);
765 inline void EmitXmmRegisterOperand(int rm, XmmRegister reg);
766 inline void EmitFixup(AssemblerFixup* fixup);
767 inline void EmitOperandSizeOverride();
768
769 void EmitOperand(int rm, const Operand& operand);
770 void EmitImmediate(const Immediate& imm);
771 void EmitComplex(int rm, const Operand& operand, const Immediate& immediate);
772 void EmitLabel(Label* label, int instruction_size);
773 void EmitLabelLink(Label* label);
Mark Mendell73f455e2015-08-21 09:30:05 -0400774 void EmitLabelLink(NearLabel* label);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700775
Mark P Mendell73945692015-04-29 14:56:17 +0000776 void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm);
777 void EmitGenericShift(int rm, const Operand& operand, Register shifter);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700778
Mark Mendell0616ae02015-04-17 12:49:27 -0400779 ConstantArea constant_area_;
780
Ian Rogers2c8f6532011-09-02 17:16:34 -0700781 DISALLOW_COPY_AND_ASSIGN(X86Assembler);
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700782};
783
Ian Rogers2c8f6532011-09-02 17:16:34 -0700784inline void X86Assembler::EmitUint8(uint8_t value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700785 buffer_.Emit<uint8_t>(value);
786}
787
Ian Rogers2c8f6532011-09-02 17:16:34 -0700788inline void X86Assembler::EmitInt32(int32_t value) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700789 buffer_.Emit<int32_t>(value);
790}
791
Ian Rogers2c8f6532011-09-02 17:16:34 -0700792inline void X86Assembler::EmitRegisterOperand(int rm, int reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700793 CHECK_GE(rm, 0);
794 CHECK_LT(rm, 8);
795 buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg);
796}
797
Ian Rogers2c8f6532011-09-02 17:16:34 -0700798inline void X86Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700799 EmitRegisterOperand(rm, static_cast<Register>(reg));
800}
801
Ian Rogers2c8f6532011-09-02 17:16:34 -0700802inline void X86Assembler::EmitFixup(AssemblerFixup* fixup) {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700803 buffer_.EmitFixup(fixup);
804}
805
Ian Rogers2c8f6532011-09-02 17:16:34 -0700806inline void X86Assembler::EmitOperandSizeOverride() {
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700807 EmitUint8(0x66);
808}
809
Ian Rogers2c8f6532011-09-02 17:16:34 -0700810// Slowpath entered when Thread::Current()->_exception is non-null
Ian Rogersdd7624d2014-03-14 17:43:00 -0700811class X86ExceptionSlowPath FINAL : public SlowPath {
Ian Rogers2c8f6532011-09-02 17:16:34 -0700812 public:
Brian Carlstrom93ba8932013-07-17 21:31:49 -0700813 explicit X86ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {}
Ian Rogersdd7624d2014-03-14 17:43:00 -0700814 virtual void Emit(Assembler *sp_asm) OVERRIDE;
Ian Rogers00f7d0e2012-07-19 15:28:27 -0700815 private:
816 const size_t stack_adjust_;
Ian Rogers2c8f6532011-09-02 17:16:34 -0700817};
818
Ian Rogers2c8f6532011-09-02 17:16:34 -0700819} // namespace x86
Carl Shapiro6b6b5f02011-06-21 15:05:09 -0700820} // namespace art
Carl Shapiroa5d5cfd2011-06-21 12:46:59 -0700821
Ian Rogers166db042013-07-26 12:05:57 -0700822#endif // ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_