Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_VIXL_H_ |
| 18 | #define ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_VIXL_H_ |
| 19 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 20 | #include "base/enums.h" |
| 21 | #include "code_generator.h" |
Artem Serov | cfbe913 | 2016-10-14 15:58:56 +0100 | [diff] [blame] | 22 | #include "common_arm.h" |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 23 | #include "driver/compiler_options.h" |
| 24 | #include "nodes.h" |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 25 | #include "parallel_move_resolver.h" |
Andreas Gampe | 8cf9cb3 | 2017-07-19 09:28:38 -0700 | [diff] [blame] | 26 | #include "string_reference.h" |
Mathieu Chartier | dbddc22 | 2017-05-24 12:04:13 -0700 | [diff] [blame] | 27 | #include "type_reference.h" |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 28 | #include "utils/arm/assembler_arm_vixl.h" |
| 29 | |
| 30 | // TODO(VIXL): make vixl clean wrt -Wshadow. |
| 31 | #pragma GCC diagnostic push |
| 32 | #pragma GCC diagnostic ignored "-Wshadow" |
| 33 | #include "aarch32/constants-aarch32.h" |
| 34 | #include "aarch32/instructions-aarch32.h" |
| 35 | #include "aarch32/macro-assembler-aarch32.h" |
| 36 | #pragma GCC diagnostic pop |
| 37 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 38 | namespace art { |
| 39 | namespace arm { |
| 40 | |
Roland Levillain | ba650a4 | 2017-03-06 13:52:32 +0000 | [diff] [blame] | 41 | // This constant is used as an approximate margin when emission of veneer and literal pools |
| 42 | // must be blocked. |
| 43 | static constexpr int kMaxMacroInstructionSizeInBytes = |
| 44 | 15 * vixl::aarch32::kMaxInstructionSizeInBytes; |
| 45 | |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 46 | static const vixl::aarch32::Register kParameterCoreRegistersVIXL[] = { |
| 47 | vixl::aarch32::r1, |
| 48 | vixl::aarch32::r2, |
| 49 | vixl::aarch32::r3 |
| 50 | }; |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 51 | static const size_t kParameterCoreRegistersLengthVIXL = arraysize(kParameterCoreRegistersVIXL); |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 52 | static const vixl::aarch32::SRegister kParameterFpuRegistersVIXL[] = { |
| 53 | vixl::aarch32::s0, |
| 54 | vixl::aarch32::s1, |
| 55 | vixl::aarch32::s2, |
| 56 | vixl::aarch32::s3, |
| 57 | vixl::aarch32::s4, |
| 58 | vixl::aarch32::s5, |
| 59 | vixl::aarch32::s6, |
| 60 | vixl::aarch32::s7, |
| 61 | vixl::aarch32::s8, |
| 62 | vixl::aarch32::s9, |
| 63 | vixl::aarch32::s10, |
| 64 | vixl::aarch32::s11, |
| 65 | vixl::aarch32::s12, |
| 66 | vixl::aarch32::s13, |
| 67 | vixl::aarch32::s14, |
| 68 | vixl::aarch32::s15 |
| 69 | }; |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 70 | static const size_t kParameterFpuRegistersLengthVIXL = arraysize(kParameterFpuRegistersVIXL); |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 71 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 72 | static const vixl::aarch32::Register kMethodRegister = vixl::aarch32::r0; |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 73 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 74 | static const vixl::aarch32::Register kCoreAlwaysSpillRegister = vixl::aarch32::r5; |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 75 | |
Roland Levillain | 6d729a7 | 2017-06-30 18:34:01 +0100 | [diff] [blame] | 76 | // Callee saves core registers r5, r6, r7, r8 (except when emitting Baker |
| 77 | // read barriers, where it is used as Marking Register), r10, r11, and lr. |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 78 | static const vixl::aarch32::RegisterList kCoreCalleeSaves = vixl::aarch32::RegisterList::Union( |
| 79 | vixl::aarch32::RegisterList(vixl::aarch32::r5, |
| 80 | vixl::aarch32::r6, |
Roland Levillain | 6d729a7 | 2017-06-30 18:34:01 +0100 | [diff] [blame] | 81 | vixl::aarch32::r7), |
| 82 | // Do not consider r8 as a callee-save register with Baker read barriers. |
| 83 | ((kEmitCompilerReadBarrier && kUseBakerReadBarrier) |
| 84 | ? vixl::aarch32::RegisterList() |
| 85 | : vixl::aarch32::RegisterList(vixl::aarch32::r8)), |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 86 | vixl::aarch32::RegisterList(vixl::aarch32::r10, |
| 87 | vixl::aarch32::r11, |
| 88 | vixl::aarch32::lr)); |
| 89 | |
| 90 | // Callee saves FP registers s16 to s31 inclusive. |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 91 | static const vixl::aarch32::SRegisterList kFpuCalleeSaves = |
| 92 | vixl::aarch32::SRegisterList(vixl::aarch32::s16, 16); |
| 93 | |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 94 | static const vixl::aarch32::Register kRuntimeParameterCoreRegistersVIXL[] = { |
| 95 | vixl::aarch32::r0, |
| 96 | vixl::aarch32::r1, |
| 97 | vixl::aarch32::r2, |
| 98 | vixl::aarch32::r3 |
| 99 | }; |
| 100 | static const size_t kRuntimeParameterCoreRegistersLengthVIXL = |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 101 | arraysize(kRuntimeParameterCoreRegistersVIXL); |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 102 | static const vixl::aarch32::SRegister kRuntimeParameterFpuRegistersVIXL[] = { |
| 103 | vixl::aarch32::s0, |
| 104 | vixl::aarch32::s1, |
| 105 | vixl::aarch32::s2, |
| 106 | vixl::aarch32::s3 |
| 107 | }; |
| 108 | static const size_t kRuntimeParameterFpuRegistersLengthVIXL = |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 109 | arraysize(kRuntimeParameterFpuRegistersVIXL); |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 110 | |
| 111 | class LoadClassSlowPathARMVIXL; |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 112 | class CodeGeneratorARMVIXL; |
| 113 | |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 114 | using VIXLInt32Literal = vixl::aarch32::Literal<int32_t>; |
| 115 | using VIXLUInt32Literal = vixl::aarch32::Literal<uint32_t>; |
| 116 | |
Artem Serov | 551b28f | 2016-10-18 19:11:30 +0100 | [diff] [blame] | 117 | class JumpTableARMVIXL : public DeletableArenaObject<kArenaAllocSwitchTable> { |
| 118 | public: |
| 119 | explicit JumpTableARMVIXL(HPackedSwitch* switch_instr) |
Artem Serov | 09a940d | 2016-11-11 16:15:11 +0000 | [diff] [blame] | 120 | : switch_instr_(switch_instr), |
| 121 | table_start_(), |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 122 | bb_addresses_(switch_instr->GetAllocator()->Adapter(kArenaAllocCodeGenerator)) { |
Artem Serov | 09a940d | 2016-11-11 16:15:11 +0000 | [diff] [blame] | 123 | uint32_t num_entries = switch_instr_->GetNumEntries(); |
| 124 | for (uint32_t i = 0; i < num_entries; i++) { |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 125 | VIXLInt32Literal *lit = new VIXLInt32Literal(0, vixl32::RawLiteral::kManuallyPlaced); |
Artem Serov | 09a940d | 2016-11-11 16:15:11 +0000 | [diff] [blame] | 126 | bb_addresses_.emplace_back(lit); |
| 127 | } |
| 128 | } |
Artem Serov | 551b28f | 2016-10-18 19:11:30 +0100 | [diff] [blame] | 129 | |
| 130 | vixl::aarch32::Label* GetTableStartLabel() { return &table_start_; } |
| 131 | |
| 132 | void EmitTable(CodeGeneratorARMVIXL* codegen); |
Artem Serov | 09a940d | 2016-11-11 16:15:11 +0000 | [diff] [blame] | 133 | void FixTable(CodeGeneratorARMVIXL* codegen); |
Artem Serov | 551b28f | 2016-10-18 19:11:30 +0100 | [diff] [blame] | 134 | |
| 135 | private: |
| 136 | HPackedSwitch* const switch_instr_; |
| 137 | vixl::aarch32::Label table_start_; |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 138 | ArenaVector<std::unique_ptr<VIXLInt32Literal>> bb_addresses_; |
Artem Serov | 551b28f | 2016-10-18 19:11:30 +0100 | [diff] [blame] | 139 | |
| 140 | DISALLOW_COPY_AND_ASSIGN(JumpTableARMVIXL); |
| 141 | }; |
| 142 | |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 143 | class InvokeRuntimeCallingConventionARMVIXL |
| 144 | : public CallingConvention<vixl::aarch32::Register, vixl::aarch32::SRegister> { |
| 145 | public: |
| 146 | InvokeRuntimeCallingConventionARMVIXL() |
| 147 | : CallingConvention(kRuntimeParameterCoreRegistersVIXL, |
| 148 | kRuntimeParameterCoreRegistersLengthVIXL, |
| 149 | kRuntimeParameterFpuRegistersVIXL, |
| 150 | kRuntimeParameterFpuRegistersLengthVIXL, |
| 151 | kArmPointerSize) {} |
| 152 | |
| 153 | private: |
| 154 | DISALLOW_COPY_AND_ASSIGN(InvokeRuntimeCallingConventionARMVIXL); |
| 155 | }; |
| 156 | |
| 157 | class InvokeDexCallingConventionARMVIXL |
| 158 | : public CallingConvention<vixl::aarch32::Register, vixl::aarch32::SRegister> { |
| 159 | public: |
| 160 | InvokeDexCallingConventionARMVIXL() |
| 161 | : CallingConvention(kParameterCoreRegistersVIXL, |
| 162 | kParameterCoreRegistersLengthVIXL, |
| 163 | kParameterFpuRegistersVIXL, |
| 164 | kParameterFpuRegistersLengthVIXL, |
| 165 | kArmPointerSize) {} |
| 166 | |
| 167 | private: |
| 168 | DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionARMVIXL); |
| 169 | }; |
| 170 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 171 | class InvokeDexCallingConventionVisitorARMVIXL : public InvokeDexCallingConventionVisitor { |
| 172 | public: |
| 173 | InvokeDexCallingConventionVisitorARMVIXL() {} |
| 174 | virtual ~InvokeDexCallingConventionVisitorARMVIXL() {} |
| 175 | |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 176 | Location GetNextLocation(DataType::Type type) OVERRIDE; |
| 177 | Location GetReturnLocation(DataType::Type type) const OVERRIDE; |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 178 | Location GetMethodLocation() const OVERRIDE; |
| 179 | |
| 180 | private: |
| 181 | InvokeDexCallingConventionARMVIXL calling_convention; |
| 182 | uint32_t double_index_ = 0; |
| 183 | |
| 184 | DISALLOW_COPY_AND_ASSIGN(InvokeDexCallingConventionVisitorARMVIXL); |
| 185 | }; |
| 186 | |
Artem Serov | cfbe913 | 2016-10-14 15:58:56 +0100 | [diff] [blame] | 187 | class FieldAccessCallingConventionARMVIXL : public FieldAccessCallingConvention { |
| 188 | public: |
| 189 | FieldAccessCallingConventionARMVIXL() {} |
| 190 | |
| 191 | Location GetObjectLocation() const OVERRIDE { |
| 192 | return helpers::LocationFrom(vixl::aarch32::r1); |
| 193 | } |
| 194 | Location GetFieldIndexLocation() const OVERRIDE { |
| 195 | return helpers::LocationFrom(vixl::aarch32::r0); |
| 196 | } |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 197 | Location GetReturnLocation(DataType::Type type) const OVERRIDE { |
| 198 | return DataType::Is64BitType(type) |
Artem Serov | cfbe913 | 2016-10-14 15:58:56 +0100 | [diff] [blame] | 199 | ? helpers::LocationFrom(vixl::aarch32::r0, vixl::aarch32::r1) |
| 200 | : helpers::LocationFrom(vixl::aarch32::r0); |
| 201 | } |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 202 | Location GetSetValueLocation(DataType::Type type, bool is_instance) const OVERRIDE { |
| 203 | return DataType::Is64BitType(type) |
Nicolas Geoffray | a72859d | 2017-01-26 22:47:27 +0000 | [diff] [blame] | 204 | ? helpers::LocationFrom(vixl::aarch32::r2, vixl::aarch32::r3) |
Artem Serov | cfbe913 | 2016-10-14 15:58:56 +0100 | [diff] [blame] | 205 | : (is_instance |
| 206 | ? helpers::LocationFrom(vixl::aarch32::r2) |
| 207 | : helpers::LocationFrom(vixl::aarch32::r1)); |
| 208 | } |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 209 | Location GetFpuLocation(DataType::Type type) const OVERRIDE { |
| 210 | return DataType::Is64BitType(type) |
Artem Serov | cfbe913 | 2016-10-14 15:58:56 +0100 | [diff] [blame] | 211 | ? helpers::LocationFrom(vixl::aarch32::s0, vixl::aarch32::s1) |
| 212 | : helpers::LocationFrom(vixl::aarch32::s0); |
| 213 | } |
| 214 | |
| 215 | private: |
| 216 | DISALLOW_COPY_AND_ASSIGN(FieldAccessCallingConventionARMVIXL); |
| 217 | }; |
| 218 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 219 | class SlowPathCodeARMVIXL : public SlowPathCode { |
| 220 | public: |
| 221 | explicit SlowPathCodeARMVIXL(HInstruction* instruction) |
| 222 | : SlowPathCode(instruction), entry_label_(), exit_label_() {} |
| 223 | |
| 224 | vixl::aarch32::Label* GetEntryLabel() { return &entry_label_; } |
| 225 | vixl::aarch32::Label* GetExitLabel() { return &exit_label_; } |
| 226 | |
| 227 | void SaveLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) OVERRIDE; |
| 228 | void RestoreLiveRegisters(CodeGenerator* codegen, LocationSummary* locations) OVERRIDE; |
| 229 | |
| 230 | private: |
| 231 | vixl::aarch32::Label entry_label_; |
| 232 | vixl::aarch32::Label exit_label_; |
| 233 | |
| 234 | DISALLOW_COPY_AND_ASSIGN(SlowPathCodeARMVIXL); |
| 235 | }; |
| 236 | |
| 237 | class ParallelMoveResolverARMVIXL : public ParallelMoveResolverWithSwap { |
| 238 | public: |
| 239 | ParallelMoveResolverARMVIXL(ArenaAllocator* allocator, CodeGeneratorARMVIXL* codegen) |
| 240 | : ParallelMoveResolverWithSwap(allocator), codegen_(codegen) {} |
| 241 | |
| 242 | void EmitMove(size_t index) OVERRIDE; |
| 243 | void EmitSwap(size_t index) OVERRIDE; |
| 244 | void SpillScratch(int reg) OVERRIDE; |
| 245 | void RestoreScratch(int reg) OVERRIDE; |
| 246 | |
| 247 | ArmVIXLAssembler* GetAssembler() const; |
| 248 | |
| 249 | private: |
Alexandre Rames | 9c19bd6 | 2016-10-24 11:50:32 +0100 | [diff] [blame] | 250 | void Exchange(vixl32::Register reg, int mem); |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 251 | void Exchange(int mem1, int mem2); |
| 252 | |
| 253 | CodeGeneratorARMVIXL* const codegen_; |
| 254 | |
| 255 | DISALLOW_COPY_AND_ASSIGN(ParallelMoveResolverARMVIXL); |
| 256 | }; |
| 257 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 258 | class LocationsBuilderARMVIXL : public HGraphVisitor { |
| 259 | public: |
| 260 | LocationsBuilderARMVIXL(HGraph* graph, CodeGeneratorARMVIXL* codegen) |
| 261 | : HGraphVisitor(graph), codegen_(codegen) {} |
| 262 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 263 | #define DECLARE_VISIT_INSTRUCTION(name, super) \ |
| 264 | void Visit##name(H##name* instr) OVERRIDE; |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 265 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 266 | FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION) |
| 267 | FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION) |
| 268 | FOR_EACH_CONCRETE_INSTRUCTION_SHARED(DECLARE_VISIT_INSTRUCTION) |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 269 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 270 | #undef DECLARE_VISIT_INSTRUCTION |
| 271 | |
| 272 | void VisitInstruction(HInstruction* instruction) OVERRIDE { |
| 273 | LOG(FATAL) << "Unreachable instruction " << instruction->DebugName() |
| 274 | << " (id " << instruction->GetId() << ")"; |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 275 | } |
| 276 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 277 | private: |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 278 | void HandleInvoke(HInvoke* invoke); |
Artem Serov | 02109dd | 2016-09-23 17:17:54 +0100 | [diff] [blame] | 279 | void HandleBitwiseOperation(HBinaryOperation* operation, Opcode opcode); |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 280 | void HandleCondition(HCondition* condition); |
Artem Serov | 02109dd | 2016-09-23 17:17:54 +0100 | [diff] [blame] | 281 | void HandleIntegerRotate(LocationSummary* locations); |
| 282 | void HandleLongRotate(LocationSummary* locations); |
| 283 | void HandleShift(HBinaryOperation* operation); |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 284 | void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info); |
| 285 | void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info); |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 286 | |
Alexandre Rames | 9c19bd6 | 2016-10-24 11:50:32 +0100 | [diff] [blame] | 287 | Location ArithmeticZeroOrFpuRegister(HInstruction* input); |
Artem Serov | 02109dd | 2016-09-23 17:17:54 +0100 | [diff] [blame] | 288 | Location ArmEncodableConstantOrRegister(HInstruction* constant, Opcode opcode); |
| 289 | bool CanEncodeConstantAsImmediate(HConstant* input_cst, Opcode opcode); |
| 290 | bool CanEncodeConstantAsImmediate(uint32_t value, Opcode opcode, SetCc set_cc = kCcDontCare); |
Alexandre Rames | 9c19bd6 | 2016-10-24 11:50:32 +0100 | [diff] [blame] | 291 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 292 | CodeGeneratorARMVIXL* const codegen_; |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 293 | InvokeDexCallingConventionVisitorARMVIXL parameter_visitor_; |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 294 | |
| 295 | DISALLOW_COPY_AND_ASSIGN(LocationsBuilderARMVIXL); |
| 296 | }; |
| 297 | |
| 298 | class InstructionCodeGeneratorARMVIXL : public InstructionCodeGenerator { |
| 299 | public: |
| 300 | InstructionCodeGeneratorARMVIXL(HGraph* graph, CodeGeneratorARMVIXL* codegen); |
| 301 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 302 | #define DECLARE_VISIT_INSTRUCTION(name, super) \ |
| 303 | void Visit##name(H##name* instr) OVERRIDE; |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 304 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 305 | FOR_EACH_CONCRETE_INSTRUCTION_COMMON(DECLARE_VISIT_INSTRUCTION) |
| 306 | FOR_EACH_CONCRETE_INSTRUCTION_ARM(DECLARE_VISIT_INSTRUCTION) |
| 307 | FOR_EACH_CONCRETE_INSTRUCTION_SHARED(DECLARE_VISIT_INSTRUCTION) |
| 308 | |
| 309 | #undef DECLARE_VISIT_INSTRUCTION |
| 310 | |
| 311 | void VisitInstruction(HInstruction* instruction) OVERRIDE { |
| 312 | LOG(FATAL) << "Unreachable instruction " << instruction->DebugName() |
| 313 | << " (id " << instruction->GetId() << ")"; |
| 314 | } |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 315 | |
| 316 | ArmVIXLAssembler* GetAssembler() const { return assembler_; } |
xueliang.zhong | f51bc62 | 2016-11-04 09:23:32 +0000 | [diff] [blame] | 317 | ArmVIXLMacroAssembler* GetVIXLAssembler() { return GetAssembler()->GetVIXLAssembler(); } |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 318 | |
| 319 | private: |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 320 | // Generate code for the given suspend check. If not null, `successor` |
| 321 | // is the block to branch to if the suspend check is not needed, and after |
| 322 | // the suspend call. |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 323 | void GenerateSuspendCheck(HSuspendCheck* instruction, HBasicBlock* successor); |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 324 | void GenerateClassInitializationCheck(LoadClassSlowPathARMVIXL* slow_path, |
| 325 | vixl32::Register class_reg); |
Artem Serov | 02109dd | 2016-09-23 17:17:54 +0100 | [diff] [blame] | 326 | void GenerateAndConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value); |
| 327 | void GenerateOrrConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value); |
| 328 | void GenerateEorConst(vixl::aarch32::Register out, vixl::aarch32::Register first, uint32_t value); |
Anton Kirilov | dda4396 | 2016-11-21 19:55:20 +0000 | [diff] [blame] | 329 | void GenerateAddLongConst(Location out, Location first, uint64_t value); |
Artem Serov | 02109dd | 2016-09-23 17:17:54 +0100 | [diff] [blame] | 330 | void HandleBitwiseOperation(HBinaryOperation* operation); |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 331 | void HandleCondition(HCondition* condition); |
Artem Serov | 02109dd | 2016-09-23 17:17:54 +0100 | [diff] [blame] | 332 | void HandleIntegerRotate(HRor* ror); |
| 333 | void HandleLongRotate(HRor* ror); |
| 334 | void HandleShift(HBinaryOperation* operation); |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 335 | |
| 336 | void GenerateWideAtomicStore(vixl::aarch32::Register addr, |
| 337 | uint32_t offset, |
| 338 | vixl::aarch32::Register value_lo, |
| 339 | vixl::aarch32::Register value_hi, |
| 340 | vixl::aarch32::Register temp1, |
| 341 | vixl::aarch32::Register temp2, |
| 342 | HInstruction* instruction); |
| 343 | void GenerateWideAtomicLoad(vixl::aarch32::Register addr, |
| 344 | uint32_t offset, |
| 345 | vixl::aarch32::Register out_lo, |
| 346 | vixl::aarch32::Register out_hi); |
| 347 | |
| 348 | void HandleFieldSet(HInstruction* instruction, |
| 349 | const FieldInfo& field_info, |
| 350 | bool value_can_be_null); |
| 351 | void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info); |
| 352 | |
Artem Serov | cfbe913 | 2016-10-14 15:58:56 +0100 | [diff] [blame] | 353 | // Generate a heap reference load using one register `out`: |
| 354 | // |
| 355 | // out <- *(out + offset) |
| 356 | // |
| 357 | // while honoring heap poisoning and/or read barriers (if any). |
| 358 | // |
| 359 | // Location `maybe_temp` is used when generating a read barrier and |
| 360 | // shall be a register in that case; it may be an invalid location |
| 361 | // otherwise. |
| 362 | void GenerateReferenceLoadOneRegister(HInstruction* instruction, |
| 363 | Location out, |
| 364 | uint32_t offset, |
Artem Serov | 657022c | 2016-11-23 14:19:38 +0000 | [diff] [blame] | 365 | Location maybe_temp, |
| 366 | ReadBarrierOption read_barrier_option); |
Anton Kirilov | e28d9ae | 2016-10-25 18:17:23 +0100 | [diff] [blame] | 367 | // Generate a heap reference load using two different registers |
| 368 | // `out` and `obj`: |
| 369 | // |
| 370 | // out <- *(obj + offset) |
| 371 | // |
| 372 | // while honoring heap poisoning and/or read barriers (if any). |
| 373 | // |
| 374 | // Location `maybe_temp` is used when generating a Baker's (fast |
| 375 | // path) read barrier and shall be a register in that case; it may |
| 376 | // be an invalid location otherwise. |
| 377 | void GenerateReferenceLoadTwoRegisters(HInstruction* instruction, |
| 378 | Location out, |
| 379 | Location obj, |
| 380 | uint32_t offset, |
Artem Serov | 657022c | 2016-11-23 14:19:38 +0000 | [diff] [blame] | 381 | Location maybe_temp, |
| 382 | ReadBarrierOption read_barrier_option); |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 383 | // Generate a GC root reference load: |
| 384 | // |
| 385 | // root <- *(obj + offset) |
| 386 | // |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 387 | // while honoring read barriers based on read_barrier_option. |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 388 | void GenerateGcRootFieldLoad(HInstruction* instruction, |
| 389 | Location root, |
| 390 | vixl::aarch32::Register obj, |
| 391 | uint32_t offset, |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 392 | ReadBarrierOption read_barrier_option); |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 393 | void GenerateTestAndBranch(HInstruction* instruction, |
| 394 | size_t condition_input_index, |
| 395 | vixl::aarch32::Label* true_target, |
xueliang.zhong | f51bc62 | 2016-11-04 09:23:32 +0000 | [diff] [blame] | 396 | vixl::aarch32::Label* false_target, |
| 397 | bool far_target = true); |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 398 | void GenerateCompareTestAndBranch(HCondition* condition, |
| 399 | vixl::aarch32::Label* true_target, |
Anton Kirilov | fd52253 | 2017-05-10 12:46:57 +0100 | [diff] [blame] | 400 | vixl::aarch32::Label* false_target, |
| 401 | bool is_far_target = true); |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 402 | void DivRemOneOrMinusOne(HBinaryOperation* instruction); |
| 403 | void DivRemByPowerOfTwo(HBinaryOperation* instruction); |
| 404 | void GenerateDivRemWithAnyConstant(HBinaryOperation* instruction); |
| 405 | void GenerateDivRemConstantIntegral(HBinaryOperation* instruction); |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 406 | void HandleGoto(HInstruction* got, HBasicBlock* successor); |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 407 | |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 408 | vixl::aarch32::MemOperand VecAddress( |
| 409 | HVecMemoryOperation* instruction, |
| 410 | // This function may acquire a scratch register. |
| 411 | vixl::aarch32::UseScratchRegisterScope* temps_scope, |
| 412 | /*out*/ vixl32::Register* scratch); |
| 413 | vixl::aarch32::AlignedMemOperand VecAddressUnaligned( |
| 414 | HVecMemoryOperation* instruction, |
| 415 | // This function may acquire a scratch register. |
| 416 | vixl::aarch32::UseScratchRegisterScope* temps_scope, |
| 417 | /*out*/ vixl32::Register* scratch); |
| 418 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 419 | ArmVIXLAssembler* const assembler_; |
| 420 | CodeGeneratorARMVIXL* const codegen_; |
| 421 | |
| 422 | DISALLOW_COPY_AND_ASSIGN(InstructionCodeGeneratorARMVIXL); |
| 423 | }; |
| 424 | |
| 425 | class CodeGeneratorARMVIXL : public CodeGenerator { |
| 426 | public: |
| 427 | CodeGeneratorARMVIXL(HGraph* graph, |
| 428 | const ArmInstructionSetFeatures& isa_features, |
| 429 | const CompilerOptions& compiler_options, |
| 430 | OptimizingCompilerStats* stats = nullptr); |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 431 | virtual ~CodeGeneratorARMVIXL() {} |
| 432 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 433 | void GenerateFrameEntry() OVERRIDE; |
| 434 | void GenerateFrameExit() OVERRIDE; |
| 435 | void Bind(HBasicBlock* block) OVERRIDE; |
| 436 | void MoveConstant(Location destination, int32_t value) OVERRIDE; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 437 | void MoveLocation(Location dst, Location src, DataType::Type dst_type) OVERRIDE; |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 438 | void AddLocationAsTemp(Location location, LocationSummary* locations) OVERRIDE; |
| 439 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 440 | size_t SaveCoreRegister(size_t stack_index, uint32_t reg_id) OVERRIDE; |
| 441 | size_t RestoreCoreRegister(size_t stack_index, uint32_t reg_id) OVERRIDE; |
| 442 | size_t SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) OVERRIDE; |
| 443 | size_t RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) OVERRIDE; |
| 444 | |
| 445 | size_t GetWordSize() const OVERRIDE { |
| 446 | return static_cast<size_t>(kArmPointerSize); |
| 447 | } |
| 448 | |
| 449 | size_t GetFloatingPointSpillSlotSize() const OVERRIDE { return vixl::aarch32::kRegSizeInBytes; } |
| 450 | |
| 451 | HGraphVisitor* GetLocationBuilder() OVERRIDE { return &location_builder_; } |
| 452 | |
| 453 | HGraphVisitor* GetInstructionVisitor() OVERRIDE { return &instruction_visitor_; } |
| 454 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 455 | ArmVIXLAssembler* GetAssembler() OVERRIDE { return &assembler_; } |
| 456 | |
| 457 | const ArmVIXLAssembler& GetAssembler() const OVERRIDE { return assembler_; } |
| 458 | |
xueliang.zhong | f51bc62 | 2016-11-04 09:23:32 +0000 | [diff] [blame] | 459 | ArmVIXLMacroAssembler* GetVIXLAssembler() { return GetAssembler()->GetVIXLAssembler(); } |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 460 | |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 461 | uintptr_t GetAddressOf(HBasicBlock* block) OVERRIDE { |
| 462 | vixl::aarch32::Label* block_entry_label = GetLabelOf(block); |
| 463 | DCHECK(block_entry_label->IsBound()); |
| 464 | return block_entry_label->GetLocation(); |
| 465 | } |
| 466 | |
Artem Serov | 09a940d | 2016-11-11 16:15:11 +0000 | [diff] [blame] | 467 | void FixJumpTables(); |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 468 | void SetupBlockedRegisters() const OVERRIDE; |
| 469 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 470 | void DumpCoreRegister(std::ostream& stream, int reg) const OVERRIDE; |
| 471 | void DumpFloatingPointRegister(std::ostream& stream, int reg) const OVERRIDE; |
| 472 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 473 | ParallelMoveResolver* GetMoveResolver() OVERRIDE { return &move_resolver_; } |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 474 | InstructionSet GetInstructionSet() const OVERRIDE { return InstructionSet::kThumb2; } |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 475 | // Helper method to move a 32-bit value between two locations. |
| 476 | void Move32(Location destination, Location source); |
| 477 | |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 478 | void LoadFromShiftedRegOffset(DataType::Type type, |
Scott Wakeling | c34dba7 | 2016-10-03 10:14:44 +0100 | [diff] [blame] | 479 | Location out_loc, |
| 480 | vixl::aarch32::Register base, |
| 481 | vixl::aarch32::Register reg_index, |
| 482 | vixl::aarch32::Condition cond = vixl::aarch32::al); |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 483 | void StoreToShiftedRegOffset(DataType::Type type, |
Scott Wakeling | c34dba7 | 2016-10-03 10:14:44 +0100 | [diff] [blame] | 484 | Location out_loc, |
| 485 | vixl::aarch32::Register base, |
| 486 | vixl::aarch32::Register reg_index, |
| 487 | vixl::aarch32::Condition cond = vixl::aarch32::al); |
| 488 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 489 | // Generate code to invoke a runtime entry point. |
| 490 | void InvokeRuntime(QuickEntrypointEnum entrypoint, |
| 491 | HInstruction* instruction, |
| 492 | uint32_t dex_pc, |
| 493 | SlowPathCode* slow_path = nullptr) OVERRIDE; |
| 494 | |
| 495 | // Generate code to invoke a runtime entry point, but do not record |
| 496 | // PC-related information in a stack map. |
| 497 | void InvokeRuntimeWithoutRecordingPcInfo(int32_t entry_point_offset, |
| 498 | HInstruction* instruction, |
| 499 | SlowPathCode* slow_path); |
| 500 | |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 501 | // Emit a write barrier. |
| 502 | void MarkGCCard(vixl::aarch32::Register temp, |
| 503 | vixl::aarch32::Register card, |
| 504 | vixl::aarch32::Register object, |
| 505 | vixl::aarch32::Register value, |
| 506 | bool can_be_null); |
| 507 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 508 | void GenerateMemoryBarrier(MemBarrierKind kind); |
| 509 | |
| 510 | vixl::aarch32::Label* GetLabelOf(HBasicBlock* block) { |
| 511 | block = FirstNonEmptyBlock(block); |
| 512 | return &(block_labels_[block->GetBlockId()]); |
| 513 | } |
| 514 | |
Donghui Bai | 426b49c | 2016-11-08 14:55:38 +0800 | [diff] [blame] | 515 | vixl32::Label* GetFinalLabel(HInstruction* instruction, vixl32::Label* final_label); |
| 516 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 517 | void Initialize() OVERRIDE { |
| 518 | block_labels_.resize(GetGraph()->GetBlocks().size()); |
| 519 | } |
| 520 | |
| 521 | void Finalize(CodeAllocator* allocator) OVERRIDE; |
| 522 | |
| 523 | const ArmInstructionSetFeatures& GetInstructionSetFeatures() const { return isa_features_; } |
| 524 | |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 525 | bool NeedsTwoRegisters(DataType::Type type) const OVERRIDE { |
| 526 | return type == DataType::Type::kFloat64 || type == DataType::Type::kInt64; |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 527 | } |
| 528 | |
| 529 | void ComputeSpillMask() OVERRIDE; |
| 530 | |
| 531 | vixl::aarch32::Label* GetFrameEntryLabel() { return &frame_entry_label_; } |
| 532 | |
| 533 | // Check if the desired_string_load_kind is supported. If it is, return it, |
| 534 | // otherwise return a fall-back kind that should be used instead. |
| 535 | HLoadString::LoadKind GetSupportedLoadStringKind( |
| 536 | HLoadString::LoadKind desired_string_load_kind) OVERRIDE; |
| 537 | |
| 538 | // Check if the desired_class_load_kind is supported. If it is, return it, |
| 539 | // otherwise return a fall-back kind that should be used instead. |
| 540 | HLoadClass::LoadKind GetSupportedLoadClassKind( |
| 541 | HLoadClass::LoadKind desired_class_load_kind) OVERRIDE; |
| 542 | |
| 543 | // Check if the desired_dispatch_info is supported. If it is, return it, |
| 544 | // otherwise return a fall-back info that should be used instead. |
| 545 | HInvokeStaticOrDirect::DispatchInfo GetSupportedInvokeStaticOrDirectDispatch( |
| 546 | const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info, |
| 547 | HInvokeStaticOrDirect* invoke) OVERRIDE; |
| 548 | |
Vladimir Marko | e7197bf | 2017-06-02 17:00:23 +0100 | [diff] [blame] | 549 | void GenerateStaticOrDirectCall( |
| 550 | HInvokeStaticOrDirect* invoke, Location temp, SlowPathCode* slow_path = nullptr) OVERRIDE; |
| 551 | void GenerateVirtualCall( |
| 552 | HInvokeVirtual* invoke, Location temp, SlowPathCode* slow_path = nullptr) OVERRIDE; |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 553 | |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 554 | void MoveFromReturnRegister(Location trg, DataType::Type type) OVERRIDE; |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 555 | |
| 556 | // The PcRelativePatchInfo is used for PC-relative addressing of dex cache arrays |
| 557 | // and boot image strings/types. The only difference is the interpretation of the |
| 558 | // offset_or_index. The PC-relative address is loaded with three instructions, |
| 559 | // MOVW+MOVT to load the offset to base_reg and then ADD base_reg, PC. The offset |
| 560 | // is calculated from the ADD's effective PC, i.e. PC+4 on Thumb2. Though we |
| 561 | // currently emit these 3 instructions together, instruction scheduling could |
| 562 | // split this sequence apart, so we keep separate labels for each of them. |
| 563 | struct PcRelativePatchInfo { |
| 564 | PcRelativePatchInfo(const DexFile& dex_file, uint32_t off_or_idx) |
| 565 | : target_dex_file(dex_file), offset_or_index(off_or_idx) { } |
| 566 | PcRelativePatchInfo(PcRelativePatchInfo&& other) = default; |
| 567 | |
| 568 | const DexFile& target_dex_file; |
| 569 | // Either the dex cache array element offset or the string/type index. |
| 570 | uint32_t offset_or_index; |
| 571 | vixl::aarch32::Label movw_label; |
| 572 | vixl::aarch32::Label movt_label; |
| 573 | vixl::aarch32::Label add_pc_label; |
| 574 | }; |
| 575 | |
Vladimir Marko | 6597946 | 2017-05-19 17:25:12 +0100 | [diff] [blame] | 576 | PcRelativePatchInfo* NewPcRelativeMethodPatch(MethodReference target_method); |
Vladimir Marko | 0eb882b | 2017-05-15 13:39:18 +0100 | [diff] [blame] | 577 | PcRelativePatchInfo* NewMethodBssEntryPatch(MethodReference target_method); |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 578 | PcRelativePatchInfo* NewPcRelativeTypePatch(const DexFile& dex_file, dex::TypeIndex type_index); |
Vladimir Marko | 1998cd0 | 2017-01-13 13:02:58 +0000 | [diff] [blame] | 579 | PcRelativePatchInfo* NewTypeBssEntryPatch(const DexFile& dex_file, dex::TypeIndex type_index); |
Vladimir Marko | 6597946 | 2017-05-19 17:25:12 +0100 | [diff] [blame] | 580 | PcRelativePatchInfo* NewPcRelativeStringPatch(const DexFile& dex_file, |
| 581 | dex::StringIndex string_index); |
Vladimir Marko | 6cfbdbc | 2017-07-25 13:26:39 +0100 | [diff] [blame] | 582 | PcRelativePatchInfo* NewStringBssEntryPatch(const DexFile& dex_file, |
| 583 | dex::StringIndex string_index); |
Vladimir Marko | eee1c0e | 2017-04-21 17:58:41 +0100 | [diff] [blame] | 584 | |
| 585 | // Add a new baker read barrier patch and return the label to be bound |
| 586 | // before the BNE instruction. |
| 587 | vixl::aarch32::Label* NewBakerReadBarrierPatch(uint32_t custom_data); |
| 588 | |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 589 | VIXLUInt32Literal* DeduplicateBootImageAddressLiteral(uint32_t address); |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 590 | VIXLUInt32Literal* DeduplicateJitStringLiteral(const DexFile& dex_file, |
Nicolas Geoffray | f0acfe7 | 2017-01-09 20:54:52 +0000 | [diff] [blame] | 591 | dex::StringIndex string_index, |
| 592 | Handle<mirror::String> handle); |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 593 | VIXLUInt32Literal* DeduplicateJitClassLiteral(const DexFile& dex_file, |
| 594 | dex::TypeIndex type_index, |
Nicolas Geoffray | 5247c08 | 2017-01-13 14:17:29 +0000 | [diff] [blame] | 595 | Handle<mirror::Class> handle); |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 596 | |
Vladimir Marko | d8dbc8d | 2017-09-20 13:37:47 +0100 | [diff] [blame] | 597 | void EmitLinkerPatches(ArenaVector<linker::LinkerPatch>* linker_patches) OVERRIDE; |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 598 | |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 599 | void EmitJitRootPatches(uint8_t* code, const uint8_t* roots_data) OVERRIDE; |
| 600 | |
Vladimir Marko | eee1c0e | 2017-04-21 17:58:41 +0100 | [diff] [blame] | 601 | // Maybe add the reserved entrypoint register as a temporary for field load. This temp |
| 602 | // is added only for AOT compilation if link-time generated thunks for fields are enabled. |
| 603 | void MaybeAddBakerCcEntrypointTempForFields(LocationSummary* locations); |
| 604 | |
Anton Kirilov | e28d9ae | 2016-10-25 18:17:23 +0100 | [diff] [blame] | 605 | // Fast path implementation of ReadBarrier::Barrier for a heap |
| 606 | // reference field load when Baker's read barriers are used. |
| 607 | void GenerateFieldLoadWithBakerReadBarrier(HInstruction* instruction, |
| 608 | Location ref, |
| 609 | vixl::aarch32::Register obj, |
| 610 | uint32_t offset, |
| 611 | Location temp, |
| 612 | bool needs_null_check); |
Anton Kirilov | edb2ac3 | 2016-11-30 15:14:10 +0000 | [diff] [blame] | 613 | // Fast path implementation of ReadBarrier::Barrier for a heap |
| 614 | // reference array load when Baker's read barriers are used. |
| 615 | void GenerateArrayLoadWithBakerReadBarrier(HInstruction* instruction, |
| 616 | Location ref, |
| 617 | vixl::aarch32::Register obj, |
| 618 | uint32_t data_offset, |
| 619 | Location index, |
| 620 | Location temp, |
| 621 | bool needs_null_check); |
Anton Kirilov | e28d9ae | 2016-10-25 18:17:23 +0100 | [diff] [blame] | 622 | // Factored implementation, used by GenerateFieldLoadWithBakerReadBarrier, |
| 623 | // GenerateArrayLoadWithBakerReadBarrier and some intrinsics. |
| 624 | // |
| 625 | // Load the object reference located at the address |
| 626 | // `obj + offset + (index << scale_factor)`, held by object `obj`, into |
| 627 | // `ref`, and mark it if needed. |
Anton Kirilov | e28d9ae | 2016-10-25 18:17:23 +0100 | [diff] [blame] | 628 | void GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction, |
| 629 | Location ref, |
| 630 | vixl::aarch32::Register obj, |
| 631 | uint32_t offset, |
| 632 | Location index, |
| 633 | ScaleFactor scale_factor, |
| 634 | Location temp, |
Roland Levillain | ff48700 | 2017-03-07 16:50:01 +0000 | [diff] [blame] | 635 | bool needs_null_check); |
| 636 | |
| 637 | // Generate code checking whether the the reference field at the |
| 638 | // address `obj + field_offset`, held by object `obj`, needs to be |
| 639 | // marked, and if so, marking it and updating the field within `obj` |
| 640 | // with the marked value. |
| 641 | // |
| 642 | // This routine is used for the implementation of the |
| 643 | // UnsafeCASObject intrinsic with Baker read barriers. |
| 644 | // |
| 645 | // This method has a structure similar to |
| 646 | // GenerateReferenceLoadWithBakerReadBarrier, but note that argument |
| 647 | // `ref` is only as a temporary here, and thus its value should not |
| 648 | // be used afterwards. |
| 649 | void UpdateReferenceFieldWithBakerReadBarrier(HInstruction* instruction, |
| 650 | Location ref, |
| 651 | vixl::aarch32::Register obj, |
| 652 | Location field_offset, |
| 653 | Location temp, |
| 654 | bool needs_null_check, |
| 655 | vixl::aarch32::Register temp2); |
Anton Kirilov | e28d9ae | 2016-10-25 18:17:23 +0100 | [diff] [blame] | 656 | |
Roland Levillain | ba650a4 | 2017-03-06 13:52:32 +0000 | [diff] [blame] | 657 | // Generate a heap reference load (with no read barrier). |
| 658 | void GenerateRawReferenceLoad(HInstruction* instruction, |
| 659 | Location ref, |
| 660 | vixl::aarch32::Register obj, |
| 661 | uint32_t offset, |
| 662 | Location index, |
| 663 | ScaleFactor scale_factor, |
| 664 | bool needs_null_check); |
| 665 | |
Roland Levillain | 5daa495 | 2017-07-03 17:23:56 +0100 | [diff] [blame] | 666 | // Emit code checking the status of the Marking Register, and |
| 667 | // aborting the program if MR does not match the value stored in the |
| 668 | // art::Thread object. Code is only emitted in debug mode and if |
| 669 | // CompilerOptions::EmitRunTimeChecksInDebugMode returns true. |
| 670 | // |
| 671 | // Argument `code` is used to identify the different occurrences of |
| 672 | // MaybeGenerateMarkingRegisterCheck in the code generator, and is |
| 673 | // used together with kMarkingRegisterCheckBreakCodeBaseCode to |
| 674 | // create the value passed to the BKPT instruction. Note that unlike |
| 675 | // in the ARM64 code generator, where `__LINE__` is passed as `code` |
| 676 | // argument to |
| 677 | // CodeGeneratorARM64::MaybeGenerateMarkingRegisterCheck, we cannot |
| 678 | // realistically do that here, as Encoding T1 for the BKPT |
| 679 | // instruction only accepts 8-bit immediate values. |
| 680 | // |
| 681 | // If `temp_loc` is a valid location, it is expected to be a |
| 682 | // register and will be used as a temporary to generate code; |
| 683 | // otherwise, a temporary will be fetched from the core register |
| 684 | // scratch pool. |
| 685 | virtual void MaybeGenerateMarkingRegisterCheck(int code, |
| 686 | Location temp_loc = Location::NoLocation()); |
| 687 | |
Anton Kirilov | e28d9ae | 2016-10-25 18:17:23 +0100 | [diff] [blame] | 688 | // Generate a read barrier for a heap reference within `instruction` |
| 689 | // using a slow path. |
| 690 | // |
| 691 | // A read barrier for an object reference read from the heap is |
| 692 | // implemented as a call to the artReadBarrierSlow runtime entry |
| 693 | // point, which is passed the values in locations `ref`, `obj`, and |
| 694 | // `offset`: |
| 695 | // |
| 696 | // mirror::Object* artReadBarrierSlow(mirror::Object* ref, |
| 697 | // mirror::Object* obj, |
| 698 | // uint32_t offset); |
| 699 | // |
| 700 | // The `out` location contains the value returned by |
| 701 | // artReadBarrierSlow. |
| 702 | // |
| 703 | // When `index` is provided (i.e. for array accesses), the offset |
| 704 | // value passed to artReadBarrierSlow is adjusted to take `index` |
| 705 | // into account. |
| 706 | void GenerateReadBarrierSlow(HInstruction* instruction, |
| 707 | Location out, |
| 708 | Location ref, |
| 709 | Location obj, |
| 710 | uint32_t offset, |
| 711 | Location index = Location::NoLocation()); |
| 712 | |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 713 | // If read barriers are enabled, generate a read barrier for a heap |
| 714 | // reference using a slow path. If heap poisoning is enabled, also |
| 715 | // unpoison the reference in `out`. |
| 716 | void MaybeGenerateReadBarrierSlow(HInstruction* instruction, |
| 717 | Location out, |
| 718 | Location ref, |
| 719 | Location obj, |
| 720 | uint32_t offset, |
| 721 | Location index = Location::NoLocation()); |
| 722 | |
Anton Kirilov | edb2ac3 | 2016-11-30 15:14:10 +0000 | [diff] [blame] | 723 | // Generate a read barrier for a GC root within `instruction` using |
| 724 | // a slow path. |
| 725 | // |
| 726 | // A read barrier for an object reference GC root is implemented as |
| 727 | // a call to the artReadBarrierForRootSlow runtime entry point, |
| 728 | // which is passed the value in location `root`: |
| 729 | // |
| 730 | // mirror::Object* artReadBarrierForRootSlow(GcRoot<mirror::Object>* root); |
| 731 | // |
| 732 | // The `out` location contains the value returned by |
| 733 | // artReadBarrierForRootSlow. |
| 734 | void GenerateReadBarrierForRootSlow(HInstruction* instruction, Location out, Location root); |
| 735 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 736 | void GenerateNop() OVERRIDE; |
| 737 | |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 738 | void GenerateImplicitNullCheck(HNullCheck* instruction) OVERRIDE; |
| 739 | void GenerateExplicitNullCheck(HNullCheck* instruction) OVERRIDE; |
| 740 | |
| 741 | JumpTableARMVIXL* CreateJumpTable(HPackedSwitch* switch_instr) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 742 | jump_tables_.emplace_back(new (GetGraph()->GetAllocator()) JumpTableARMVIXL(switch_instr)); |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 743 | return jump_tables_.back().get(); |
| 744 | } |
| 745 | void EmitJumpTables(); |
| 746 | |
| 747 | void EmitMovwMovtPlaceholder(CodeGeneratorARMVIXL::PcRelativePatchInfo* labels, |
| 748 | vixl::aarch32::Register out); |
| 749 | |
Anton Kirilov | 5601d4e | 2017-05-11 19:33:50 +0100 | [diff] [blame] | 750 | // `temp` is an extra temporary register that is used for some conditions; |
| 751 | // callers may not specify it, in which case the method will use a scratch |
| 752 | // register instead. |
| 753 | void GenerateConditionWithZero(IfCondition condition, |
| 754 | vixl::aarch32::Register out, |
| 755 | vixl::aarch32::Register in, |
| 756 | vixl::aarch32::Register temp = vixl32::Register()); |
| 757 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 758 | private: |
Scott Wakeling | a7812ae | 2016-10-17 10:03:36 +0100 | [diff] [blame] | 759 | vixl::aarch32::Register GetInvokeStaticOrDirectExtraParameter(HInvokeStaticOrDirect* invoke, |
| 760 | vixl::aarch32::Register temp); |
| 761 | |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 762 | using Uint32ToLiteralMap = ArenaSafeMap<uint32_t, VIXLUInt32Literal*>; |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 763 | using StringToLiteralMap = ArenaSafeMap<StringReference, |
| 764 | VIXLUInt32Literal*, |
| 765 | StringReferenceValueComparator>; |
| 766 | using TypeToLiteralMap = ArenaSafeMap<TypeReference, |
| 767 | VIXLUInt32Literal*, |
| 768 | TypeReferenceValueComparator>; |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 769 | |
Vladimir Marko | eee1c0e | 2017-04-21 17:58:41 +0100 | [diff] [blame] | 770 | struct BakerReadBarrierPatchInfo { |
| 771 | explicit BakerReadBarrierPatchInfo(uint32_t data) : label(), custom_data(data) { } |
| 772 | |
| 773 | vixl::aarch32::Label label; |
| 774 | uint32_t custom_data; |
| 775 | }; |
| 776 | |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 777 | VIXLUInt32Literal* DeduplicateUint32Literal(uint32_t value, Uint32ToLiteralMap* map); |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 778 | PcRelativePatchInfo* NewPcRelativePatch(const DexFile& dex_file, |
| 779 | uint32_t offset_or_index, |
| 780 | ArenaDeque<PcRelativePatchInfo>* patches); |
Vladimir Marko | d8dbc8d | 2017-09-20 13:37:47 +0100 | [diff] [blame] | 781 | template <linker::LinkerPatch (*Factory)(size_t, const DexFile*, uint32_t, uint32_t)> |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 782 | static void EmitPcRelativeLinkerPatches(const ArenaDeque<PcRelativePatchInfo>& infos, |
Vladimir Marko | d8dbc8d | 2017-09-20 13:37:47 +0100 | [diff] [blame] | 783 | ArenaVector<linker::LinkerPatch>* linker_patches); |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 784 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 785 | // Labels for each block that will be compiled. |
| 786 | // We use a deque so that the `vixl::aarch32::Label` objects do not move in memory. |
| 787 | ArenaDeque<vixl::aarch32::Label> block_labels_; // Indexed by block id. |
| 788 | vixl::aarch32::Label frame_entry_label_; |
| 789 | |
Artem Serov | 551b28f | 2016-10-18 19:11:30 +0100 | [diff] [blame] | 790 | ArenaVector<std::unique_ptr<JumpTableARMVIXL>> jump_tables_; |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 791 | LocationsBuilderARMVIXL location_builder_; |
| 792 | InstructionCodeGeneratorARMVIXL instruction_visitor_; |
| 793 | ParallelMoveResolverARMVIXL move_resolver_; |
| 794 | |
| 795 | ArmVIXLAssembler assembler_; |
| 796 | const ArmInstructionSetFeatures& isa_features_; |
| 797 | |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 798 | // Deduplication map for 32-bit literals, used for non-patchable boot image addresses. |
| 799 | Uint32ToLiteralMap uint32_literals_; |
Vladimir Marko | 6597946 | 2017-05-19 17:25:12 +0100 | [diff] [blame] | 800 | // PC-relative method patch info for kBootImageLinkTimePcRelative. |
| 801 | ArenaDeque<PcRelativePatchInfo> pc_relative_method_patches_; |
Vladimir Marko | 0eb882b | 2017-05-15 13:39:18 +0100 | [diff] [blame] | 802 | // PC-relative method patch info for kBssEntry. |
| 803 | ArenaDeque<PcRelativePatchInfo> method_bss_entry_patches_; |
Vladimir Marko | 1998cd0 | 2017-01-13 13:02:58 +0000 | [diff] [blame] | 804 | // PC-relative type patch info for kBootImageLinkTimePcRelative. |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 805 | ArenaDeque<PcRelativePatchInfo> pc_relative_type_patches_; |
Vladimir Marko | 1998cd0 | 2017-01-13 13:02:58 +0000 | [diff] [blame] | 806 | // PC-relative type patch info for kBssEntry. |
| 807 | ArenaDeque<PcRelativePatchInfo> type_bss_entry_patches_; |
Vladimir Marko | 6cfbdbc | 2017-07-25 13:26:39 +0100 | [diff] [blame] | 808 | // PC-relative String patch info; type depends on configuration (intern table or boot image PIC). |
Vladimir Marko | 6597946 | 2017-05-19 17:25:12 +0100 | [diff] [blame] | 809 | ArenaDeque<PcRelativePatchInfo> pc_relative_string_patches_; |
Vladimir Marko | 6cfbdbc | 2017-07-25 13:26:39 +0100 | [diff] [blame] | 810 | // PC-relative String patch info for kBssEntry. |
| 811 | ArenaDeque<PcRelativePatchInfo> string_bss_entry_patches_; |
Vladimir Marko | eee1c0e | 2017-04-21 17:58:41 +0100 | [diff] [blame] | 812 | // Baker read barrier patch info. |
| 813 | ArenaDeque<BakerReadBarrierPatchInfo> baker_read_barrier_patches_; |
Artem Serov | c5fcb44 | 2016-12-02 19:19:58 +0000 | [diff] [blame] | 814 | |
| 815 | // Patches for string literals in JIT compiled code. |
| 816 | StringToLiteralMap jit_string_patches_; |
| 817 | // Patches for class literals in JIT compiled code. |
| 818 | TypeToLiteralMap jit_class_patches_; |
Artem Serov | d4cc5b2 | 2016-11-04 11:19:09 +0000 | [diff] [blame] | 819 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 820 | DISALLOW_COPY_AND_ASSIGN(CodeGeneratorARMVIXL); |
| 821 | }; |
| 822 | |
Scott Wakeling | fe88546 | 2016-09-22 10:24:38 +0100 | [diff] [blame] | 823 | } // namespace arm |
| 824 | } // namespace art |
| 825 | |
| 826 | #endif // ART_COMPILER_OPTIMIZING_CODE_GENERATOR_ARM_VIXL_H_ |