Allow mixing of thread offsets between 32 and 64bit architectures.
Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.
Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
diff --git a/compiler/utils/arm/assembler_arm.cc b/compiler/utils/arm/assembler_arm.cc
index 872a557..59eb98e 100644
--- a/compiler/utils/arm/assembler_arm.cc
+++ b/compiler/utils/arm/assembler_arm.cc
@@ -1577,7 +1577,7 @@
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
}
-void ArmAssembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
+void ArmAssembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm,
ManagedRegister mscratch) {
ArmManagedRegister scratch = mscratch.AsArm();
CHECK(scratch.IsCoreRegister()) << scratch;
@@ -1609,18 +1609,18 @@
return EmitLoad(this, m_dst, SP, src.Int32Value(), size);
}
-void ArmAssembler::Load(ManagedRegister m_dst, ThreadOffset src, size_t size) {
+void ArmAssembler::LoadFromThread32(ManagedRegister m_dst, ThreadOffset<4> src, size_t size) {
return EmitLoad(this, m_dst, TR, src.Int32Value(), size);
}
-void ArmAssembler::LoadRawPtrFromThread(ManagedRegister m_dst, ThreadOffset offs) {
+void ArmAssembler::LoadRawPtrFromThread32(ManagedRegister m_dst, ThreadOffset<4> offs) {
ArmManagedRegister dst = m_dst.AsArm();
CHECK(dst.IsCoreRegister()) << dst;
LoadFromOffset(kLoadWord, dst.AsCoreRegister(), TR, offs.Int32Value());
}
-void ArmAssembler::CopyRawPtrFromThread(FrameOffset fr_offs,
- ThreadOffset thr_offs,
+void ArmAssembler::CopyRawPtrFromThread32(FrameOffset fr_offs,
+ ThreadOffset<4> thr_offs,
ManagedRegister mscratch) {
ArmManagedRegister scratch = mscratch.AsArm();
CHECK(scratch.IsCoreRegister()) << scratch;
@@ -1630,7 +1630,7 @@
SP, fr_offs.Int32Value());
}
-void ArmAssembler::CopyRawPtrToThread(ThreadOffset thr_offs,
+void ArmAssembler::CopyRawPtrToThread32(ThreadOffset<4> thr_offs,
FrameOffset fr_offs,
ManagedRegister mscratch) {
ArmManagedRegister scratch = mscratch.AsArm();
@@ -1641,7 +1641,7 @@
TR, thr_offs.Int32Value());
}
-void ArmAssembler::StoreStackOffsetToThread(ThreadOffset thr_offs,
+void ArmAssembler::StoreStackOffsetToThread32(ThreadOffset<4> thr_offs,
FrameOffset fr_offs,
ManagedRegister mscratch) {
ArmManagedRegister scratch = mscratch.AsArm();
@@ -1651,7 +1651,7 @@
TR, thr_offs.Int32Value());
}
-void ArmAssembler::StoreStackPointerToThread(ThreadOffset thr_offs) {
+void ArmAssembler::StoreStackPointerToThread32(ThreadOffset<4> thr_offs) {
StoreToOffset(kStoreWord, SP, TR, thr_offs.Int32Value());
}
@@ -1844,7 +1844,7 @@
// TODO: place reference map on call
}
-void ArmAssembler::Call(ThreadOffset /*offset*/, ManagedRegister /*scratch*/) {
+void ArmAssembler::CallFromThread32(ThreadOffset<4> /*offset*/, ManagedRegister /*scratch*/) {
UNIMPLEMENTED(FATAL);
}
@@ -1862,7 +1862,7 @@
ArmExceptionSlowPath* slow = new ArmExceptionSlowPath(scratch, stack_adjust);
buffer_.EnqueueSlowPath(slow);
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
- TR, Thread::ExceptionOffset().Int32Value());
+ TR, Thread::ExceptionOffset<4>().Int32Value());
cmp(scratch.AsCoreRegister(), ShifterOperand(0));
b(slow->Entry(), NE);
}
@@ -1878,7 +1878,7 @@
// Don't care about preserving R0 as this call won't return
__ mov(R0, ShifterOperand(scratch_.AsCoreRegister()));
// Set up call to Thread::Current()->pDeliverException
- __ LoadFromOffset(kLoadWord, R12, TR, QUICK_ENTRYPOINT_OFFSET(pDeliverException).Int32Value());
+ __ LoadFromOffset(kLoadWord, R12, TR, QUICK_ENTRYPOINT_OFFSET(4, pDeliverException).Int32Value());
__ blx(R12);
// Call never returns
__ bkpt(0);
diff --git a/compiler/utils/arm/assembler_arm.h b/compiler/utils/arm/assembler_arm.h
index bb9207c..f5be04a 100644
--- a/compiler/utils/arm/assembler_arm.h
+++ b/compiler/utils/arm/assembler_arm.h
@@ -35,6 +35,7 @@
// Data-processing operands - Uninitialized
ShifterOperand() {
type_ = -1;
+ encoding_ = 0;
}
// Data-processing operands - Immediate
@@ -210,7 +211,7 @@
};
-class ArmAssembler : public Assembler {
+class ArmAssembler FINAL : public Assembler {
public:
ArmAssembler() {}
virtual ~ArmAssembler() {}
@@ -438,127 +439,116 @@
//
// Emit code that will create an activation on the stack
- virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
- const std::vector<ManagedRegister>& callee_save_regs,
- const ManagedRegisterEntrySpills& entry_spills);
+ void BuildFrame(size_t frame_size, ManagedRegister method_reg,
+ const std::vector<ManagedRegister>& callee_save_regs,
+ const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
// Emit code that will remove an activation from the stack
- virtual void RemoveFrame(size_t frame_size,
- const std::vector<ManagedRegister>& callee_save_regs);
+ void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
+ OVERRIDE;
- virtual void IncreaseFrameSize(size_t adjust);
- virtual void DecreaseFrameSize(size_t adjust);
+ void IncreaseFrameSize(size_t adjust) OVERRIDE;
+ void DecreaseFrameSize(size_t adjust) OVERRIDE;
// Store routines
- virtual void Store(FrameOffset offs, ManagedRegister src, size_t size);
- virtual void StoreRef(FrameOffset dest, ManagedRegister src);
- virtual void StoreRawPtr(FrameOffset dest, ManagedRegister src);
+ void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE;
+ void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE;
+ void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE;
- virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
- ManagedRegister scratch);
+ void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
- virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
- ManagedRegister scratch);
+ void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister scratch)
+ OVERRIDE;
- virtual void StoreStackOffsetToThread(ThreadOffset thr_offs,
- FrameOffset fr_offs,
- ManagedRegister scratch);
+ void StoreStackOffsetToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
+ ManagedRegister scratch) OVERRIDE;
- virtual void StoreStackPointerToThread(ThreadOffset thr_offs);
+ void StoreStackPointerToThread32(ThreadOffset<4> thr_offs) OVERRIDE;
- virtual void StoreSpanning(FrameOffset dest, ManagedRegister src,
- FrameOffset in_off, ManagedRegister scratch);
+ void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
+ ManagedRegister scratch) OVERRIDE;
// Load routines
- virtual void Load(ManagedRegister dest, FrameOffset src, size_t size);
+ void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE;
- virtual void Load(ManagedRegister dest, ThreadOffset src, size_t size);
+ void LoadFromThread32(ManagedRegister dest, ThreadOffset<4> src, size_t size) OVERRIDE;
- virtual void LoadRef(ManagedRegister dest, FrameOffset src);
+ void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE;
- virtual void LoadRef(ManagedRegister dest, ManagedRegister base,
- MemberOffset offs);
+ void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE;
- virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
- Offset offs);
+ void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
- virtual void LoadRawPtrFromThread(ManagedRegister dest,
- ThreadOffset offs);
+ void LoadRawPtrFromThread32(ManagedRegister dest, ThreadOffset<4> offs) OVERRIDE;
// Copying routines
- virtual void Move(ManagedRegister dest, ManagedRegister src, size_t size);
+ void Move(ManagedRegister dest, ManagedRegister src, size_t size) OVERRIDE;
- virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
- ManagedRegister scratch);
+ void CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs,
+ ManagedRegister scratch) OVERRIDE;
- virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
- ManagedRegister scratch);
+ void CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs, ManagedRegister scratch)
+ OVERRIDE;
- virtual void CopyRef(FrameOffset dest, FrameOffset src,
- ManagedRegister scratch);
+ void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE;
- virtual void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
- ManagedRegister scratch, size_t size);
+ void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(ManagedRegister dest, Offset dest_offset,
- ManagedRegister src, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
+ ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
+ ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void MemoryBarrier(ManagedRegister scratch);
+ void MemoryBarrier(ManagedRegister scratch) OVERRIDE;
// Sign extension
- virtual void SignExtend(ManagedRegister mreg, size_t size);
+ void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Zero extension
- virtual void ZeroExtend(ManagedRegister mreg, size_t size);
+ void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Exploit fast access in managed code to Thread::Current()
- virtual void GetCurrentThread(ManagedRegister tr);
- virtual void GetCurrentThread(FrameOffset dest_offset,
- ManagedRegister scratch);
+ void GetCurrentThread(ManagedRegister tr) OVERRIDE;
+ void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE;
// Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed. in_reg holds a possibly stale reference
// that can be used to avoid loading the SIRT entry to see if the value is
// NULL.
- virtual void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
- ManagedRegister in_reg, bool null_allowed);
+ void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset, ManagedRegister in_reg,
+ bool null_allowed) OVERRIDE;
// Set up out_off to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed.
- virtual void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
- ManagedRegister scratch, bool null_allowed);
+ void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset, ManagedRegister scratch,
+ bool null_allowed) OVERRIDE;
// src holds a SIRT entry (Object**) load this into dst
- virtual void LoadReferenceFromSirt(ManagedRegister dst,
- ManagedRegister src);
+ void LoadReferenceFromSirt(ManagedRegister dst, ManagedRegister src) OVERRIDE;
// Heap::VerifyObject on src. In some cases (such as a reference to this) we
// know that src may not be null.
- virtual void VerifyObject(ManagedRegister src, bool could_be_null);
- virtual void VerifyObject(FrameOffset src, bool could_be_null);
+ void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
+ void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
// Call to address held at [base+offset]
- virtual void Call(ManagedRegister base, Offset offset,
- ManagedRegister scratch);
- virtual void Call(FrameOffset base, Offset offset,
- ManagedRegister scratch);
- virtual void Call(ThreadOffset offset, ManagedRegister scratch);
+ void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
+ void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
+ void CallFromThread32(ThreadOffset<4> offset, ManagedRegister scratch) OVERRIDE;
// Generate code to check if Thread::Current()->exception_ is non-null
// and branch to a ExceptionSlowPath if it is.
- virtual void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust);
+ void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE;
private:
void EmitType01(Condition cond,
@@ -642,12 +632,12 @@
};
// Slowpath entered when Thread::Current()->_exception is non-null
-class ArmExceptionSlowPath : public SlowPath {
+class ArmExceptionSlowPath FINAL : public SlowPath {
public:
explicit ArmExceptionSlowPath(ArmManagedRegister scratch, size_t stack_adjust)
: scratch_(scratch), stack_adjust_(stack_adjust) {
}
- virtual void Emit(Assembler *sp_asm);
+ void Emit(Assembler *sp_asm) OVERRIDE;
private:
const ArmManagedRegister scratch_;
const size_t stack_adjust_;
diff --git a/compiler/utils/arm/constants_arm.h b/compiler/utils/arm/constants_arm.h
index cc795b1..058f945 100644
--- a/compiler/utils/arm/constants_arm.h
+++ b/compiler/utils/arm/constants_arm.h
@@ -242,22 +242,22 @@
}
// Get the raw instruction bits.
- inline int32_t InstructionBits() const {
+ int32_t InstructionBits() const {
return *reinterpret_cast<const int32_t*>(this);
}
// Set the raw instruction bits to value.
- inline void SetInstructionBits(int32_t value) {
+ void SetInstructionBits(int32_t value) {
*reinterpret_cast<int32_t*>(this) = value;
}
// Read one particular bit out of the instruction bits.
- inline int Bit(int nr) const {
+ int Bit(int nr) const {
return (InstructionBits() >> nr) & 1;
}
// Read a bit field out of the instruction bits.
- inline int Bits(int shift, int count) const {
+ int Bits(int shift, int count) const {
return (InstructionBits() >> shift) & ((1 << count) - 1);
}
@@ -265,80 +265,80 @@
// Accessors for the different named fields used in the ARM encoding.
// The naming of these accessor corresponds to figure A3-1.
// Generally applicable fields
- inline Condition ConditionField() const {
+ Condition ConditionField() const {
return static_cast<Condition>(Bits(kConditionShift, kConditionBits));
}
- inline int TypeField() const { return Bits(kTypeShift, kTypeBits); }
+ int TypeField() const { return Bits(kTypeShift, kTypeBits); }
- inline Register RnField() const { return static_cast<Register>(
+ Register RnField() const { return static_cast<Register>(
Bits(kRnShift, kRnBits)); }
- inline Register RdField() const { return static_cast<Register>(
+ Register RdField() const { return static_cast<Register>(
Bits(kRdShift, kRdBits)); }
// Fields used in Data processing instructions
- inline Opcode OpcodeField() const {
+ Opcode OpcodeField() const {
return static_cast<Opcode>(Bits(kOpcodeShift, kOpcodeBits));
}
- inline int SField() const { return Bits(kSShift, kSBits); }
+ int SField() const { return Bits(kSShift, kSBits); }
// with register
- inline Register RmField() const {
+ Register RmField() const {
return static_cast<Register>(Bits(kRmShift, kRmBits));
}
- inline Shift ShiftField() const { return static_cast<Shift>(
+ Shift ShiftField() const { return static_cast<Shift>(
Bits(kShiftShift, kShiftBits)); }
- inline int RegShiftField() const { return Bit(4); }
- inline Register RsField() const {
+ int RegShiftField() const { return Bit(4); }
+ Register RsField() const {
return static_cast<Register>(Bits(kRsShift, kRsBits));
}
- inline int ShiftAmountField() const { return Bits(kShiftImmShift,
+ int ShiftAmountField() const { return Bits(kShiftImmShift,
kShiftImmBits); }
// with immediate
- inline int RotateField() const { return Bits(kRotateShift, kRotateBits); }
- inline int Immed8Field() const { return Bits(kImmed8Shift, kImmed8Bits); }
+ int RotateField() const { return Bits(kRotateShift, kRotateBits); }
+ int Immed8Field() const { return Bits(kImmed8Shift, kImmed8Bits); }
// Fields used in Load/Store instructions
- inline int PUField() const { return Bits(23, 2); }
- inline int BField() const { return Bit(22); }
- inline int WField() const { return Bit(21); }
- inline int LField() const { return Bit(20); }
+ int PUField() const { return Bits(23, 2); }
+ int BField() const { return Bit(22); }
+ int WField() const { return Bit(21); }
+ int LField() const { return Bit(20); }
// with register uses same fields as Data processing instructions above
// with immediate
- inline int Offset12Field() const { return Bits(kOffset12Shift,
+ int Offset12Field() const { return Bits(kOffset12Shift,
kOffset12Bits); }
// multiple
- inline int RlistField() const { return Bits(0, 16); }
+ int RlistField() const { return Bits(0, 16); }
// extra loads and stores
- inline int SignField() const { return Bit(6); }
- inline int HField() const { return Bit(5); }
- inline int ImmedHField() const { return Bits(8, 4); }
- inline int ImmedLField() const { return Bits(0, 4); }
+ int SignField() const { return Bit(6); }
+ int HField() const { return Bit(5); }
+ int ImmedHField() const { return Bits(8, 4); }
+ int ImmedLField() const { return Bits(0, 4); }
// Fields used in Branch instructions
- inline int LinkField() const { return Bits(kLinkShift, kLinkBits); }
- inline int SImmed24Field() const { return ((InstructionBits() << 8) >> 8); }
+ int LinkField() const { return Bits(kLinkShift, kLinkBits); }
+ int SImmed24Field() const { return ((InstructionBits() << 8) >> 8); }
// Fields used in Supervisor Call instructions
- inline uint32_t SvcField() const { return Bits(0, 24); }
+ uint32_t SvcField() const { return Bits(0, 24); }
// Field used in Breakpoint instruction
- inline uint16_t BkptField() const {
+ uint16_t BkptField() const {
return ((Bits(8, 12) << 4) | Bits(0, 4));
}
// Field used in 16-bit immediate move instructions
- inline uint16_t MovwField() const {
+ uint16_t MovwField() const {
return ((Bits(16, 4) << 12) | Bits(0, 12));
}
// Field used in VFP float immediate move instruction
- inline float ImmFloatField() const {
+ float ImmFloatField() const {
uint32_t imm32 = (Bit(19) << 31) | (((1 << 5) - Bit(18)) << 25) |
(Bits(16, 2) << 23) | (Bits(0, 4) << 19);
return bit_cast<float, uint32_t>(imm32);
}
// Field used in VFP double immediate move instruction
- inline double ImmDoubleField() const {
+ double ImmDoubleField() const {
uint64_t imm64 = (Bit(19)*(1LL << 63)) | (((1LL << 8) - Bit(18)) << 54) |
(Bits(16, 2)*(1LL << 52)) | (Bits(0, 4)*(1LL << 48));
return bit_cast<double, uint64_t>(imm64);
@@ -347,7 +347,7 @@
// Test for data processing instructions of type 0 or 1.
// See "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition",
// section A5.1 "ARM instruction set encoding".
- inline bool IsDataProcessing() const {
+ bool IsDataProcessing() const {
CHECK_NE(ConditionField(), kSpecialCondition);
CHECK_EQ(Bits(26, 2), 0); // Type 0 or 1.
return ((Bits(20, 5) & 0x19) != 0x10) &&
@@ -359,47 +359,47 @@
// Tests for special encodings of type 0 instructions (extra loads and stores,
// as well as multiplications, synchronization primitives, and miscellaneous).
// Can only be called for a type 0 or 1 instruction.
- inline bool IsMiscellaneous() const {
+ bool IsMiscellaneous() const {
CHECK_EQ(Bits(26, 2), 0); // Type 0 or 1.
return ((Bit(25) == 0) && ((Bits(20, 5) & 0x19) == 0x10) && (Bit(7) == 0));
}
- inline bool IsMultiplyOrSyncPrimitive() const {
+ bool IsMultiplyOrSyncPrimitive() const {
CHECK_EQ(Bits(26, 2), 0); // Type 0 or 1.
return ((Bit(25) == 0) && (Bits(4, 4) == 9));
}
// Test for Supervisor Call instruction.
- inline bool IsSvc() const {
+ bool IsSvc() const {
return ((InstructionBits() & 0xff000000) == 0xef000000);
}
// Test for Breakpoint instruction.
- inline bool IsBkpt() const {
+ bool IsBkpt() const {
return ((InstructionBits() & 0xfff000f0) == 0xe1200070);
}
// VFP register fields.
- inline SRegister SnField() const {
+ SRegister SnField() const {
return static_cast<SRegister>((Bits(kRnShift, kRnBits) << 1) + Bit(7));
}
- inline SRegister SdField() const {
+ SRegister SdField() const {
return static_cast<SRegister>((Bits(kRdShift, kRdBits) << 1) + Bit(22));
}
- inline SRegister SmField() const {
+ SRegister SmField() const {
return static_cast<SRegister>((Bits(kRmShift, kRmBits) << 1) + Bit(5));
}
- inline DRegister DnField() const {
+ DRegister DnField() const {
return static_cast<DRegister>(Bits(kRnShift, kRnBits) + (Bit(7) << 4));
}
- inline DRegister DdField() const {
+ DRegister DdField() const {
return static_cast<DRegister>(Bits(kRdShift, kRdBits) + (Bit(22) << 4));
}
- inline DRegister DmField() const {
+ DRegister DmField() const {
return static_cast<DRegister>(Bits(kRmShift, kRmBits) + (Bit(5) << 4));
}
// Test for VFP data processing or single transfer instructions of type 7.
- inline bool IsVFPDataProcessingOrSingleTransfer() const {
+ bool IsVFPDataProcessingOrSingleTransfer() const {
CHECK_NE(ConditionField(), kSpecialCondition);
CHECK_EQ(TypeField(), 7);
return ((Bit(24) == 0) && (Bits(9, 3) == 5));
@@ -408,7 +408,7 @@
}
// Test for VFP 64-bit transfer instructions of type 6.
- inline bool IsVFPDoubleTransfer() const {
+ bool IsVFPDoubleTransfer() const {
CHECK_NE(ConditionField(), kSpecialCondition);
CHECK_EQ(TypeField(), 6);
return ((Bits(21, 4) == 2) && (Bits(9, 3) == 5) &&
@@ -416,20 +416,20 @@
}
// Test for VFP load and store instructions of type 6.
- inline bool IsVFPLoadStore() const {
+ bool IsVFPLoadStore() const {
CHECK_NE(ConditionField(), kSpecialCondition);
CHECK_EQ(TypeField(), 6);
return ((Bits(20, 5) & 0x12) == 0x10) && (Bits(9, 3) == 5);
}
// Special accessors that test for existence of a value.
- inline bool HasS() const { return SField() == 1; }
- inline bool HasB() const { return BField() == 1; }
- inline bool HasW() const { return WField() == 1; }
- inline bool HasL() const { return LField() == 1; }
- inline bool HasSign() const { return SignField() == 1; }
- inline bool HasH() const { return HField() == 1; }
- inline bool HasLink() const { return LinkField() == 1; }
+ bool HasS() const { return SField() == 1; }
+ bool HasB() const { return BField() == 1; }
+ bool HasW() const { return WField() == 1; }
+ bool HasL() const { return LField() == 1; }
+ bool HasSign() const { return SignField() == 1; }
+ bool HasH() const { return HField() == 1; }
+ bool HasLink() const { return LinkField() == 1; }
// Instructions are read out of a code stream. The only way to get a
// reference to an instruction is to convert a pointer. There is no way