Allow mixing of thread offsets between 32 and 64bit architectures.
Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.
Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
diff --git a/compiler/dex/quick/arm/call_arm.cc b/compiler/dex/quick/arm/call_arm.cc
index d6724f1..2e37877 100644
--- a/compiler/dex/quick/arm/call_arm.cc
+++ b/compiler/dex/quick/arm/call_arm.cc
@@ -164,7 +164,7 @@
// Making a call - use explicit registers
FlushAllRegs(); /* Everything to home location */
LoadValueDirectFixed(rl_src, rs_r0);
- LoadWordDisp(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData).Int32Value(),
+ LoadWordDisp(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(4, pHandleFillArrayData).Int32Value(),
rs_rARM_LR);
// Materialize a pointer to the fill data image
NewLIR3(kThumb2Adr, r1, 0, WrapPointer(tab_rec));
@@ -192,7 +192,7 @@
null_check_branch = OpCmpImmBranch(kCondEq, rs_r0, 0, NULL);
}
}
- LoadWordDisp(rs_rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), rs_r2);
+ LoadWordDisp(rs_rARM_SELF, Thread::ThinLockIdOffset<4>().Int32Value(), rs_r2);
NewLIR3(kThumb2Ldrex, r1, r0, mirror::Object::MonitorOffset().Int32Value() >> 2);
MarkPossibleNullPointerException(opt_flags);
LIR* not_unlocked_branch = OpCmpImmBranch(kCondNe, rs_r1, 0, NULL);
@@ -207,7 +207,7 @@
}
// TODO: move to a slow path.
// Go expensive route - artLockObjectFromCode(obj);
- LoadWordDisp(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(pLockObject).Int32Value(), rs_rARM_LR);
+ LoadWordDisp(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(4, pLockObject).Int32Value(), rs_rARM_LR);
ClobberCallerSave();
LIR* call_inst = OpReg(kOpBlx, rs_rARM_LR);
MarkSafepointPC(call_inst);
@@ -218,7 +218,7 @@
} else {
// Explicit null-check as slow-path is entered using an IT.
GenNullCheck(rs_r0, opt_flags);
- LoadWordDisp(rs_rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), rs_r2);
+ LoadWordDisp(rs_rARM_SELF, Thread::ThinLockIdOffset<4>().Int32Value(), rs_r2);
NewLIR3(kThumb2Ldrex, r1, r0, mirror::Object::MonitorOffset().Int32Value() >> 2);
MarkPossibleNullPointerException(opt_flags);
OpRegImm(kOpCmp, rs_r1, 0);
@@ -227,7 +227,7 @@
OpRegImm(kOpCmp, rs_r1, 0);
OpIT(kCondNe, "T");
// Go expensive route - artLockObjectFromCode(self, obj);
- LoadWordDisp/*ne*/(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(pLockObject).Int32Value(), rs_rARM_LR);
+ LoadWordDisp/*ne*/(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(4, pLockObject).Int32Value(), rs_rARM_LR);
ClobberCallerSave();
LIR* call_inst = OpReg(kOpBlx/*ne*/, rs_rARM_LR);
MarkSafepointPC(call_inst);
@@ -245,7 +245,7 @@
LoadValueDirectFixed(rl_src, rs_r0); // Get obj
LockCallTemps(); // Prepare for explicit register usage
LIR* null_check_branch = nullptr;
- LoadWordDisp(rs_rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), rs_r2);
+ LoadWordDisp(rs_rARM_SELF, Thread::ThinLockIdOffset<4>().Int32Value(), rs_r2);
constexpr bool kArchVariantHasGoodBranchPredictor = false; // TODO: true if cortex-A15.
if (kArchVariantHasGoodBranchPredictor) {
if ((opt_flags & MIR_IGNORE_NULL_CHECK) && !(cu_->disable_opt & (1 << kNullCheckElimination))) {
@@ -270,7 +270,7 @@
}
// TODO: move to a slow path.
// Go expensive route - artUnlockObjectFromCode(obj);
- LoadWordDisp(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(pUnlockObject).Int32Value(), rs_rARM_LR);
+ LoadWordDisp(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject).Int32Value(), rs_rARM_LR);
ClobberCallerSave();
LIR* call_inst = OpReg(kOpBlx, rs_rARM_LR);
MarkSafepointPC(call_inst);
@@ -283,14 +283,14 @@
GenNullCheck(rs_r0, opt_flags);
LoadWordDisp(rs_r0, mirror::Object::MonitorOffset().Int32Value(), rs_r1); // Get lock
MarkPossibleNullPointerException(opt_flags);
- LoadWordDisp(rs_rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), rs_r2);
+ LoadWordDisp(rs_rARM_SELF, Thread::ThinLockIdOffset<4>().Int32Value(), rs_r2);
LoadConstantNoClobber(rs_r3, 0);
// Is lock unheld on lock or held by us (==thread_id) on unlock?
OpRegReg(kOpCmp, rs_r1, rs_r2);
OpIT(kCondEq, "EE");
StoreWordDisp/*eq*/(rs_r0, mirror::Object::MonitorOffset().Int32Value(), rs_r3);
// Go expensive route - UnlockObjectFromCode(obj);
- LoadWordDisp/*ne*/(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(pUnlockObject).Int32Value(),
+ LoadWordDisp/*ne*/(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject).Int32Value(),
rs_rARM_LR);
ClobberCallerSave();
LIR* call_inst = OpReg(kOpBlx/*ne*/, rs_rARM_LR);
@@ -300,7 +300,7 @@
}
void ArmMir2Lir::GenMoveException(RegLocation rl_dest) {
- int ex_offset = Thread::ExceptionOffset().Int32Value();
+ int ex_offset = Thread::ExceptionOffset<4>().Int32Value();
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
RegStorage reset_reg = AllocTemp();
LoadWordDisp(rs_rARM_SELF, ex_offset, rl_result.reg);
@@ -317,7 +317,7 @@
RegStorage reg_card_base = AllocTemp();
RegStorage reg_card_no = AllocTemp();
LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
- LoadWordDisp(rs_rARM_SELF, Thread::CardTableOffset().Int32Value(), reg_card_base);
+ LoadWordDisp(rs_rARM_SELF, Thread::CardTableOffset<4>().Int32Value(), reg_card_base);
OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift);
StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, kUnsignedByte);
LIR* target = NewLIR0(kPseudoTargetLabel);
@@ -350,7 +350,7 @@
if (!skip_overflow_check) {
if (Runtime::Current()->ExplicitStackOverflowChecks()) {
/* Load stack limit */
- LoadWordDisp(rs_rARM_SELF, Thread::StackEndOffset().Int32Value(), rs_r12);
+ LoadWordDisp(rs_rARM_SELF, Thread::StackEndOffset<4>().Int32Value(), rs_r12);
}
}
/* Spill core callee saves */
@@ -384,7 +384,7 @@
}
m2l_->OpRegImm(kOpAdd, rs_rARM_SP, sp_displace_);
m2l_->ClobberCallerSave();
- ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowStackOverflow);
+ ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pThrowStackOverflow);
// Load the entrypoint directly into the pc instead of doing a load + branch. Assumes
// codegen and target are in thumb2 mode.
m2l_->LoadWordDisp(rs_rARM_SELF, func_offset.Int32Value(), rs_rARM_PC);
diff --git a/compiler/dex/quick/arm/codegen_arm.h b/compiler/dex/quick/arm/codegen_arm.h
index 8bfdb6a..7982231 100644
--- a/compiler/dex/quick/arm/codegen_arm.h
+++ b/compiler/dex/quick/arm/codegen_arm.h
@@ -30,7 +30,7 @@
bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
RegLocation rl_dest, int lit);
LIR* CheckSuspendUsingLoad() OVERRIDE;
- RegStorage LoadHelper(ThreadOffset offset);
+ RegStorage LoadHelper(ThreadOffset<4> offset);
LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
int s_reg);
LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, int s_reg);
@@ -171,12 +171,12 @@
LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
LIR* OpTestSuspend(LIR* target);
- LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
+ LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset);
LIR* OpVldm(RegStorage r_base, int count);
LIR* OpVstm(RegStorage r_base, int count);
void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
void OpRegCopyWide(RegStorage dest, RegStorage src);
- void OpTlsCmp(ThreadOffset offset, int val);
+ void OpTlsCmp(ThreadOffset<4> offset, int val);
LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
int s_reg);
diff --git a/compiler/dex/quick/arm/fp_arm.cc b/compiler/dex/quick/arm/fp_arm.cc
index 398bf96..07a13ce 100644
--- a/compiler/dex/quick/arm/fp_arm.cc
+++ b/compiler/dex/quick/arm/fp_arm.cc
@@ -49,7 +49,7 @@
case Instruction::REM_FLOAT_2ADDR:
case Instruction::REM_FLOAT:
FlushAllRegs(); // Send everything to home location
- CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(pFmodf), rl_src1, rl_src2,
+ CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pFmodf), rl_src1, rl_src2,
false);
rl_result = GetReturn(true);
StoreValue(rl_dest, rl_result);
@@ -92,7 +92,7 @@
case Instruction::REM_DOUBLE_2ADDR:
case Instruction::REM_DOUBLE:
FlushAllRegs(); // Send everything to home location
- CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(pFmod), rl_src1, rl_src2,
+ CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pFmod), rl_src1, rl_src2,
false);
rl_result = GetReturnWide(true);
StoreValueWide(rl_dest, rl_result);
@@ -162,7 +162,7 @@
return;
}
case Instruction::FLOAT_TO_LONG:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+ GenConversionCall(QUICK_ENTRYPOINT_OFFSET(4, pF2l), rl_dest, rl_src);
return;
case Instruction::LONG_TO_FLOAT: {
rl_src = LoadValueWide(rl_src, kFPReg);
@@ -192,7 +192,7 @@
return;
}
case Instruction::DOUBLE_TO_LONG:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+ GenConversionCall(QUICK_ENTRYPOINT_OFFSET(4, pD2l), rl_dest, rl_src);
return;
default:
LOG(FATAL) << "Unexpected opcode: " << opcode;
@@ -359,7 +359,7 @@
branch = NewLIR2(kThumbBCond, 0, kArmCondEq);
ClobberCallerSave();
LockCallTemps(); // Using fixed registers
- RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pSqrt));
+ RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pSqrt));
NewLIR3(kThumb2Fmrrd, r0, r1, S2d(rl_src.reg.GetLowReg(), rl_src.reg.GetHighReg()));
NewLIR1(kThumbBlxR, r_tgt.GetReg());
NewLIR3(kThumb2Fmdrr, S2d(rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg()), r0, r1);
diff --git a/compiler/dex/quick/arm/int_arm.cc b/compiler/dex/quick/arm/int_arm.cc
index 46db466..fde6e8a 100644
--- a/compiler/dex/quick/arm/int_arm.cc
+++ b/compiler/dex/quick/arm/int_arm.cc
@@ -578,7 +578,7 @@
LOG(FATAL) << "Unexpected use of OpLea for Arm";
}
-void ArmMir2Lir::OpTlsCmp(ThreadOffset offset, int val) {
+void ArmMir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) {
LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm";
}
@@ -848,7 +848,7 @@
*/
RegLocation rl_result;
if (BadOverlap(rl_src1, rl_dest) || (BadOverlap(rl_src2, rl_dest))) {
- ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pLmul);
+ ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pLmul);
FlushAllRegs();
CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false);
rl_result = GetReturnWide(false);
diff --git a/compiler/dex/quick/arm/target_arm.cc b/compiler/dex/quick/arm/target_arm.cc
index 5bab0e3..5ebe0a3 100644
--- a/compiler/dex/quick/arm/target_arm.cc
+++ b/compiler/dex/quick/arm/target_arm.cc
@@ -727,14 +727,14 @@
FreeTemp(r3);
}
-RegStorage ArmMir2Lir::LoadHelper(ThreadOffset offset) {
+RegStorage ArmMir2Lir::LoadHelper(ThreadOffset<4> offset) {
LoadWordDisp(rs_rARM_SELF, offset.Int32Value(), rs_rARM_LR);
return rs_rARM_LR;
}
LIR* ArmMir2Lir::CheckSuspendUsingLoad() {
RegStorage tmp = rs_r0;
- LoadWordDisp(rs_rARM_SELF, Thread::ThreadSuspendTriggerOffset().Int32Value(), tmp);
+ LoadWordDisp(rs_rARM_SELF, Thread::ThreadSuspendTriggerOffset<4>().Int32Value(), tmp);
LIR* load2 = LoadWordDisp(tmp, 0, tmp);
return load2;
}
diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc
index 8df5b25..1634905 100644
--- a/compiler/dex/quick/arm/utility_arm.cc
+++ b/compiler/dex/quick/arm/utility_arm.cc
@@ -1109,7 +1109,7 @@
return res;
}
-LIR* ArmMir2Lir::OpThreadMem(OpKind op, ThreadOffset thread_offset) {
+LIR* ArmMir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) {
LOG(FATAL) << "Unexpected use of OpThreadMem for Arm";
return NULL;
}
diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc
index 866ce5f..44f81f8 100644
--- a/compiler/dex/quick/gen_common.cc
+++ b/compiler/dex/quick/gen_common.cc
@@ -251,7 +251,7 @@
void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest,
RegLocation rl_src) {
FlushAllRegs(); /* Everything to home location */
- ThreadOffset func_offset(-1);
+ ThreadOffset<4> func_offset(-1);
const DexFile* dex_file = cu_->dex_file;
CompilerDriver* driver = cu_->compiler_driver;
if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *dex_file,
@@ -265,22 +265,22 @@
// The fast path.
if (!use_direct_type_ptr) {
LoadClassType(type_idx, kArg0);
- func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArrayResolved);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pAllocArrayResolved);
CallRuntimeHelperRegMethodRegLocation(func_offset, TargetReg(kArg0), rl_src, true);
} else {
// Use the direct pointer.
- func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArrayResolved);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pAllocArrayResolved);
CallRuntimeHelperImmMethodRegLocation(func_offset, direct_type_ptr, rl_src, true);
}
} else {
// The slow path.
DCHECK_EQ(func_offset.Int32Value(), -1);
- func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArray);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pAllocArray);
CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true);
}
DCHECK_NE(func_offset.Int32Value(), -1);
} else {
- func_offset= QUICK_ENTRYPOINT_OFFSET(pAllocArrayWithAccessCheck);
+ func_offset= QUICK_ENTRYPOINT_OFFSET(4, pAllocArrayWithAccessCheck);
CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true);
}
RegLocation rl_result = GetReturn(false);
@@ -297,12 +297,12 @@
int elems = info->num_arg_words;
int type_idx = info->index;
FlushAllRegs(); /* Everything to home location */
- ThreadOffset func_offset(-1);
+ ThreadOffset<4> func_offset(-1);
if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *cu_->dex_file,
type_idx)) {
- func_offset = QUICK_ENTRYPOINT_OFFSET(pCheckAndAllocArray);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pCheckAndAllocArray);
} else {
- func_offset = QUICK_ENTRYPOINT_OFFSET(pCheckAndAllocArrayWithAccessCheck);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pCheckAndAllocArrayWithAccessCheck);
}
CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true);
FreeTemp(TargetReg(kArg2));
@@ -410,7 +410,7 @@
void Compile() {
LIR* unresolved_target = GenerateTargetLabel();
uninit_->target = unresolved_target;
- m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeStaticStorage),
+ m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeStaticStorage),
storage_index_, true);
// Copy helper's result into r_base, a no-op on all but MIPS.
m2l_->OpRegCopy(r_base_, m2l_->TargetReg(kRet0));
@@ -502,10 +502,10 @@
FreeTemp(r_base);
} else {
FlushAllRegs(); // Everything to home locations
- ThreadOffset setter_offset =
- is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pSet64Static)
- : (is_object ? QUICK_ENTRYPOINT_OFFSET(pSetObjStatic)
- : QUICK_ENTRYPOINT_OFFSET(pSet32Static));
+ ThreadOffset<4> setter_offset =
+ is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(4, pSet64Static)
+ : (is_object ? QUICK_ENTRYPOINT_OFFSET(4, pSetObjStatic)
+ : QUICK_ENTRYPOINT_OFFSET(4, pSet32Static));
CallRuntimeHelperImmRegLocation(setter_offset, field_info.FieldIndex(), rl_src, true);
}
}
@@ -583,10 +583,10 @@
}
} else {
FlushAllRegs(); // Everything to home locations
- ThreadOffset getterOffset =
- is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pGet64Static)
- :(is_object ? QUICK_ENTRYPOINT_OFFSET(pGetObjStatic)
- : QUICK_ENTRYPOINT_OFFSET(pGet32Static));
+ ThreadOffset<4> getterOffset =
+ is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(4, pGet64Static)
+ :(is_object ? QUICK_ENTRYPOINT_OFFSET(4, pGetObjStatic)
+ : QUICK_ENTRYPOINT_OFFSET(4, pGet32Static));
CallRuntimeHelperImm(getterOffset, field_info.FieldIndex(), true);
if (is_long_or_double) {
RegLocation rl_result = GetReturnWide(rl_dest.fp);
@@ -610,7 +610,7 @@
void Mir2Lir::HandleSuspendLaunchPads() {
int num_elems = suspend_launchpads_.Size();
- ThreadOffset helper_offset = QUICK_ENTRYPOINT_OFFSET(pTestSuspend);
+ ThreadOffset<4> helper_offset = QUICK_ENTRYPOINT_OFFSET(4, pTestSuspend);
for (int i = 0; i < num_elems; i++) {
ResetRegPool();
ResetDefTracking();
@@ -632,13 +632,13 @@
LIR* lab = throw_launchpads_.Get(i);
current_dalvik_offset_ = lab->operands[1];
AppendLIR(lab);
- ThreadOffset func_offset(-1);
+ ThreadOffset<4> func_offset(-1);
int v1 = lab->operands[2];
int v2 = lab->operands[3];
const bool target_x86 = cu_->instruction_set == kX86;
switch (lab->operands[0]) {
case kThrowNullPointer:
- func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowNullPointer);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pThrowNullPointer);
break;
case kThrowConstantArrayBounds: // v1 is length reg (for Arm/Mips), v2 constant index
// v1 holds the constant array index. Mips/Arm uses v2 for length, x86 reloads.
@@ -651,7 +651,7 @@
// Make sure the following LoadConstant doesn't mess with kArg1.
LockTemp(TargetReg(kArg1));
LoadConstant(TargetReg(kArg0), v2);
- func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowArrayBounds);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds);
break;
case kThrowArrayBounds:
// Move v1 (array index) to kArg0 and v2 (array length) to kArg1
@@ -687,15 +687,15 @@
OpRegCopy(TargetReg(kArg0), RegStorage::Solo32(v1));
}
}
- func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowArrayBounds);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds);
break;
case kThrowDivZero:
- func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowDivZero);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pThrowDivZero);
break;
case kThrowNoSuchMethod:
OpRegCopy(TargetReg(kArg0), RegStorage::Solo32(v1));
func_offset =
- QUICK_ENTRYPOINT_OFFSET(pThrowNoSuchMethod);
+ QUICK_ENTRYPOINT_OFFSET(4, pThrowNoSuchMethod);
break;
default:
LOG(FATAL) << "Unexpected throw kind: " << lab->operands[0];
@@ -762,10 +762,10 @@
StoreValue(rl_dest, rl_result);
}
} else {
- ThreadOffset getterOffset =
- is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pGet64Instance)
- : (is_object ? QUICK_ENTRYPOINT_OFFSET(pGetObjInstance)
- : QUICK_ENTRYPOINT_OFFSET(pGet32Instance));
+ ThreadOffset<4> getterOffset =
+ is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(4, pGet64Instance)
+ : (is_object ? QUICK_ENTRYPOINT_OFFSET(4, pGetObjInstance)
+ : QUICK_ENTRYPOINT_OFFSET(4, pGet32Instance));
CallRuntimeHelperImmRegLocation(getterOffset, field_info.FieldIndex(), rl_obj, true);
if (is_long_or_double) {
RegLocation rl_result = GetReturnWide(rl_dest.fp);
@@ -820,10 +820,10 @@
}
}
} else {
- ThreadOffset setter_offset =
- is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pSet64Instance)
- : (is_object ? QUICK_ENTRYPOINT_OFFSET(pSetObjInstance)
- : QUICK_ENTRYPOINT_OFFSET(pSet32Instance));
+ ThreadOffset<4> setter_offset =
+ is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(4, pSet64Instance)
+ : (is_object ? QUICK_ENTRYPOINT_OFFSET(4, pSetObjInstance)
+ : QUICK_ENTRYPOINT_OFFSET(4, pSet32Instance));
CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_info.FieldIndex(),
rl_obj, rl_src, true);
}
@@ -834,10 +834,10 @@
bool needs_range_check = !(opt_flags & MIR_IGNORE_RANGE_CHECK);
bool needs_null_check = !((cu_->disable_opt & (1 << kNullCheckElimination)) &&
(opt_flags & MIR_IGNORE_NULL_CHECK));
- ThreadOffset helper = needs_range_check
- ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(pAputObjectWithNullAndBoundCheck)
- : QUICK_ENTRYPOINT_OFFSET(pAputObjectWithBoundCheck))
- : QUICK_ENTRYPOINT_OFFSET(pAputObject);
+ ThreadOffset<4> helper = needs_range_check
+ ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(4, pAputObjectWithNullAndBoundCheck)
+ : QUICK_ENTRYPOINT_OFFSET(4, pAputObjectWithBoundCheck))
+ : QUICK_ENTRYPOINT_OFFSET(4, pAputObject);
CallRuntimeHelperRegLocationRegLocationRegLocation(helper, rl_array, rl_index, rl_src, true);
}
@@ -850,7 +850,7 @@
type_idx)) {
// Call out to helper which resolves type and verifies access.
// Resolved type returned in kRet0.
- CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess),
+ CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess),
type_idx, rl_method.reg, true);
RegLocation rl_result = GetReturn(false);
StoreValue(rl_dest, rl_result);
@@ -882,7 +882,7 @@
void Compile() {
GenerateTargetLabel();
- m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx_,
+ m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_,
rl_method_.reg, true);
m2l_->OpRegCopy(rl_result_.reg, m2l_->TargetReg(kRet0));
@@ -950,7 +950,7 @@
void Compile() {
GenerateTargetLabel();
- RegStorage r_tgt = m2l_->CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(pResolveString));
+ RegStorage r_tgt = m2l_->CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(4, pResolveString));
m2l_->OpRegCopy(m2l_->TargetReg(kArg0), r_method_); // .eq
LIR* call_inst = m2l_->OpReg(kOpBlx, r_tgt);
@@ -970,7 +970,7 @@
DCHECK_EQ(cu_->instruction_set, kX86);
LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kRet0), 0, NULL);
LoadConstant(TargetReg(kArg1), string_idx);
- CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pResolveString), r_method, TargetReg(kArg1),
+ CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pResolveString), r_method, TargetReg(kArg1),
true);
LIR* target = NewLIR0(kPseudoTargetLabel);
branch->target = target;
@@ -995,7 +995,7 @@
FlushAllRegs(); /* Everything to home location */
// alloc will always check for resolution, do we also need to verify
// access because the verifier was unable to?
- ThreadOffset func_offset(-1);
+ ThreadOffset<4> func_offset(-1);
const DexFile* dex_file = cu_->dex_file;
CompilerDriver* driver = cu_->compiler_driver;
if (driver->CanAccessInstantiableTypeWithoutChecks(
@@ -1010,31 +1010,31 @@
if (!use_direct_type_ptr) {
LoadClassType(type_idx, kArg0);
if (!is_type_initialized) {
- func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectResolved);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pAllocObjectResolved);
CallRuntimeHelperRegMethod(func_offset, TargetReg(kArg0), true);
} else {
- func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectInitialized);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pAllocObjectInitialized);
CallRuntimeHelperRegMethod(func_offset, TargetReg(kArg0), true);
}
} else {
// Use the direct pointer.
if (!is_type_initialized) {
- func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectResolved);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pAllocObjectResolved);
CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true);
} else {
- func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectInitialized);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pAllocObjectInitialized);
CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true);
}
}
} else {
// The slow path.
DCHECK_EQ(func_offset.Int32Value(), -1);
- func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObject);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pAllocObject);
CallRuntimeHelperImmMethod(func_offset, type_idx, true);
}
DCHECK_NE(func_offset.Int32Value(), -1);
} else {
- func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectWithAccessCheck);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pAllocObjectWithAccessCheck);
CallRuntimeHelperImmMethod(func_offset, type_idx, true);
}
RegLocation rl_result = GetReturn(false);
@@ -1043,7 +1043,7 @@
void Mir2Lir::GenThrow(RegLocation rl_src) {
FlushAllRegs();
- CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pDeliverException), rl_src, true);
+ CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pDeliverException), rl_src, true);
}
// For final classes there are no sub-classes to check and so we can answer the instance-of
@@ -1118,7 +1118,7 @@
if (needs_access_check) {
// Check we have access to type_idx and if not throw IllegalAccessError,
// returns Class* in kArg0
- CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess),
+ CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess),
type_idx, true);
OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path
LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref
@@ -1140,7 +1140,7 @@
LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL);
// Not resolved
// Call out to helper, which will return resolved type in kRet0
- CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx, true);
+ CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx, true);
OpRegCopy(TargetReg(kArg2), TargetReg(kRet0)); // Align usage with fast path
LoadValueDirectFixed(rl_src, TargetReg(kArg0)); /* reload Ref */
// Rejoin code paths
@@ -1175,7 +1175,7 @@
}
} else {
if (cu_->instruction_set == kThumb2) {
- RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial));
+ RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial));
if (!type_known_abstract) {
/* Uses conditional nullification */
OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); // Same?
@@ -1191,7 +1191,7 @@
LoadConstant(rl_result.reg, 1); // assume true
branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL);
}
- RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial));
+ RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial));
OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .ne case - arg0 <= class
OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class)
FreeTemp(r_tgt);
@@ -1252,7 +1252,7 @@
// Check we have access to type_idx and if not throw IllegalAccessError,
// returns Class* in kRet0
// InitializeTypeAndVerifyAccess(idx, method)
- CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess),
+ CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess),
type_idx, TargetReg(kArg1), true);
OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path
} else if (use_declaring_class) {
@@ -1285,7 +1285,7 @@
// Call out to helper, which will return resolved type in kArg0
// InitializeTypeFromCode(idx, method)
- m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx_,
+ m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx_,
m2l_->TargetReg(kArg1), true);
m2l_->OpRegCopy(class_reg_, m2l_->TargetReg(kRet0)); // Align usage with fast path
m2l_->OpUnconditionalBranch(cont_);
@@ -1316,7 +1316,7 @@
m2l_->LoadWordDisp(m2l_->TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(),
m2l_->TargetReg(kArg1));
}
- m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pCheckCast), m2l_->TargetReg(kArg2),
+ m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pCheckCast), m2l_->TargetReg(kArg2),
m2l_->TargetReg(kArg1), true);
m2l_->OpUnconditionalBranch(cont_);
@@ -1401,20 +1401,20 @@
void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_shift) {
- ThreadOffset func_offset(-1);
+ ThreadOffset<4> func_offset(-1);
switch (opcode) {
case Instruction::SHL_LONG:
case Instruction::SHL_LONG_2ADDR:
- func_offset = QUICK_ENTRYPOINT_OFFSET(pShlLong);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pShlLong);
break;
case Instruction::SHR_LONG:
case Instruction::SHR_LONG_2ADDR:
- func_offset = QUICK_ENTRYPOINT_OFFSET(pShrLong);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pShrLong);
break;
case Instruction::USHR_LONG:
case Instruction::USHR_LONG_2ADDR:
- func_offset = QUICK_ENTRYPOINT_OFFSET(pUshrLong);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pUshrLong);
break;
default:
LOG(FATAL) << "Unexpected case";
@@ -1547,7 +1547,7 @@
// If we haven't already generated the code use the callout function.
if (!done) {
- ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pIdivmod);
+ ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pIdivmod);
FlushAllRegs(); /* Send everything to home location */
LoadValueDirectFixed(rl_src2, TargetReg(kArg1));
RegStorage r_tgt = CallHelperSetup(func_offset);
@@ -1798,7 +1798,7 @@
FlushAllRegs(); /* Everything to home location. */
LoadValueDirectFixed(rl_src, TargetReg(kArg0));
Clobber(TargetReg(kArg0));
- ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pIdivmod);
+ ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pIdivmod);
CallRuntimeHelperRegImm(func_offset, TargetReg(kArg0), lit, false);
if (is_div)
rl_result = GetReturn(false);
@@ -1829,7 +1829,7 @@
OpKind second_op = kOpBkpt;
bool call_out = false;
bool check_zero = false;
- ThreadOffset func_offset(-1);
+ ThreadOffset<4> func_offset(-1);
int ret_reg = TargetReg(kRet0).GetReg();
switch (opcode) {
@@ -1875,7 +1875,7 @@
} else {
call_out = true;
ret_reg = TargetReg(kRet0).GetReg();
- func_offset = QUICK_ENTRYPOINT_OFFSET(pLmul);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pLmul);
}
break;
case Instruction::DIV_LONG:
@@ -1883,13 +1883,13 @@
call_out = true;
check_zero = true;
ret_reg = TargetReg(kRet0).GetReg();
- func_offset = QUICK_ENTRYPOINT_OFFSET(pLdiv);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pLdiv);
break;
case Instruction::REM_LONG:
case Instruction::REM_LONG_2ADDR:
call_out = true;
check_zero = true;
- func_offset = QUICK_ENTRYPOINT_OFFSET(pLmod);
+ func_offset = QUICK_ENTRYPOINT_OFFSET(4, pLmod);
/* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */
ret_reg = (cu_->instruction_set == kThumb2) ? TargetReg(kArg2).GetReg() : TargetReg(kRet0).GetReg();
break;
@@ -1951,7 +1951,7 @@
}
}
-void Mir2Lir::GenConversionCall(ThreadOffset func_offset,
+void Mir2Lir::GenConversionCall(ThreadOffset<4> func_offset,
RegLocation rl_dest, RegLocation rl_src) {
/*
* Don't optimize the register usage since it calls out to support
@@ -2024,13 +2024,13 @@
/* Call out to helper assembly routine that will null check obj and then lock it. */
void Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) {
FlushAllRegs();
- CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pLockObject), rl_src, true);
+ CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pLockObject), rl_src, true);
}
/* Call out to helper assembly routine that will null check obj and then unlock it. */
void Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) {
FlushAllRegs();
- CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pUnlockObject), rl_src, true);
+ CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject), rl_src, true);
}
/* Generic code for generating a wide constant into a VR. */
diff --git a/compiler/dex/quick/gen_invoke.cc b/compiler/dex/quick/gen_invoke.cc
index 7689b51..0746913 100644
--- a/compiler/dex/quick/gen_invoke.cc
+++ b/compiler/dex/quick/gen_invoke.cc
@@ -66,12 +66,12 @@
* has a memory call operation, part 1 is a NOP for x86. For other targets,
* load arguments between the two parts.
*/
-RegStorage Mir2Lir::CallHelperSetup(ThreadOffset helper_offset) {
+RegStorage Mir2Lir::CallHelperSetup(ThreadOffset<4> helper_offset) {
return (cu_->instruction_set == kX86) ? RegStorage::InvalidReg() : LoadHelper(helper_offset);
}
/* NOTE: if r_tgt is a temp, it will be freed following use */
-LIR* Mir2Lir::CallHelper(RegStorage r_tgt, ThreadOffset helper_offset, bool safepoint_pc,
+LIR* Mir2Lir::CallHelper(RegStorage r_tgt, ThreadOffset<4> helper_offset, bool safepoint_pc,
bool use_link) {
LIR* call_inst;
OpKind op = use_link ? kOpBlx : kOpBx;
@@ -87,21 +87,22 @@
return call_inst;
}
-void Mir2Lir::CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc) {
+void Mir2Lir::CallRuntimeHelperImm(ThreadOffset<4> helper_offset, int arg0, bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
LoadConstant(TargetReg(kArg0), arg0);
ClobberCallerSave();
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperReg(ThreadOffset helper_offset, RegStorage arg0, bool safepoint_pc) {
+void Mir2Lir::CallRuntimeHelperReg(ThreadOffset<4> helper_offset, RegStorage arg0,
+ bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
OpRegCopy(TargetReg(kArg0), arg0);
ClobberCallerSave();
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0,
+void Mir2Lir::CallRuntimeHelperRegLocation(ThreadOffset<4> helper_offset, RegLocation arg0,
bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
if (arg0.wide == 0) {
@@ -114,7 +115,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1,
+void Mir2Lir::CallRuntimeHelperImmImm(ThreadOffset<4> helper_offset, int arg0, int arg1,
bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
LoadConstant(TargetReg(kArg0), arg0);
@@ -123,7 +124,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0,
+void Mir2Lir::CallRuntimeHelperImmRegLocation(ThreadOffset<4> helper_offset, int arg0,
RegLocation arg1, bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
if (arg1.wide == 0) {
@@ -137,8 +138,8 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, int arg1,
- bool safepoint_pc) {
+void Mir2Lir::CallRuntimeHelperRegLocationImm(ThreadOffset<4> helper_offset, RegLocation arg0,
+ int arg1, bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
LoadValueDirectFixed(arg0, TargetReg(kArg0));
LoadConstant(TargetReg(kArg1), arg1);
@@ -146,7 +147,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, RegStorage arg1,
+void Mir2Lir::CallRuntimeHelperImmReg(ThreadOffset<4> helper_offset, int arg0, RegStorage arg1,
bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
OpRegCopy(TargetReg(kArg1), arg1);
@@ -155,7 +156,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperRegImm(ThreadOffset helper_offset, RegStorage arg0, int arg1,
+void Mir2Lir::CallRuntimeHelperRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, int arg1,
bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
OpRegCopy(TargetReg(kArg0), arg0);
@@ -164,7 +165,8 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, bool safepoint_pc) {
+void Mir2Lir::CallRuntimeHelperImmMethod(ThreadOffset<4> helper_offset, int arg0,
+ bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
LoadCurrMethodDirect(TargetReg(kArg1));
LoadConstant(TargetReg(kArg0), arg0);
@@ -172,7 +174,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperRegMethod(ThreadOffset helper_offset, RegStorage arg0,
+void Mir2Lir::CallRuntimeHelperRegMethod(ThreadOffset<4> helper_offset, RegStorage arg0,
bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
DCHECK_NE(TargetReg(kArg1).GetReg(), arg0.GetReg());
@@ -184,7 +186,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperRegMethodRegLocation(ThreadOffset helper_offset, RegStorage arg0,
+void Mir2Lir::CallRuntimeHelperRegMethodRegLocation(ThreadOffset<4> helper_offset, RegStorage arg0,
RegLocation arg2, bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
DCHECK_NE(TargetReg(kArg1).GetReg(), arg0.GetReg());
@@ -197,8 +199,9 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, RegLocation arg0,
- RegLocation arg1, bool safepoint_pc) {
+void Mir2Lir::CallRuntimeHelperRegLocationRegLocation(ThreadOffset<4> helper_offset,
+ RegLocation arg0, RegLocation arg1,
+ bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
if (arg0.wide == 0) {
LoadValueDirectFixed(arg0, arg0.fp ? TargetReg(kFArg0) : TargetReg(kArg0));
@@ -246,7 +249,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperRegReg(ThreadOffset helper_offset, RegStorage arg0,
+void Mir2Lir::CallRuntimeHelperRegReg(ThreadOffset<4> helper_offset, RegStorage arg0,
RegStorage arg1, bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
DCHECK_NE(TargetReg(kArg0).GetReg(), arg1.GetReg()); // check copy into arg0 won't clobber arg1
@@ -256,7 +259,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, RegStorage arg0,
+void Mir2Lir::CallRuntimeHelperRegRegImm(ThreadOffset<4> helper_offset, RegStorage arg0,
RegStorage arg1, int arg2, bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
DCHECK_NE(TargetReg(kArg0).GetReg(), arg1.GetReg()); // check copy into arg0 won't clobber arg1
@@ -267,7 +270,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset,
+void Mir2Lir::CallRuntimeHelperImmMethodRegLocation(ThreadOffset<4> helper_offset,
int arg0, RegLocation arg2, bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
LoadValueDirectFixed(arg2, TargetReg(kArg2));
@@ -277,7 +280,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0,
+void Mir2Lir::CallRuntimeHelperImmMethodImm(ThreadOffset<4> helper_offset, int arg0,
int arg2, bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
LoadCurrMethodDirect(TargetReg(kArg1));
@@ -287,7 +290,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset,
+void Mir2Lir::CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<4> helper_offset,
int arg0, RegLocation arg1,
RegLocation arg2, bool safepoint_pc) {
RegStorage r_tgt = CallHelperSetup(helper_offset);
@@ -304,7 +307,7 @@
CallHelper(r_tgt, helper_offset, safepoint_pc);
}
-void Mir2Lir::CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset,
+void Mir2Lir::CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<4> helper_offset,
RegLocation arg0, RegLocation arg1,
RegLocation arg2,
bool safepoint_pc) {
@@ -597,7 +600,7 @@
return state + 1;
}
-static int NextInvokeInsnSP(CompilationUnit* cu, CallInfo* info, ThreadOffset trampoline,
+static int NextInvokeInsnSP(CompilationUnit* cu, CallInfo* info, ThreadOffset<4> trampoline,
int state, const MethodReference& target_method,
uint32_t method_idx) {
Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
@@ -623,7 +626,7 @@
const MethodReference& target_method,
uint32_t unused, uintptr_t unused2,
uintptr_t unused3, InvokeType unused4) {
- ThreadOffset trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeStaticTrampolineWithAccessCheck);
+ ThreadOffset<4> trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeStaticTrampolineWithAccessCheck);
return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0);
}
@@ -631,7 +634,7 @@
const MethodReference& target_method,
uint32_t unused, uintptr_t unused2,
uintptr_t unused3, InvokeType unused4) {
- ThreadOffset trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeDirectTrampolineWithAccessCheck);
+ ThreadOffset<4> trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeDirectTrampolineWithAccessCheck);
return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0);
}
@@ -639,7 +642,7 @@
const MethodReference& target_method,
uint32_t unused, uintptr_t unused2,
uintptr_t unused3, InvokeType unused4) {
- ThreadOffset trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeSuperTrampolineWithAccessCheck);
+ ThreadOffset<4> trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeSuperTrampolineWithAccessCheck);
return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0);
}
@@ -647,7 +650,7 @@
const MethodReference& target_method,
uint32_t unused, uintptr_t unused2,
uintptr_t unused3, InvokeType unused4) {
- ThreadOffset trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeVirtualTrampolineWithAccessCheck);
+ ThreadOffset<4> trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeVirtualTrampolineWithAccessCheck);
return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0);
}
@@ -656,7 +659,8 @@
const MethodReference& target_method,
uint32_t unused, uintptr_t unused2,
uintptr_t unused3, InvokeType unused4) {
- ThreadOffset trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeInterfaceTrampolineWithAccessCheck);
+ ThreadOffset<4> trampoline =
+ QUICK_ENTRYPOINT_OFFSET(4, pInvokeInterfaceTrampolineWithAccessCheck);
return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0);
}
@@ -986,7 +990,7 @@
// Generate memcpy
OpRegRegImm(kOpAdd, TargetReg(kArg0), TargetReg(kSp), outs_offset);
OpRegRegImm(kOpAdd, TargetReg(kArg1), TargetReg(kSp), start_offset);
- CallRuntimeHelperRegRegImm(QUICK_ENTRYPOINT_OFFSET(pMemcpy), TargetReg(kArg0),
+ CallRuntimeHelperRegRegImm(QUICK_ENTRYPOINT_OFFSET(4, pMemcpy), TargetReg(kArg0),
TargetReg(kArg1), (info->num_arg_words - 3) * 4, false);
}
@@ -1318,7 +1322,7 @@
RegLocation rl_start = info->args[2]; // 3rd arg only present in III flavor of IndexOf.
LoadValueDirectFixed(rl_start, reg_start);
}
- RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pIndexOf));
+ RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pIndexOf));
GenExplicitNullCheck(reg_ptr, info->opt_flags);
LIR* high_code_point_branch =
rl_char.is_const ? nullptr : OpCmpImmBranch(kCondGt, reg_char, 0xFFFF, nullptr);
@@ -1356,7 +1360,7 @@
LoadValueDirectFixed(rl_this, reg_this);
LoadValueDirectFixed(rl_cmp, reg_cmp);
RegStorage r_tgt = (cu_->instruction_set != kX86) ?
- LoadHelper(QUICK_ENTRYPOINT_OFFSET(pStringCompareTo)) : RegStorage::InvalidReg();
+ LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pStringCompareTo)) : RegStorage::InvalidReg();
GenExplicitNullCheck(reg_this, info->opt_flags);
info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked.
// TUNING: check if rl_cmp.s_reg_low is already null checked
@@ -1366,7 +1370,7 @@
if (cu_->instruction_set != kX86) {
OpReg(kOpBlx, r_tgt);
} else {
- OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(pStringCompareTo));
+ OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(4, pStringCompareTo));
}
RegLocation rl_return = GetReturn(false);
RegLocation rl_dest = InlineTarget(info);
@@ -1377,7 +1381,7 @@
bool Mir2Lir::GenInlinedCurrentThread(CallInfo* info) {
RegLocation rl_dest = InlineTarget(info);
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
- ThreadOffset offset = Thread::PeerOffset();
+ ThreadOffset<4> offset = Thread::PeerOffset<4>();
if (cu_->instruction_set == kThumb2 || cu_->instruction_set == kMips) {
LoadWordDisp(TargetReg(kSelf), offset.Int32Value(), rl_result.reg);
} else {
@@ -1551,22 +1555,22 @@
mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset().Int32Value());
}
} else {
- ThreadOffset trampoline(-1);
+ ThreadOffset<4> trampoline(-1);
switch (info->type) {
case kInterface:
- trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeInterfaceTrampolineWithAccessCheck);
+ trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeInterfaceTrampolineWithAccessCheck);
break;
case kDirect:
- trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeDirectTrampolineWithAccessCheck);
+ trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeDirectTrampolineWithAccessCheck);
break;
case kStatic:
- trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeStaticTrampolineWithAccessCheck);
+ trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeStaticTrampolineWithAccessCheck);
break;
case kSuper:
- trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeSuperTrampolineWithAccessCheck);
+ trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeSuperTrampolineWithAccessCheck);
break;
case kVirtual:
- trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeVirtualTrampolineWithAccessCheck);
+ trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeVirtualTrampolineWithAccessCheck);
break;
default:
LOG(FATAL) << "Unexpected invoke type";
diff --git a/compiler/dex/quick/mips/call_mips.cc b/compiler/dex/quick/mips/call_mips.cc
index 972457a..a938478 100644
--- a/compiler/dex/quick/mips/call_mips.cc
+++ b/compiler/dex/quick/mips/call_mips.cc
@@ -244,7 +244,7 @@
GenBarrier();
NewLIR0(kMipsCurrPC); // Really a jal to .+8
// Now, fill the branch delay slot with the helper load
- RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData));
+ RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pHandleFillArrayData));
GenBarrier(); // Scheduling barrier
// Construct BaseLabel and set up table base register
@@ -260,7 +260,7 @@
}
void MipsMir2Lir::GenMoveException(RegLocation rl_dest) {
- int ex_offset = Thread::ExceptionOffset().Int32Value();
+ int ex_offset = Thread::ExceptionOffset<4>().Int32Value();
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
RegStorage reset_reg = AllocTemp();
LoadWordDisp(rs_rMIPS_SELF, ex_offset, rl_result.reg);
@@ -277,7 +277,7 @@
RegStorage reg_card_base = AllocTemp();
RegStorage reg_card_no = AllocTemp();
LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
- LoadWordDisp(rs_rMIPS_SELF, Thread::CardTableOffset().Int32Value(), reg_card_base);
+ LoadWordDisp(rs_rMIPS_SELF, Thread::CardTableOffset<4>().Int32Value(), reg_card_base);
OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift);
StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, kUnsignedByte);
LIR* target = NewLIR0(kPseudoTargetLabel);
@@ -310,7 +310,7 @@
RegStorage new_sp = AllocTemp();
if (!skip_overflow_check) {
/* Load stack limit */
- LoadWordDisp(rs_rMIPS_SELF, Thread::StackEndOffset().Int32Value(), check_reg);
+ LoadWordDisp(rs_rMIPS_SELF, Thread::StackEndOffset<4>().Int32Value(), check_reg);
}
/* Spill core callee saves */
SpillCoreRegs();
@@ -331,7 +331,7 @@
m2l_->LoadWordDisp(rs_rMIPS_SP, 0, rs_rRA);
m2l_->OpRegImm(kOpAdd, rs_rMIPS_SP, sp_displace_);
m2l_->ClobberCallerSave();
- ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowStackOverflow);
+ ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pThrowStackOverflow);
RegStorage r_tgt = m2l_->CallHelperSetup(func_offset); // Doesn't clobber LR.
m2l_->CallHelper(r_tgt, func_offset, false /* MarkSafepointPC */, false /* UseLink */);
}
diff --git a/compiler/dex/quick/mips/codegen_mips.h b/compiler/dex/quick/mips/codegen_mips.h
index bc1ad02..0f9da6a 100644
--- a/compiler/dex/quick/mips/codegen_mips.h
+++ b/compiler/dex/quick/mips/codegen_mips.h
@@ -30,7 +30,7 @@
bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
RegLocation rl_dest, int lit);
LIR* CheckSuspendUsingLoad() OVERRIDE;
- RegStorage LoadHelper(ThreadOffset offset);
+ RegStorage LoadHelper(ThreadOffset<4> offset);
LIR* LoadBaseDisp(int r_base, int displacement, int r_dest, OpSize size, int s_reg);
LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
int s_reg);
@@ -170,12 +170,12 @@
LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
LIR* OpTestSuspend(LIR* target);
- LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
+ LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset);
LIR* OpVldm(RegStorage r_base, int count);
LIR* OpVstm(RegStorage r_base, int count);
void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
void OpRegCopyWide(RegStorage dest, RegStorage src);
- void OpTlsCmp(ThreadOffset offset, int val);
+ void OpTlsCmp(ThreadOffset<4> offset, int val);
// TODO: collapse r_dest.
LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
diff --git a/compiler/dex/quick/mips/fp_mips.cc b/compiler/dex/quick/mips/fp_mips.cc
index 2bc5540..a479dc7 100644
--- a/compiler/dex/quick/mips/fp_mips.cc
+++ b/compiler/dex/quick/mips/fp_mips.cc
@@ -50,7 +50,7 @@
case Instruction::REM_FLOAT_2ADDR:
case Instruction::REM_FLOAT:
FlushAllRegs(); // Send everything to home location
- CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(pFmodf), rl_src1, rl_src2,
+ CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pFmodf), rl_src1, rl_src2,
false);
rl_result = GetReturn(true);
StoreValue(rl_dest, rl_result);
@@ -93,7 +93,7 @@
case Instruction::REM_DOUBLE_2ADDR:
case Instruction::REM_DOUBLE:
FlushAllRegs(); // Send everything to home location
- CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(pFmod), rl_src1, rl_src2,
+ CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pFmod), rl_src1, rl_src2,
false);
rl_result = GetReturnWide(true);
StoreValueWide(rl_dest, rl_result);
@@ -135,22 +135,22 @@
op = kMipsFcvtdw;
break;
case Instruction::FLOAT_TO_INT:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pF2iz), rl_dest, rl_src);
+ GenConversionCall(QUICK_ENTRYPOINT_OFFSET(4, pF2iz), rl_dest, rl_src);
return;
case Instruction::DOUBLE_TO_INT:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pD2iz), rl_dest, rl_src);
+ GenConversionCall(QUICK_ENTRYPOINT_OFFSET(4, pD2iz), rl_dest, rl_src);
return;
case Instruction::LONG_TO_DOUBLE:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+ GenConversionCall(QUICK_ENTRYPOINT_OFFSET(4, pL2d), rl_dest, rl_src);
return;
case Instruction::FLOAT_TO_LONG:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+ GenConversionCall(QUICK_ENTRYPOINT_OFFSET(4, pF2l), rl_dest, rl_src);
return;
case Instruction::LONG_TO_FLOAT:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pL2f), rl_dest, rl_src);
+ GenConversionCall(QUICK_ENTRYPOINT_OFFSET(4, pL2f), rl_dest, rl_src);
return;
case Instruction::DOUBLE_TO_LONG:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+ GenConversionCall(QUICK_ENTRYPOINT_OFFSET(4, pD2l), rl_dest, rl_src);
return;
default:
LOG(FATAL) << "Unexpected opcode: " << opcode;
@@ -176,22 +176,22 @@
void MipsMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2) {
bool wide = true;
- ThreadOffset offset(-1);
+ ThreadOffset<4> offset(-1);
switch (opcode) {
case Instruction::CMPL_FLOAT:
- offset = QUICK_ENTRYPOINT_OFFSET(pCmplFloat);
+ offset = QUICK_ENTRYPOINT_OFFSET(4, pCmplFloat);
wide = false;
break;
case Instruction::CMPG_FLOAT:
- offset = QUICK_ENTRYPOINT_OFFSET(pCmpgFloat);
+ offset = QUICK_ENTRYPOINT_OFFSET(4, pCmpgFloat);
wide = false;
break;
case Instruction::CMPL_DOUBLE:
- offset = QUICK_ENTRYPOINT_OFFSET(pCmplDouble);
+ offset = QUICK_ENTRYPOINT_OFFSET(4, pCmplDouble);
break;
case Instruction::CMPG_DOUBLE:
- offset = QUICK_ENTRYPOINT_OFFSET(pCmpgDouble);
+ offset = QUICK_ENTRYPOINT_OFFSET(4, pCmpgDouble);
break;
default:
LOG(FATAL) << "Unexpected opcode: " << opcode;
diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc
index dfe8b35..2424dc5 100644
--- a/compiler/dex/quick/mips/int_mips.cc
+++ b/compiler/dex/quick/mips/int_mips.cc
@@ -270,7 +270,7 @@
LOG(FATAL) << "Unexpected use of OpLea for Arm";
}
-void MipsMir2Lir::OpTlsCmp(ThreadOffset offset, int val) {
+void MipsMir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) {
LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm";
}
diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc
index 67a44fa..1fe2bea 100644
--- a/compiler/dex/quick/mips/target_mips.cc
+++ b/compiler/dex/quick/mips/target_mips.cc
@@ -514,14 +514,14 @@
* ensure that all branch instructions can be restarted if
* there is a trap in the shadow. Allocate a temp register.
*/
-RegStorage MipsMir2Lir::LoadHelper(ThreadOffset offset) {
+RegStorage MipsMir2Lir::LoadHelper(ThreadOffset<4> offset) {
LoadWordDisp(rs_rMIPS_SELF, offset.Int32Value(), rs_rT9);
return rs_rT9;
}
LIR* MipsMir2Lir::CheckSuspendUsingLoad() {
RegStorage tmp = AllocTemp();
- LoadWordDisp(rs_rMIPS_SELF, Thread::ThreadSuspendTriggerOffset().Int32Value(), tmp);
+ LoadWordDisp(rs_rMIPS_SELF, Thread::ThreadSuspendTriggerOffset<4>().Int32Value(), tmp);
LIR *inst = LoadWordDisp(tmp, 0, tmp);
FreeTemp(tmp);
return inst;
diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc
index 4f31341..c959510 100644
--- a/compiler/dex/quick/mips/utility_mips.cc
+++ b/compiler/dex/quick/mips/utility_mips.cc
@@ -642,7 +642,7 @@
return StoreBaseDispBody(r_base, displacement, r_src.GetLow(), r_src.GetHigh(), kLong);
}
-LIR* MipsMir2Lir::OpThreadMem(OpKind op, ThreadOffset thread_offset) {
+LIR* MipsMir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) {
LOG(FATAL) << "Unexpected use of OpThreadMem for MIPS";
return NULL;
}
diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h
index 10f431f..276c4b8 100644
--- a/compiler/dex/quick/mir_to_lir.h
+++ b/compiler/dex/quick/mir_to_lir.h
@@ -601,7 +601,7 @@
RegLocation rl_src, int lit);
void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest,
RegLocation rl_src1, RegLocation rl_src2);
- void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest,
+ void GenConversionCall(ThreadOffset<4> func_offset, RegLocation rl_dest,
RegLocation rl_src);
void GenSuspendTest(int opt_flags);
void GenSuspendTestAndBranch(int opt_flags, LIR* target);
@@ -612,43 +612,44 @@
RegLocation rl_src1, RegLocation rl_src2);
// Shared by all targets - implemented in gen_invoke.cc.
- LIR* CallHelper(RegStorage r_tgt, ThreadOffset helper_offset, bool safepoint_pc,
+ LIR* CallHelper(RegStorage r_tgt, ThreadOffset<4> helper_offset, bool safepoint_pc,
bool use_link = true);
- RegStorage CallHelperSetup(ThreadOffset helper_offset);
- void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc);
- void CallRuntimeHelperReg(ThreadOffset helper_offset, RegStorage arg0, bool safepoint_pc);
- void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0,
+ RegStorage CallHelperSetup(ThreadOffset<4> helper_offset);
+ void CallRuntimeHelperImm(ThreadOffset<4> helper_offset, int arg0, bool safepoint_pc);
+ void CallRuntimeHelperReg(ThreadOffset<4> helper_offset, RegStorage arg0, bool safepoint_pc);
+ void CallRuntimeHelperRegLocation(ThreadOffset<4> helper_offset, RegLocation arg0,
bool safepoint_pc);
- void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1,
+ void CallRuntimeHelperImmImm(ThreadOffset<4> helper_offset, int arg0, int arg1,
bool safepoint_pc);
- void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0,
+ void CallRuntimeHelperImmRegLocation(ThreadOffset<4> helper_offset, int arg0,
RegLocation arg1, bool safepoint_pc);
- void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0,
+ void CallRuntimeHelperRegLocationImm(ThreadOffset<4> helper_offset, RegLocation arg0,
int arg1, bool safepoint_pc);
- void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, RegStorage arg1,
+ void CallRuntimeHelperImmReg(ThreadOffset<4> helper_offset, int arg0, RegStorage arg1,
bool safepoint_pc);
- void CallRuntimeHelperRegImm(ThreadOffset helper_offset, RegStorage arg0, int arg1,
+ void CallRuntimeHelperRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, int arg1,
bool safepoint_pc);
- void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0,
+ void CallRuntimeHelperImmMethod(ThreadOffset<4> helper_offset, int arg0,
bool safepoint_pc);
- void CallRuntimeHelperRegMethod(ThreadOffset helper_offset, RegStorage arg0, bool safepoint_pc);
- void CallRuntimeHelperRegMethodRegLocation(ThreadOffset helper_offset, RegStorage arg0,
+ void CallRuntimeHelperRegMethod(ThreadOffset<4> helper_offset, RegStorage arg0,
+ bool safepoint_pc);
+ void CallRuntimeHelperRegMethodRegLocation(ThreadOffset<4> helper_offset, RegStorage arg0,
RegLocation arg2, bool safepoint_pc);
- void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset,
+ void CallRuntimeHelperRegLocationRegLocation(ThreadOffset<4> helper_offset,
RegLocation arg0, RegLocation arg1,
bool safepoint_pc);
- void CallRuntimeHelperRegReg(ThreadOffset helper_offset, RegStorage arg0, RegStorage arg1,
+ void CallRuntimeHelperRegReg(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1,
bool safepoint_pc);
- void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, RegStorage arg0, RegStorage arg1,
+ void CallRuntimeHelperRegRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1,
int arg2, bool safepoint_pc);
- void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0,
+ void CallRuntimeHelperImmMethodRegLocation(ThreadOffset<4> helper_offset, int arg0,
RegLocation arg2, bool safepoint_pc);
- void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2,
+ void CallRuntimeHelperImmMethodImm(ThreadOffset<4> helper_offset, int arg0, int arg2,
bool safepoint_pc);
- void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset,
+ void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<4> helper_offset,
int arg0, RegLocation arg1, RegLocation arg2,
bool safepoint_pc);
- void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset,
+ void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<4> helper_offset,
RegLocation arg0, RegLocation arg1,
RegLocation arg2,
bool safepoint_pc);
@@ -670,7 +671,8 @@
/**
* @brief Used to determine the register location of destination.
- * @details This is needed during generation of inline intrinsics because it finds destination of return,
+ * @details This is needed during generation of inline intrinsics because it finds destination
+ * of return,
* either the physical register or the target of move-result.
* @param info Information about the invoke.
* @return Returns the destination location.
@@ -731,7 +733,8 @@
* @brief Used to do the final store in a wide destination as per bytecode semantics.
* @see StoreValue
* @param rl_dest The destination dalvik register location.
- * @param rl_src The source register location. Can be either physical register or dalvik register.
+ * @param rl_src The source register location. Can be either physical register or dalvik
+ * register.
*/
void StoreValueWide(RegLocation rl_dest, RegLocation rl_src);
@@ -812,7 +815,7 @@
virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div,
RegLocation rl_src, RegLocation rl_dest, int lit) = 0;
virtual LIR* CheckSuspendUsingLoad() = 0;
- virtual RegStorage LoadHelper(ThreadOffset offset) = 0;
+ virtual RegStorage LoadHelper(ThreadOffset<4> offset) = 0;
virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
int s_reg) = 0;
virtual LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest,
@@ -948,7 +951,8 @@
/**
* @brief Used for generating code that throws ArithmeticException if both registers are zero.
- * @details This is used for generating DivideByZero checks when divisor is held in two separate registers.
+ * @details This is used for generating DivideByZero checks when divisor is held in two
+ * separate registers.
* @param reg_lo The register holding the lower 32-bits.
* @param reg_hi The register holding the upper 32-bits.
*/
@@ -1047,13 +1051,13 @@
virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1,
RegStorage r_src2) = 0;
virtual LIR* OpTestSuspend(LIR* target) = 0;
- virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0;
+ virtual LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) = 0;
virtual LIR* OpVldm(RegStorage r_base, int count) = 0;
virtual LIR* OpVstm(RegStorage r_base, int count) = 0;
virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale,
int offset) = 0;
virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0;
- virtual void OpTlsCmp(ThreadOffset offset, int val) = 0;
+ virtual void OpTlsCmp(ThreadOffset<4> offset, int val) = 0;
virtual bool InexpensiveConstantInt(int32_t value) = 0;
virtual bool InexpensiveConstantFloat(int32_t value) = 0;
virtual bool InexpensiveConstantLong(int64_t value) = 0;
diff --git a/compiler/dex/quick/x86/call_x86.cc b/compiler/dex/quick/x86/call_x86.cc
index d97cf4d..729b30d 100644
--- a/compiler/dex/quick/x86/call_x86.cc
+++ b/compiler/dex/quick/x86/call_x86.cc
@@ -156,12 +156,12 @@
}
NewLIR2(kX86PcRelAdr, rX86_ARG1, WrapPointer(tab_rec));
NewLIR2(kX86Add32RR, rX86_ARG1, rX86_ARG2);
- CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData), rs_rX86_ARG0,
+ CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pHandleFillArrayData), rs_rX86_ARG0,
rs_rX86_ARG1, true);
}
void X86Mir2Lir::GenMoveException(RegLocation rl_dest) {
- int ex_offset = Thread::ExceptionOffset().Int32Value();
+ int ex_offset = Thread::ExceptionOffset<4>().Int32Value();
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
NewLIR2(kX86Mov32RT, rl_result.reg.GetReg(), ex_offset);
NewLIR2(kX86Mov32TI, ex_offset, 0);
@@ -175,7 +175,7 @@
RegStorage reg_card_base = AllocTemp();
RegStorage reg_card_no = AllocTemp();
LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
- NewLIR2(kX86Mov32RT, reg_card_base.GetReg(), Thread::CardTableOffset().Int32Value());
+ NewLIR2(kX86Mov32RT, reg_card_base.GetReg(), Thread::CardTableOffset<4>().Int32Value());
OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift);
StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, kUnsignedByte);
LIR* target = NewLIR0(kPseudoTargetLabel);
@@ -222,7 +222,7 @@
GenerateTargetLabel();
m2l_->OpRegImm(kOpAdd, rs_rX86_SP, sp_displace_);
m2l_->ClobberCallerSave();
- ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowStackOverflow);
+ ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pThrowStackOverflow);
// Assumes codegen and target are in thumb2 mode.
m2l_->CallHelper(RegStorage::InvalidReg(), func_offset, false /* MarkSafepointPC */,
false /* UseLink */);
@@ -240,7 +240,7 @@
// in case a signal comes in that's not using an alternate signal stack and the large frame may
// have moved us outside of the reserved area at the end of the stack.
// cmp rX86_SP, fs:[stack_end_]; jcc throw_launchpad
- OpRegThreadMem(kOpCmp, rX86_SP, Thread::StackEndOffset());
+ OpRegThreadMem(kOpCmp, rX86_SP, Thread::StackEndOffset<4>());
LIR* branch = OpCondBranch(kCondUlt, nullptr);
AddSlowPath(new(arena_)StackOverflowSlowPath(this, branch, frame_size_ - 4));
}
diff --git a/compiler/dex/quick/x86/codegen_x86.h b/compiler/dex/quick/x86/codegen_x86.h
index 6d427e7..56b64dd 100644
--- a/compiler/dex/quick/x86/codegen_x86.h
+++ b/compiler/dex/quick/x86/codegen_x86.h
@@ -30,7 +30,7 @@
bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
RegLocation rl_dest, int lit);
LIR* CheckSuspendUsingLoad() OVERRIDE;
- RegStorage LoadHelper(ThreadOffset offset);
+ RegStorage LoadHelper(ThreadOffset<4> offset);
LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
int s_reg);
LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, int s_reg);
@@ -245,14 +245,14 @@
LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
LIR* OpTestSuspend(LIR* target);
- LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
+ LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset);
LIR* OpVldm(RegStorage r_base, int count);
LIR* OpVstm(RegStorage r_base, int count);
void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
void OpRegCopyWide(RegStorage dest, RegStorage src);
- void OpTlsCmp(ThreadOffset offset, int val);
+ void OpTlsCmp(ThreadOffset<4> offset, int val);
- void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset);
+ void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset<4> thread_offset);
void SpillCoreRegs();
void UnSpillCoreRegs();
static const X86EncodingMap EncodingMap[kX86Last];
diff --git a/compiler/dex/quick/x86/fp_x86.cc b/compiler/dex/quick/x86/fp_x86.cc
index 3fb9012..ee5387f 100644
--- a/compiler/dex/quick/x86/fp_x86.cc
+++ b/compiler/dex/quick/x86/fp_x86.cc
@@ -49,7 +49,7 @@
case Instruction::REM_FLOAT_2ADDR:
case Instruction::REM_FLOAT:
FlushAllRegs(); // Send everything to home location
- CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(pFmodf), rl_src1, rl_src2,
+ CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pFmodf), rl_src1, rl_src2,
false);
rl_result = GetReturn(true);
StoreValue(rl_dest, rl_result);
@@ -100,7 +100,7 @@
case Instruction::REM_DOUBLE_2ADDR:
case Instruction::REM_DOUBLE:
FlushAllRegs(); // Send everything to home location
- CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(pFmod), rl_src1, rl_src2,
+ CallRuntimeHelperRegLocationRegLocation(QUICK_ENTRYPOINT_OFFSET(4, pFmod), rl_src1, rl_src2,
false);
rl_result = GetReturnWide(true);
StoreValueWide(rl_dest, rl_result);
@@ -274,10 +274,10 @@
GenLongToFP(rl_dest, rl_src, false /* is_double */);
return;
case Instruction::FLOAT_TO_LONG:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
+ GenConversionCall(QUICK_ENTRYPOINT_OFFSET(4, pF2l), rl_dest, rl_src);
return;
case Instruction::DOUBLE_TO_LONG:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pD2l), rl_dest, rl_src);
+ GenConversionCall(QUICK_ENTRYPOINT_OFFSET(4, pD2l), rl_dest, rl_src);
return;
default:
LOG(INFO) << "Unexpected opcode: " << opcode;
diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc
index 851f448..0e7ba6b 100644
--- a/compiler/dex/quick/x86/int_x86.cc
+++ b/compiler/dex/quick/x86/int_x86.cc
@@ -742,7 +742,7 @@
NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset);
}
-void X86Mir2Lir::OpTlsCmp(ThreadOffset offset, int val) {
+void X86Mir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) {
NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val);
}
@@ -893,7 +893,7 @@
// Test suspend flag, return target of taken suspend branch
LIR* X86Mir2Lir::OpTestSuspend(LIR* target) {
- OpTlsCmp(Thread::ThreadFlagsOffset(), 0);
+ OpTlsCmp(Thread::ThreadFlagsOffset<4>(), 0);
return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target);
}
@@ -1293,7 +1293,7 @@
StoreValueWide(rl_dest, rl_result);
}
-void X86Mir2Lir::OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset) {
+void X86Mir2Lir::OpRegThreadMem(OpKind op, int r_dest, ThreadOffset<4> thread_offset) {
X86OpCode opcode = kX86Bkpt;
switch (op) {
case kOpCmp: opcode = kX86Cmp32RT; break;
@@ -1834,7 +1834,7 @@
if (needs_access_check) {
// Check we have access to type_idx and if not throw IllegalAccessError,
// Caller function returns Class* in kArg0.
- CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess),
+ CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess),
type_idx, true);
OpRegCopy(class_reg, TargetReg(kRet0));
LoadValueDirectFixed(rl_src, TargetReg(kArg0));
@@ -1855,7 +1855,7 @@
// Need to test presence of type in dex cache at runtime.
LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL);
// Type is not resolved. Call out to helper, which will return resolved type in kRet0/kArg0.
- CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx, true);
+ CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx, true);
OpRegCopy(TargetReg(kArg2), TargetReg(kRet0)); // Align usage with fast path.
LoadValueDirectFixed(rl_src, TargetReg(kArg0)); /* Reload Ref. */
// Rejoin code paths
@@ -1889,7 +1889,7 @@
branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL);
}
OpRegCopy(TargetReg(kArg0), TargetReg(kArg2));
- OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial));
+ OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial));
}
// TODO: only clobber when type isn't final?
ClobberCallerSave();
diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index da64250..925e736 100644
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -581,16 +581,18 @@
X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena)
: Mir2Lir(cu, mir_graph, arena),
+ base_of_code_(nullptr), store_method_addr_(false), store_method_addr_used_(false),
method_address_insns_(arena, 100, kGrowableArrayMisc),
class_type_address_insns_(arena, 100, kGrowableArrayMisc),
call_method_insns_(arena, 100, kGrowableArrayMisc),
stack_decrement_(nullptr), stack_increment_(nullptr) {
- store_method_addr_used_ = false;
- for (int i = 0; i < kX86Last; i++) {
- if (X86Mir2Lir::EncodingMap[i].opcode != i) {
- LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name
- << " is wrong: expecting " << i << ", seeing "
- << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode);
+ if (kIsDebugBuild) {
+ for (int i = 0; i < kX86Last; i++) {
+ if (X86Mir2Lir::EncodingMap[i].opcode != i) {
+ LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name
+ << " is wrong: expecting " << i << ", seeing "
+ << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode);
+ }
}
}
}
@@ -601,7 +603,7 @@
}
// Not used in x86
-RegStorage X86Mir2Lir::LoadHelper(ThreadOffset offset) {
+RegStorage X86Mir2Lir::LoadHelper(ThreadOffset<4> offset) {
LOG(FATAL) << "Unexpected use of LoadHelper in x86";
return RegStorage::InvalidReg();
}
diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc
index bb5d387..e9faa7f 100644
--- a/compiler/dex/quick/x86/utility_x86.cc
+++ b/compiler/dex/quick/x86/utility_x86.cc
@@ -468,7 +468,7 @@
return OpRegImm(op, r_dest, value);
}
-LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset thread_offset) {
+LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) {
X86OpCode opcode = kX86Bkpt;
switch (op) {
case kOpBlx: opcode = kX86CallT; break;
diff --git a/compiler/driver/compiler_driver.cc b/compiler/driver/compiler_driver.cc
index 59754d5..c367260 100644
--- a/compiler/driver/compiler_driver.cc
+++ b/compiler/driver/compiler_driver.cc
@@ -336,6 +336,7 @@
compiler_(Compiler::Create(compiler_kind)),
instruction_set_(instruction_set),
instruction_set_features_(instruction_set_features),
+ instruction_set_is_64_bit_(instruction_set == kX86_64 || instruction_set == kArm64),
freezing_constructor_lock_("freezing constructor lock"),
compiled_classes_lock_("compiled classes lock"),
compiled_methods_lock_("compiled method lock"),
@@ -443,54 +444,55 @@
return res;
}
+#define CREATE_TRAMPOLINE(type, abi, offset) \
+ if (instruction_set_is_64_bit_) { \
+ return CreateTrampoline64(instruction_set_, abi, \
+ type ## _ENTRYPOINT_OFFSET(8, offset)); \
+ } else { \
+ return CreateTrampoline32(instruction_set_, abi, \
+ type ## _ENTRYPOINT_OFFSET(4, offset)); \
+ }
+
const std::vector<uint8_t>* CompilerDriver::CreateInterpreterToInterpreterBridge() const {
- return CreateTrampoline(instruction_set_, kInterpreterAbi,
- INTERPRETER_ENTRYPOINT_OFFSET(pInterpreterToInterpreterBridge));
+ CREATE_TRAMPOLINE(INTERPRETER, kInterpreterAbi, pInterpreterToInterpreterBridge)
}
const std::vector<uint8_t>* CompilerDriver::CreateInterpreterToCompiledCodeBridge() const {
- return CreateTrampoline(instruction_set_, kInterpreterAbi,
- INTERPRETER_ENTRYPOINT_OFFSET(pInterpreterToCompiledCodeBridge));
+ CREATE_TRAMPOLINE(INTERPRETER, kInterpreterAbi, pInterpreterToCompiledCodeBridge)
}
const std::vector<uint8_t>* CompilerDriver::CreateJniDlsymLookup() const {
- return CreateTrampoline(instruction_set_, kJniAbi, JNI_ENTRYPOINT_OFFSET(pDlsymLookup));
+ CREATE_TRAMPOLINE(JNI, kJniAbi, pDlsymLookup)
}
const std::vector<uint8_t>* CompilerDriver::CreatePortableImtConflictTrampoline() const {
- return CreateTrampoline(instruction_set_, kPortableAbi,
- PORTABLE_ENTRYPOINT_OFFSET(pPortableImtConflictTrampoline));
+ CREATE_TRAMPOLINE(PORTABLE, kPortableAbi, pPortableImtConflictTrampoline)
}
const std::vector<uint8_t>* CompilerDriver::CreatePortableResolutionTrampoline() const {
- return CreateTrampoline(instruction_set_, kPortableAbi,
- PORTABLE_ENTRYPOINT_OFFSET(pPortableResolutionTrampoline));
+ CREATE_TRAMPOLINE(PORTABLE, kPortableAbi, pPortableResolutionTrampoline)
}
const std::vector<uint8_t>* CompilerDriver::CreatePortableToInterpreterBridge() const {
- return CreateTrampoline(instruction_set_, kPortableAbi,
- PORTABLE_ENTRYPOINT_OFFSET(pPortableToInterpreterBridge));
+ CREATE_TRAMPOLINE(PORTABLE, kPortableAbi, pPortableToInterpreterBridge)
}
const std::vector<uint8_t>* CompilerDriver::CreateQuickGenericJniTrampoline() const {
- return CreateTrampoline(instruction_set_, kQuickAbi,
- QUICK_ENTRYPOINT_OFFSET(pQuickGenericJniTrampoline));
+ CREATE_TRAMPOLINE(QUICK, kQuickAbi, pQuickGenericJniTrampoline)
}
const std::vector<uint8_t>* CompilerDriver::CreateQuickImtConflictTrampoline() const {
- return CreateTrampoline(instruction_set_, kQuickAbi,
- QUICK_ENTRYPOINT_OFFSET(pQuickImtConflictTrampoline));
+ CREATE_TRAMPOLINE(QUICK, kQuickAbi, pQuickImtConflictTrampoline)
}
const std::vector<uint8_t>* CompilerDriver::CreateQuickResolutionTrampoline() const {
- return CreateTrampoline(instruction_set_, kQuickAbi,
- QUICK_ENTRYPOINT_OFFSET(pQuickResolutionTrampoline));
+ CREATE_TRAMPOLINE(QUICK, kQuickAbi, pQuickResolutionTrampoline)
}
const std::vector<uint8_t>* CompilerDriver::CreateQuickToInterpreterBridge() const {
- return CreateTrampoline(instruction_set_, kQuickAbi,
- QUICK_ENTRYPOINT_OFFSET(pQuickToInterpreterBridge));
+ CREATE_TRAMPOLINE(QUICK, kQuickAbi, pQuickToInterpreterBridge)
}
+#undef CREATE_TRAMPOLINE
void CompilerDriver::CompileAll(jobject class_loader,
const std::vector<const DexFile*>& dex_files,
diff --git a/compiler/driver/compiler_driver.h b/compiler/driver/compiler_driver.h
index 256aa46..ddb62e1 100644
--- a/compiler/driver/compiler_driver.h
+++ b/compiler/driver/compiler_driver.h
@@ -719,6 +719,7 @@
const InstructionSet instruction_set_;
const InstructionSetFeatures instruction_set_features_;
+ const bool instruction_set_is_64_bit_;
// All class references that require
mutable ReaderWriterMutex freezing_constructor_lock_ DEFAULT_MUTEX_ACQUIRED_AFTER;
diff --git a/compiler/jni/quick/jni_compiler.cc b/compiler/jni/quick/jni_compiler.cc
index c89bc40..dcdcdd1 100644
--- a/compiler/jni/quick/jni_compiler.cc
+++ b/compiler/jni/quick/jni_compiler.cc
@@ -101,10 +101,10 @@
__ StoreImmediateToFrame(main_jni_conv->SirtNumRefsOffset(),
main_jni_conv->ReferenceCount(),
mr_conv->InterproceduralScratchRegister());
- __ CopyRawPtrFromThread(main_jni_conv->SirtLinkOffset(),
- Thread::TopSirtOffset(),
+ __ CopyRawPtrFromThread32(main_jni_conv->SirtLinkOffset(),
+ Thread::TopSirtOffset<4>(),
mr_conv->InterproceduralScratchRegister());
- __ StoreStackOffsetToThread(Thread::TopSirtOffset(),
+ __ StoreStackOffsetToThread32(Thread::TopSirtOffset<4>(),
main_jni_conv->SirtOffset(),
mr_conv->InterproceduralScratchRegister());
@@ -154,8 +154,8 @@
}
// 4. Write out the end of the quick frames.
- __ StoreStackPointerToThread(Thread::TopOfManagedStackOffset());
- __ StoreImmediateToThread(Thread::TopOfManagedStackPcOffset(), 0,
+ __ StoreStackPointerToThread32(Thread::TopOfManagedStackOffset<4>());
+ __ StoreImmediateToThread32(Thread::TopOfManagedStackPcOffset<4>(), 0,
mr_conv->InterproceduralScratchRegister());
// 5. Move frame down to allow space for out going args.
@@ -169,8 +169,8 @@
// can occur. The result is the saved JNI local state that is restored by the exit call. We
// abuse the JNI calling convention here, that is guaranteed to support passing 2 pointer
// arguments.
- ThreadOffset jni_start = is_synchronized ? QUICK_ENTRYPOINT_OFFSET(pJniMethodStartSynchronized)
- : QUICK_ENTRYPOINT_OFFSET(pJniMethodStart);
+ ThreadOffset<4> jni_start = is_synchronized ? QUICK_ENTRYPOINT_OFFSET(4, pJniMethodStartSynchronized)
+ : QUICK_ENTRYPOINT_OFFSET(4, pJniMethodStart);
main_jni_conv->ResetIterator(FrameOffset(main_out_arg_size));
FrameOffset locked_object_sirt_offset(0);
if (is_synchronized) {
@@ -197,7 +197,7 @@
} else {
__ GetCurrentThread(main_jni_conv->CurrentParamStackOffset(),
main_jni_conv->InterproceduralScratchRegister());
- __ Call(ThreadOffset(jni_start), main_jni_conv->InterproceduralScratchRegister());
+ __ CallFromThread32(jni_start, main_jni_conv->InterproceduralScratchRegister());
}
if (is_synchronized) { // Check for exceptions from monitor enter.
__ ExceptionPoll(main_jni_conv->InterproceduralScratchRegister(), main_out_arg_size);
@@ -259,10 +259,10 @@
if (main_jni_conv->IsCurrentParamInRegister()) {
ManagedRegister jni_env = main_jni_conv->CurrentParamRegister();
DCHECK(!jni_env.Equals(main_jni_conv->InterproceduralScratchRegister()));
- __ LoadRawPtrFromThread(jni_env, Thread::JniEnvOffset());
+ __ LoadRawPtrFromThread32(jni_env, Thread::JniEnvOffset<4>());
} else {
FrameOffset jni_env = main_jni_conv->CurrentParamStackOffset();
- __ CopyRawPtrFromThread(jni_env, Thread::JniEnvOffset(),
+ __ CopyRawPtrFromThread32(jni_env, Thread::JniEnvOffset<4>(),
main_jni_conv->InterproceduralScratchRegister());
}
@@ -298,16 +298,16 @@
// 12. Call into JNI method end possibly passing a returned reference, the method and the current
// thread.
end_jni_conv->ResetIterator(FrameOffset(end_out_arg_size));
- ThreadOffset jni_end(-1);
+ ThreadOffset<4> jni_end(-1);
if (reference_return) {
// Pass result.
- jni_end = is_synchronized ? QUICK_ENTRYPOINT_OFFSET(pJniMethodEndWithReferenceSynchronized)
- : QUICK_ENTRYPOINT_OFFSET(pJniMethodEndWithReference);
+ jni_end = is_synchronized ? QUICK_ENTRYPOINT_OFFSET(4, pJniMethodEndWithReferenceSynchronized)
+ : QUICK_ENTRYPOINT_OFFSET(4, pJniMethodEndWithReference);
SetNativeParameter(jni_asm.get(), end_jni_conv.get(), end_jni_conv->ReturnRegister());
end_jni_conv->Next();
} else {
- jni_end = is_synchronized ? QUICK_ENTRYPOINT_OFFSET(pJniMethodEndSynchronized)
- : QUICK_ENTRYPOINT_OFFSET(pJniMethodEnd);
+ jni_end = is_synchronized ? QUICK_ENTRYPOINT_OFFSET(4, pJniMethodEndSynchronized)
+ : QUICK_ENTRYPOINT_OFFSET(4, pJniMethodEnd);
}
// Pass saved local reference state.
if (end_jni_conv->IsCurrentParamOnStack()) {
@@ -339,7 +339,7 @@
} else {
__ GetCurrentThread(end_jni_conv->CurrentParamStackOffset(),
end_jni_conv->InterproceduralScratchRegister());
- __ Call(ThreadOffset(jni_end), end_jni_conv->InterproceduralScratchRegister());
+ __ CallFromThread32(ThreadOffset<4>(jni_end), end_jni_conv->InterproceduralScratchRegister());
}
// 13. Reload return value
diff --git a/compiler/jni/quick/x86_64/calling_convention_x86_64.cc b/compiler/jni/quick/x86_64/calling_convention_x86_64.cc
index 8ebea46..24298d2 100644
--- a/compiler/jni/quick/x86_64/calling_convention_x86_64.cc
+++ b/compiler/jni/quick/x86_64/calling_convention_x86_64.cc
@@ -39,7 +39,7 @@
static ManagedRegister ReturnRegisterForShorty(const char* shorty, bool jni) {
if (shorty[0] == 'F' || shorty[0] == 'D') {
- return X86_64ManagedRegister::FromXmmRegister(_XMM0);
+ return X86_64ManagedRegister::FromXmmRegister(XMM0);
} else if (shorty[0] == 'J') {
return X86_64ManagedRegister::FromCpuRegister(RAX);
} else if (shorty[0] == 'V') {
@@ -89,7 +89,7 @@
} else if (itr_float_and_doubles_ < 8) {
// First eight float parameters are passed via XMM0..XMM7
res = X86_64ManagedRegister::FromXmmRegister(
- static_cast<XmmRegister>(_XMM0 + itr_float_and_doubles_));
+ static_cast<FloatRegister>(XMM0 + itr_float_and_doubles_));
}
return res;
}
@@ -171,15 +171,15 @@
} else if (itr_float_and_doubles_ < 8) {
// First eight float parameters are passed via XMM0..XMM7
res = X86_64ManagedRegister::FromXmmRegister(
- static_cast<XmmRegister>(_XMM0 + itr_float_and_doubles_));
+ static_cast<FloatRegister>(XMM0 + itr_float_and_doubles_));
}
return res;
}
FrameOffset X86_64JniCallingConvention::CurrentParamStackOffset() {
size_t offset = itr_args_
- - std::min(8U, itr_float_and_doubles_) // Float arguments passed through Xmm0..Xmm7
- - std::min(6U, itr_args_ - itr_float_and_doubles_); // Integer arguments passed through GPR
+ - std::min(8U, itr_float_and_doubles_) // Float arguments passed through Xmm0..Xmm7
+ - std::min(6U, itr_args_ - itr_float_and_doubles_); // Integer arguments passed through GPR
return FrameOffset(displacement_.Int32Value() - OutArgSize() + (offset * kPointerSize));
}
diff --git a/compiler/trampolines/trampoline_compiler.cc b/compiler/trampolines/trampoline_compiler.cc
index 32980cb..fb909a8 100644
--- a/compiler/trampolines/trampoline_compiler.cc
+++ b/compiler/trampolines/trampoline_compiler.cc
@@ -21,6 +21,7 @@
#include "utils/arm64/assembler_arm64.h"
#include "utils/mips/assembler_mips.h"
#include "utils/x86/assembler_x86.h"
+#include "utils/x86_64/assembler_x86_64.h"
#define __ assembler->
@@ -28,7 +29,7 @@
namespace arm {
static const std::vector<uint8_t>* CreateTrampoline(EntryPointCallingConvention abi,
- ThreadOffset offset) {
+ ThreadOffset<4> offset) {
UniquePtr<ArmAssembler> assembler(static_cast<ArmAssembler*>(Assembler::Create(kArm)));
switch (abi) {
@@ -56,7 +57,7 @@
namespace arm64 {
static const std::vector<uint8_t>* CreateTrampoline(EntryPointCallingConvention abi,
- ThreadOffset offset) {
+ ThreadOffset<8> offset) {
UniquePtr<Arm64Assembler> assembler(static_cast<Arm64Assembler*>(Assembler::Create(kArm64)));
switch (abi) {
@@ -96,7 +97,7 @@
namespace mips {
static const std::vector<uint8_t>* CreateTrampoline(EntryPointCallingConvention abi,
- ThreadOffset offset) {
+ ThreadOffset<4> offset) {
UniquePtr<MipsAssembler> assembler(static_cast<MipsAssembler*>(Assembler::Create(kMips)));
switch (abi) {
@@ -125,7 +126,7 @@
} // namespace mips
namespace x86 {
-static const std::vector<uint8_t>* CreateTrampoline(ThreadOffset offset) {
+static const std::vector<uint8_t>* CreateTrampoline(ThreadOffset<4> offset) {
UniquePtr<X86Assembler> assembler(static_cast<X86Assembler*>(Assembler::Create(kX86)));
// All x86 trampolines call via the Thread* held in fs.
@@ -142,11 +143,12 @@
} // namespace x86
namespace x86_64 {
-static const std::vector<uint8_t>* CreateTrampoline(ThreadOffset offset) {
- UniquePtr<x86::X86Assembler> assembler(static_cast<x86::X86Assembler*>(Assembler::Create(kX86_64)));
+static const std::vector<uint8_t>* CreateTrampoline(ThreadOffset<8> offset) {
+ UniquePtr<x86_64::X86_64Assembler>
+ assembler(static_cast<x86_64::X86_64Assembler*>(Assembler::Create(kX86_64)));
// All x86 trampolines call via the Thread* held in gs.
- __ gs()->jmp(x86::Address::Absolute(offset, true));
+ __ gs()->jmp(x86_64::Address::Absolute(offset, true));
__ int3();
size_t cs = assembler->CodeSize();
@@ -158,23 +160,32 @@
}
} // namespace x86_64
-const std::vector<uint8_t>* CreateTrampoline(InstructionSet isa, EntryPointCallingConvention abi,
- ThreadOffset offset) {
+const std::vector<uint8_t>* CreateTrampoline64(InstructionSet isa, EntryPointCallingConvention abi,
+ ThreadOffset<8> offset) {
+ switch (isa) {
+ case kArm64:
+ return arm64::CreateTrampoline(abi, offset);
+ case kX86_64:
+ return x86_64::CreateTrampoline(offset);
+ default:
+ LOG(FATAL) << "Unexpected InstructionSet: " << isa;
+ return nullptr;
+ }
+}
+
+const std::vector<uint8_t>* CreateTrampoline32(InstructionSet isa, EntryPointCallingConvention abi,
+ ThreadOffset<4> offset) {
switch (isa) {
case kArm:
case kThumb2:
return arm::CreateTrampoline(abi, offset);
- case kArm64:
- return arm64::CreateTrampoline(abi, offset);
case kMips:
return mips::CreateTrampoline(abi, offset);
case kX86:
return x86::CreateTrampoline(offset);
- case kX86_64:
- return x86_64::CreateTrampoline(offset);
default:
- LOG(FATAL) << "Unknown InstructionSet: " << isa;
- return NULL;
+ LOG(FATAL) << "Unexpected InstructionSet: " << isa;
+ return nullptr;
}
}
diff --git a/compiler/trampolines/trampoline_compiler.h b/compiler/trampolines/trampoline_compiler.h
index cb5aa27..bdab279 100644
--- a/compiler/trampolines/trampoline_compiler.h
+++ b/compiler/trampolines/trampoline_compiler.h
@@ -25,8 +25,11 @@
namespace art {
// Create code that will invoke the function held in thread local storage.
-const std::vector<uint8_t>* CreateTrampoline(InstructionSet isa, EntryPointCallingConvention abi,
- ThreadOffset entry_point_offset)
+const std::vector<uint8_t>* CreateTrampoline32(InstructionSet isa, EntryPointCallingConvention abi,
+ ThreadOffset<4> entry_point_offset)
+ SHARED_LOCKS_REQUIRED(Locks::mutator_lock_);
+const std::vector<uint8_t>* CreateTrampoline64(InstructionSet isa, EntryPointCallingConvention abi,
+ ThreadOffset<8> entry_point_offset)
SHARED_LOCKS_REQUIRED(Locks::mutator_lock_);
} // namespace art
diff --git a/compiler/utils/arm/assembler_arm.cc b/compiler/utils/arm/assembler_arm.cc
index 872a557..59eb98e 100644
--- a/compiler/utils/arm/assembler_arm.cc
+++ b/compiler/utils/arm/assembler_arm.cc
@@ -1577,7 +1577,7 @@
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
}
-void ArmAssembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
+void ArmAssembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm,
ManagedRegister mscratch) {
ArmManagedRegister scratch = mscratch.AsArm();
CHECK(scratch.IsCoreRegister()) << scratch;
@@ -1609,18 +1609,18 @@
return EmitLoad(this, m_dst, SP, src.Int32Value(), size);
}
-void ArmAssembler::Load(ManagedRegister m_dst, ThreadOffset src, size_t size) {
+void ArmAssembler::LoadFromThread32(ManagedRegister m_dst, ThreadOffset<4> src, size_t size) {
return EmitLoad(this, m_dst, TR, src.Int32Value(), size);
}
-void ArmAssembler::LoadRawPtrFromThread(ManagedRegister m_dst, ThreadOffset offs) {
+void ArmAssembler::LoadRawPtrFromThread32(ManagedRegister m_dst, ThreadOffset<4> offs) {
ArmManagedRegister dst = m_dst.AsArm();
CHECK(dst.IsCoreRegister()) << dst;
LoadFromOffset(kLoadWord, dst.AsCoreRegister(), TR, offs.Int32Value());
}
-void ArmAssembler::CopyRawPtrFromThread(FrameOffset fr_offs,
- ThreadOffset thr_offs,
+void ArmAssembler::CopyRawPtrFromThread32(FrameOffset fr_offs,
+ ThreadOffset<4> thr_offs,
ManagedRegister mscratch) {
ArmManagedRegister scratch = mscratch.AsArm();
CHECK(scratch.IsCoreRegister()) << scratch;
@@ -1630,7 +1630,7 @@
SP, fr_offs.Int32Value());
}
-void ArmAssembler::CopyRawPtrToThread(ThreadOffset thr_offs,
+void ArmAssembler::CopyRawPtrToThread32(ThreadOffset<4> thr_offs,
FrameOffset fr_offs,
ManagedRegister mscratch) {
ArmManagedRegister scratch = mscratch.AsArm();
@@ -1641,7 +1641,7 @@
TR, thr_offs.Int32Value());
}
-void ArmAssembler::StoreStackOffsetToThread(ThreadOffset thr_offs,
+void ArmAssembler::StoreStackOffsetToThread32(ThreadOffset<4> thr_offs,
FrameOffset fr_offs,
ManagedRegister mscratch) {
ArmManagedRegister scratch = mscratch.AsArm();
@@ -1651,7 +1651,7 @@
TR, thr_offs.Int32Value());
}
-void ArmAssembler::StoreStackPointerToThread(ThreadOffset thr_offs) {
+void ArmAssembler::StoreStackPointerToThread32(ThreadOffset<4> thr_offs) {
StoreToOffset(kStoreWord, SP, TR, thr_offs.Int32Value());
}
@@ -1844,7 +1844,7 @@
// TODO: place reference map on call
}
-void ArmAssembler::Call(ThreadOffset /*offset*/, ManagedRegister /*scratch*/) {
+void ArmAssembler::CallFromThread32(ThreadOffset<4> /*offset*/, ManagedRegister /*scratch*/) {
UNIMPLEMENTED(FATAL);
}
@@ -1862,7 +1862,7 @@
ArmExceptionSlowPath* slow = new ArmExceptionSlowPath(scratch, stack_adjust);
buffer_.EnqueueSlowPath(slow);
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
- TR, Thread::ExceptionOffset().Int32Value());
+ TR, Thread::ExceptionOffset<4>().Int32Value());
cmp(scratch.AsCoreRegister(), ShifterOperand(0));
b(slow->Entry(), NE);
}
@@ -1878,7 +1878,7 @@
// Don't care about preserving R0 as this call won't return
__ mov(R0, ShifterOperand(scratch_.AsCoreRegister()));
// Set up call to Thread::Current()->pDeliverException
- __ LoadFromOffset(kLoadWord, R12, TR, QUICK_ENTRYPOINT_OFFSET(pDeliverException).Int32Value());
+ __ LoadFromOffset(kLoadWord, R12, TR, QUICK_ENTRYPOINT_OFFSET(4, pDeliverException).Int32Value());
__ blx(R12);
// Call never returns
__ bkpt(0);
diff --git a/compiler/utils/arm/assembler_arm.h b/compiler/utils/arm/assembler_arm.h
index bb9207c..f5be04a 100644
--- a/compiler/utils/arm/assembler_arm.h
+++ b/compiler/utils/arm/assembler_arm.h
@@ -35,6 +35,7 @@
// Data-processing operands - Uninitialized
ShifterOperand() {
type_ = -1;
+ encoding_ = 0;
}
// Data-processing operands - Immediate
@@ -210,7 +211,7 @@
};
-class ArmAssembler : public Assembler {
+class ArmAssembler FINAL : public Assembler {
public:
ArmAssembler() {}
virtual ~ArmAssembler() {}
@@ -438,127 +439,116 @@
//
// Emit code that will create an activation on the stack
- virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
- const std::vector<ManagedRegister>& callee_save_regs,
- const ManagedRegisterEntrySpills& entry_spills);
+ void BuildFrame(size_t frame_size, ManagedRegister method_reg,
+ const std::vector<ManagedRegister>& callee_save_regs,
+ const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
// Emit code that will remove an activation from the stack
- virtual void RemoveFrame(size_t frame_size,
- const std::vector<ManagedRegister>& callee_save_regs);
+ void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
+ OVERRIDE;
- virtual void IncreaseFrameSize(size_t adjust);
- virtual void DecreaseFrameSize(size_t adjust);
+ void IncreaseFrameSize(size_t adjust) OVERRIDE;
+ void DecreaseFrameSize(size_t adjust) OVERRIDE;
// Store routines
- virtual void Store(FrameOffset offs, ManagedRegister src, size_t size);
- virtual void StoreRef(FrameOffset dest, ManagedRegister src);
- virtual void StoreRawPtr(FrameOffset dest, ManagedRegister src);
+ void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE;
+ void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE;
+ void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE;
- virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
- ManagedRegister scratch);
+ void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
- virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
- ManagedRegister scratch);
+ void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister scratch)
+ OVERRIDE;
- virtual void StoreStackOffsetToThread(ThreadOffset thr_offs,
- FrameOffset fr_offs,
- ManagedRegister scratch);
+ void StoreStackOffsetToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
+ ManagedRegister scratch) OVERRIDE;
- virtual void StoreStackPointerToThread(ThreadOffset thr_offs);
+ void StoreStackPointerToThread32(ThreadOffset<4> thr_offs) OVERRIDE;
- virtual void StoreSpanning(FrameOffset dest, ManagedRegister src,
- FrameOffset in_off, ManagedRegister scratch);
+ void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
+ ManagedRegister scratch) OVERRIDE;
// Load routines
- virtual void Load(ManagedRegister dest, FrameOffset src, size_t size);
+ void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE;
- virtual void Load(ManagedRegister dest, ThreadOffset src, size_t size);
+ void LoadFromThread32(ManagedRegister dest, ThreadOffset<4> src, size_t size) OVERRIDE;
- virtual void LoadRef(ManagedRegister dest, FrameOffset src);
+ void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE;
- virtual void LoadRef(ManagedRegister dest, ManagedRegister base,
- MemberOffset offs);
+ void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE;
- virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
- Offset offs);
+ void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
- virtual void LoadRawPtrFromThread(ManagedRegister dest,
- ThreadOffset offs);
+ void LoadRawPtrFromThread32(ManagedRegister dest, ThreadOffset<4> offs) OVERRIDE;
// Copying routines
- virtual void Move(ManagedRegister dest, ManagedRegister src, size_t size);
+ void Move(ManagedRegister dest, ManagedRegister src, size_t size) OVERRIDE;
- virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
- ManagedRegister scratch);
+ void CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs,
+ ManagedRegister scratch) OVERRIDE;
- virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
- ManagedRegister scratch);
+ void CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs, ManagedRegister scratch)
+ OVERRIDE;
- virtual void CopyRef(FrameOffset dest, FrameOffset src,
- ManagedRegister scratch);
+ void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE;
- virtual void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
- ManagedRegister scratch, size_t size);
+ void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(ManagedRegister dest, Offset dest_offset,
- ManagedRegister src, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
+ ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
+ ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void MemoryBarrier(ManagedRegister scratch);
+ void MemoryBarrier(ManagedRegister scratch) OVERRIDE;
// Sign extension
- virtual void SignExtend(ManagedRegister mreg, size_t size);
+ void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Zero extension
- virtual void ZeroExtend(ManagedRegister mreg, size_t size);
+ void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Exploit fast access in managed code to Thread::Current()
- virtual void GetCurrentThread(ManagedRegister tr);
- virtual void GetCurrentThread(FrameOffset dest_offset,
- ManagedRegister scratch);
+ void GetCurrentThread(ManagedRegister tr) OVERRIDE;
+ void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE;
// Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed. in_reg holds a possibly stale reference
// that can be used to avoid loading the SIRT entry to see if the value is
// NULL.
- virtual void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
- ManagedRegister in_reg, bool null_allowed);
+ void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset, ManagedRegister in_reg,
+ bool null_allowed) OVERRIDE;
// Set up out_off to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed.
- virtual void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
- ManagedRegister scratch, bool null_allowed);
+ void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset, ManagedRegister scratch,
+ bool null_allowed) OVERRIDE;
// src holds a SIRT entry (Object**) load this into dst
- virtual void LoadReferenceFromSirt(ManagedRegister dst,
- ManagedRegister src);
+ void LoadReferenceFromSirt(ManagedRegister dst, ManagedRegister src) OVERRIDE;
// Heap::VerifyObject on src. In some cases (such as a reference to this) we
// know that src may not be null.
- virtual void VerifyObject(ManagedRegister src, bool could_be_null);
- virtual void VerifyObject(FrameOffset src, bool could_be_null);
+ void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
+ void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
// Call to address held at [base+offset]
- virtual void Call(ManagedRegister base, Offset offset,
- ManagedRegister scratch);
- virtual void Call(FrameOffset base, Offset offset,
- ManagedRegister scratch);
- virtual void Call(ThreadOffset offset, ManagedRegister scratch);
+ void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
+ void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
+ void CallFromThread32(ThreadOffset<4> offset, ManagedRegister scratch) OVERRIDE;
// Generate code to check if Thread::Current()->exception_ is non-null
// and branch to a ExceptionSlowPath if it is.
- virtual void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust);
+ void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE;
private:
void EmitType01(Condition cond,
@@ -642,12 +632,12 @@
};
// Slowpath entered when Thread::Current()->_exception is non-null
-class ArmExceptionSlowPath : public SlowPath {
+class ArmExceptionSlowPath FINAL : public SlowPath {
public:
explicit ArmExceptionSlowPath(ArmManagedRegister scratch, size_t stack_adjust)
: scratch_(scratch), stack_adjust_(stack_adjust) {
}
- virtual void Emit(Assembler *sp_asm);
+ void Emit(Assembler *sp_asm) OVERRIDE;
private:
const ArmManagedRegister scratch_;
const size_t stack_adjust_;
diff --git a/compiler/utils/arm/constants_arm.h b/compiler/utils/arm/constants_arm.h
index cc795b1..058f945 100644
--- a/compiler/utils/arm/constants_arm.h
+++ b/compiler/utils/arm/constants_arm.h
@@ -242,22 +242,22 @@
}
// Get the raw instruction bits.
- inline int32_t InstructionBits() const {
+ int32_t InstructionBits() const {
return *reinterpret_cast<const int32_t*>(this);
}
// Set the raw instruction bits to value.
- inline void SetInstructionBits(int32_t value) {
+ void SetInstructionBits(int32_t value) {
*reinterpret_cast<int32_t*>(this) = value;
}
// Read one particular bit out of the instruction bits.
- inline int Bit(int nr) const {
+ int Bit(int nr) const {
return (InstructionBits() >> nr) & 1;
}
// Read a bit field out of the instruction bits.
- inline int Bits(int shift, int count) const {
+ int Bits(int shift, int count) const {
return (InstructionBits() >> shift) & ((1 << count) - 1);
}
@@ -265,80 +265,80 @@
// Accessors for the different named fields used in the ARM encoding.
// The naming of these accessor corresponds to figure A3-1.
// Generally applicable fields
- inline Condition ConditionField() const {
+ Condition ConditionField() const {
return static_cast<Condition>(Bits(kConditionShift, kConditionBits));
}
- inline int TypeField() const { return Bits(kTypeShift, kTypeBits); }
+ int TypeField() const { return Bits(kTypeShift, kTypeBits); }
- inline Register RnField() const { return static_cast<Register>(
+ Register RnField() const { return static_cast<Register>(
Bits(kRnShift, kRnBits)); }
- inline Register RdField() const { return static_cast<Register>(
+ Register RdField() const { return static_cast<Register>(
Bits(kRdShift, kRdBits)); }
// Fields used in Data processing instructions
- inline Opcode OpcodeField() const {
+ Opcode OpcodeField() const {
return static_cast<Opcode>(Bits(kOpcodeShift, kOpcodeBits));
}
- inline int SField() const { return Bits(kSShift, kSBits); }
+ int SField() const { return Bits(kSShift, kSBits); }
// with register
- inline Register RmField() const {
+ Register RmField() const {
return static_cast<Register>(Bits(kRmShift, kRmBits));
}
- inline Shift ShiftField() const { return static_cast<Shift>(
+ Shift ShiftField() const { return static_cast<Shift>(
Bits(kShiftShift, kShiftBits)); }
- inline int RegShiftField() const { return Bit(4); }
- inline Register RsField() const {
+ int RegShiftField() const { return Bit(4); }
+ Register RsField() const {
return static_cast<Register>(Bits(kRsShift, kRsBits));
}
- inline int ShiftAmountField() const { return Bits(kShiftImmShift,
+ int ShiftAmountField() const { return Bits(kShiftImmShift,
kShiftImmBits); }
// with immediate
- inline int RotateField() const { return Bits(kRotateShift, kRotateBits); }
- inline int Immed8Field() const { return Bits(kImmed8Shift, kImmed8Bits); }
+ int RotateField() const { return Bits(kRotateShift, kRotateBits); }
+ int Immed8Field() const { return Bits(kImmed8Shift, kImmed8Bits); }
// Fields used in Load/Store instructions
- inline int PUField() const { return Bits(23, 2); }
- inline int BField() const { return Bit(22); }
- inline int WField() const { return Bit(21); }
- inline int LField() const { return Bit(20); }
+ int PUField() const { return Bits(23, 2); }
+ int BField() const { return Bit(22); }
+ int WField() const { return Bit(21); }
+ int LField() const { return Bit(20); }
// with register uses same fields as Data processing instructions above
// with immediate
- inline int Offset12Field() const { return Bits(kOffset12Shift,
+ int Offset12Field() const { return Bits(kOffset12Shift,
kOffset12Bits); }
// multiple
- inline int RlistField() const { return Bits(0, 16); }
+ int RlistField() const { return Bits(0, 16); }
// extra loads and stores
- inline int SignField() const { return Bit(6); }
- inline int HField() const { return Bit(5); }
- inline int ImmedHField() const { return Bits(8, 4); }
- inline int ImmedLField() const { return Bits(0, 4); }
+ int SignField() const { return Bit(6); }
+ int HField() const { return Bit(5); }
+ int ImmedHField() const { return Bits(8, 4); }
+ int ImmedLField() const { return Bits(0, 4); }
// Fields used in Branch instructions
- inline int LinkField() const { return Bits(kLinkShift, kLinkBits); }
- inline int SImmed24Field() const { return ((InstructionBits() << 8) >> 8); }
+ int LinkField() const { return Bits(kLinkShift, kLinkBits); }
+ int SImmed24Field() const { return ((InstructionBits() << 8) >> 8); }
// Fields used in Supervisor Call instructions
- inline uint32_t SvcField() const { return Bits(0, 24); }
+ uint32_t SvcField() const { return Bits(0, 24); }
// Field used in Breakpoint instruction
- inline uint16_t BkptField() const {
+ uint16_t BkptField() const {
return ((Bits(8, 12) << 4) | Bits(0, 4));
}
// Field used in 16-bit immediate move instructions
- inline uint16_t MovwField() const {
+ uint16_t MovwField() const {
return ((Bits(16, 4) << 12) | Bits(0, 12));
}
// Field used in VFP float immediate move instruction
- inline float ImmFloatField() const {
+ float ImmFloatField() const {
uint32_t imm32 = (Bit(19) << 31) | (((1 << 5) - Bit(18)) << 25) |
(Bits(16, 2) << 23) | (Bits(0, 4) << 19);
return bit_cast<float, uint32_t>(imm32);
}
// Field used in VFP double immediate move instruction
- inline double ImmDoubleField() const {
+ double ImmDoubleField() const {
uint64_t imm64 = (Bit(19)*(1LL << 63)) | (((1LL << 8) - Bit(18)) << 54) |
(Bits(16, 2)*(1LL << 52)) | (Bits(0, 4)*(1LL << 48));
return bit_cast<double, uint64_t>(imm64);
@@ -347,7 +347,7 @@
// Test for data processing instructions of type 0 or 1.
// See "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition",
// section A5.1 "ARM instruction set encoding".
- inline bool IsDataProcessing() const {
+ bool IsDataProcessing() const {
CHECK_NE(ConditionField(), kSpecialCondition);
CHECK_EQ(Bits(26, 2), 0); // Type 0 or 1.
return ((Bits(20, 5) & 0x19) != 0x10) &&
@@ -359,47 +359,47 @@
// Tests for special encodings of type 0 instructions (extra loads and stores,
// as well as multiplications, synchronization primitives, and miscellaneous).
// Can only be called for a type 0 or 1 instruction.
- inline bool IsMiscellaneous() const {
+ bool IsMiscellaneous() const {
CHECK_EQ(Bits(26, 2), 0); // Type 0 or 1.
return ((Bit(25) == 0) && ((Bits(20, 5) & 0x19) == 0x10) && (Bit(7) == 0));
}
- inline bool IsMultiplyOrSyncPrimitive() const {
+ bool IsMultiplyOrSyncPrimitive() const {
CHECK_EQ(Bits(26, 2), 0); // Type 0 or 1.
return ((Bit(25) == 0) && (Bits(4, 4) == 9));
}
// Test for Supervisor Call instruction.
- inline bool IsSvc() const {
+ bool IsSvc() const {
return ((InstructionBits() & 0xff000000) == 0xef000000);
}
// Test for Breakpoint instruction.
- inline bool IsBkpt() const {
+ bool IsBkpt() const {
return ((InstructionBits() & 0xfff000f0) == 0xe1200070);
}
// VFP register fields.
- inline SRegister SnField() const {
+ SRegister SnField() const {
return static_cast<SRegister>((Bits(kRnShift, kRnBits) << 1) + Bit(7));
}
- inline SRegister SdField() const {
+ SRegister SdField() const {
return static_cast<SRegister>((Bits(kRdShift, kRdBits) << 1) + Bit(22));
}
- inline SRegister SmField() const {
+ SRegister SmField() const {
return static_cast<SRegister>((Bits(kRmShift, kRmBits) << 1) + Bit(5));
}
- inline DRegister DnField() const {
+ DRegister DnField() const {
return static_cast<DRegister>(Bits(kRnShift, kRnBits) + (Bit(7) << 4));
}
- inline DRegister DdField() const {
+ DRegister DdField() const {
return static_cast<DRegister>(Bits(kRdShift, kRdBits) + (Bit(22) << 4));
}
- inline DRegister DmField() const {
+ DRegister DmField() const {
return static_cast<DRegister>(Bits(kRmShift, kRmBits) + (Bit(5) << 4));
}
// Test for VFP data processing or single transfer instructions of type 7.
- inline bool IsVFPDataProcessingOrSingleTransfer() const {
+ bool IsVFPDataProcessingOrSingleTransfer() const {
CHECK_NE(ConditionField(), kSpecialCondition);
CHECK_EQ(TypeField(), 7);
return ((Bit(24) == 0) && (Bits(9, 3) == 5));
@@ -408,7 +408,7 @@
}
// Test for VFP 64-bit transfer instructions of type 6.
- inline bool IsVFPDoubleTransfer() const {
+ bool IsVFPDoubleTransfer() const {
CHECK_NE(ConditionField(), kSpecialCondition);
CHECK_EQ(TypeField(), 6);
return ((Bits(21, 4) == 2) && (Bits(9, 3) == 5) &&
@@ -416,20 +416,20 @@
}
// Test for VFP load and store instructions of type 6.
- inline bool IsVFPLoadStore() const {
+ bool IsVFPLoadStore() const {
CHECK_NE(ConditionField(), kSpecialCondition);
CHECK_EQ(TypeField(), 6);
return ((Bits(20, 5) & 0x12) == 0x10) && (Bits(9, 3) == 5);
}
// Special accessors that test for existence of a value.
- inline bool HasS() const { return SField() == 1; }
- inline bool HasB() const { return BField() == 1; }
- inline bool HasW() const { return WField() == 1; }
- inline bool HasL() const { return LField() == 1; }
- inline bool HasSign() const { return SignField() == 1; }
- inline bool HasH() const { return HField() == 1; }
- inline bool HasLink() const { return LinkField() == 1; }
+ bool HasS() const { return SField() == 1; }
+ bool HasB() const { return BField() == 1; }
+ bool HasW() const { return WField() == 1; }
+ bool HasL() const { return LField() == 1; }
+ bool HasSign() const { return SignField() == 1; }
+ bool HasH() const { return HField() == 1; }
+ bool HasLink() const { return LinkField() == 1; }
// Instructions are read out of a code stream. The only way to get a
// reference to an instruction is to convert a pointer. There is no way
diff --git a/compiler/utils/arm64/assembler_arm64.cc b/compiler/utils/arm64/assembler_arm64.cc
index f8b91d7..5b2c8ba 100644
--- a/compiler/utils/arm64/assembler_arm64.cc
+++ b/compiler/utils/arm64/assembler_arm64.cc
@@ -155,7 +155,7 @@
StoreToOffset(scratch.AsCoreRegister(), SP, offs.Int32Value());
}
-void Arm64Assembler::StoreImmediateToThread(ThreadOffset offs, uint32_t imm,
+void Arm64Assembler::StoreImmediateToThread32(ThreadOffset<4> offs, uint32_t imm,
ManagedRegister m_scratch) {
Arm64ManagedRegister scratch = m_scratch.AsArm64();
CHECK(scratch.IsCoreRegister()) << scratch;
@@ -163,7 +163,7 @@
StoreToOffset(scratch.AsCoreRegister(), TR, offs.Int32Value());
}
-void Arm64Assembler::StoreStackOffsetToThread(ThreadOffset tr_offs,
+void Arm64Assembler::StoreStackOffsetToThread32(ThreadOffset<4> tr_offs,
FrameOffset fr_offs,
ManagedRegister m_scratch) {
Arm64ManagedRegister scratch = m_scratch.AsArm64();
@@ -172,7 +172,7 @@
StoreToOffset(scratch.AsCoreRegister(), TR, tr_offs.Int32Value());
}
-void Arm64Assembler::StoreStackPointerToThread(ThreadOffset tr_offs) {
+void Arm64Assembler::StoreStackPointerToThread32(ThreadOffset<4> tr_offs) {
// Arm64 does not support: "str sp, [dest]" therefore we use IP1 as a temp reg.
___ Mov(reg_x(IP1), reg_x(SP));
StoreToOffset(IP1, TR, tr_offs.Int32Value());
@@ -269,7 +269,7 @@
return Load(m_dst.AsArm64(), SP, src.Int32Value(), size);
}
-void Arm64Assembler::Load(ManagedRegister m_dst, ThreadOffset src, size_t size) {
+void Arm64Assembler::LoadFromThread32(ManagedRegister m_dst, ThreadOffset<4> src, size_t size) {
return Load(m_dst.AsArm64(), TR, src.Int32Value(), size);
}
@@ -294,7 +294,7 @@
LoadFromOffset(dst.AsCoreRegister(), base.AsCoreRegister(), offs.Int32Value());
}
-void Arm64Assembler::LoadRawPtrFromThread(ManagedRegister m_dst, ThreadOffset offs) {
+void Arm64Assembler::LoadRawPtrFromThread32(ManagedRegister m_dst, ThreadOffset<4> offs) {
Arm64ManagedRegister dst = m_dst.AsArm64();
CHECK(dst.IsCoreRegister()) << dst;
LoadFromOffset(dst.AsCoreRegister(), TR, offs.Int32Value());
@@ -322,8 +322,8 @@
}
}
-void Arm64Assembler::CopyRawPtrFromThread(FrameOffset fr_offs,
- ThreadOffset tr_offs,
+void Arm64Assembler::CopyRawPtrFromThread32(FrameOffset fr_offs,
+ ThreadOffset<4> tr_offs,
ManagedRegister m_scratch) {
Arm64ManagedRegister scratch = m_scratch.AsArm64();
CHECK(scratch.IsCoreRegister()) << scratch;
@@ -331,7 +331,7 @@
StoreToOffset(scratch.AsCoreRegister(), SP, fr_offs.Int32Value());
}
-void Arm64Assembler::CopyRawPtrToThread(ThreadOffset tr_offs,
+void Arm64Assembler::CopyRawPtrToThread32(ThreadOffset<4> tr_offs,
FrameOffset fr_offs,
ManagedRegister m_scratch) {
Arm64ManagedRegister scratch = m_scratch.AsArm64();
@@ -486,7 +486,7 @@
___ Blr(reg_x(scratch.AsCoreRegister()));
}
-void Arm64Assembler::Call(ThreadOffset /*offset*/, ManagedRegister /*scratch*/) {
+void Arm64Assembler::CallFromThread32(ThreadOffset<4> /*offset*/, ManagedRegister /*scratch*/) {
UNIMPLEMENTED(FATAL) << "Unimplemented Call() variant";
}
@@ -555,7 +555,7 @@
Arm64ManagedRegister scratch = m_scratch.AsArm64();
Arm64Exception *current_exception = new Arm64Exception(scratch, stack_adjust);
exception_blocks_.push_back(current_exception);
- LoadFromOffset(scratch.AsCoreRegister(), TR, Thread::ExceptionOffset().Int32Value());
+ LoadFromOffset(scratch.AsCoreRegister(), TR, Thread::ExceptionOffset<4>().Int32Value());
___ Cmp(reg_x(scratch.AsCoreRegister()), 0);
___ B(current_exception->Entry(), COND_OP(NE));
}
@@ -569,7 +569,7 @@
// Pass exception object as argument.
// Don't care about preserving X0 as this won't return.
___ Mov(reg_x(X0), reg_x(exception->scratch_.AsCoreRegister()));
- LoadFromOffset(IP1, TR, QUICK_ENTRYPOINT_OFFSET(pDeliverException).Int32Value());
+ LoadFromOffset(IP1, TR, QUICK_ENTRYPOINT_OFFSET(8, pDeliverException).Int32Value());
___ Blr(reg_x(IP1));
// Call should never return.
___ Brk();
diff --git a/compiler/utils/arm64/assembler_arm64.h b/compiler/utils/arm64/assembler_arm64.h
index 44eb6ff..3abcaad 100644
--- a/compiler/utils/arm64/assembler_arm64.h
+++ b/compiler/utils/arm64/assembler_arm64.h
@@ -79,7 +79,7 @@
class Arm64Exception;
-class Arm64Assembler : public Assembler {
+class Arm64Assembler FINAL : public Assembler {
public:
Arm64Assembler() : vixl_buf_(new byte[BUF_SIZE]),
vixl_masm_(new vixl::MacroAssembler(vixl_buf_, BUF_SIZE)) {}
@@ -111,105 +111,97 @@
// Emit code that will create an activation on the stack.
void BuildFrame(size_t frame_size, ManagedRegister method_reg,
const std::vector<ManagedRegister>& callee_save_regs,
- const ManagedRegisterEntrySpills& entry_spills);
+ const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
// Emit code that will remove an activation from the stack.
- void RemoveFrame(size_t frame_size,
- const std::vector<ManagedRegister>& callee_save_regs);
+ void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
+ OVERRIDE;
- void IncreaseFrameSize(size_t adjust);
- void DecreaseFrameSize(size_t adjust);
+ void IncreaseFrameSize(size_t adjust) OVERRIDE;
+ void DecreaseFrameSize(size_t adjust) OVERRIDE;
// Store routines.
- void Store(FrameOffset offs, ManagedRegister src, size_t size);
- void StoreRef(FrameOffset dest, ManagedRegister src);
- void StoreRawPtr(FrameOffset dest, ManagedRegister src);
- void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
- ManagedRegister scratch);
- void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
- ManagedRegister scratch);
- void StoreStackOffsetToThread(ThreadOffset thr_offs,
- FrameOffset fr_offs,
- ManagedRegister scratch);
- void StoreStackPointerToThread(ThreadOffset thr_offs);
- void StoreSpanning(FrameOffset dest, ManagedRegister src,
- FrameOffset in_off, ManagedRegister scratch);
+ void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE;
+ void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE;
+ void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE;
+ void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
+ void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister scratch)
+ OVERRIDE;
+ void StoreStackOffsetToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
+ ManagedRegister scratch) OVERRIDE;
+ void StoreStackPointerToThread32(ThreadOffset<4> thr_offs) OVERRIDE;
+ void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
+ ManagedRegister scratch) OVERRIDE;
// Load routines.
- void Load(ManagedRegister dest, FrameOffset src, size_t size);
- void Load(ManagedRegister dest, ThreadOffset src, size_t size);
- void LoadRef(ManagedRegister dest, FrameOffset src);
- void LoadRef(ManagedRegister dest, ManagedRegister base,
- MemberOffset offs);
- void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
- Offset offs);
- void LoadRawPtrFromThread(ManagedRegister dest,
- ThreadOffset offs);
+ void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE;
+ void LoadFromThread32(ManagedRegister dest, ThreadOffset<4> src, size_t size) OVERRIDE;
+ void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE;
+ void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE;
+ void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
+ void LoadRawPtrFromThread32(ManagedRegister dest, ThreadOffset<4> offs) OVERRIDE;
+
// Copying routines.
- void Move(ManagedRegister dest, ManagedRegister src, size_t size);
- void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
- ManagedRegister scratch);
- void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
- ManagedRegister scratch);
- void CopyRef(FrameOffset dest, FrameOffset src,
- ManagedRegister scratch);
- void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size);
- void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
- ManagedRegister scratch, size_t size);
- void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
- ManagedRegister scratch, size_t size);
- void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
- ManagedRegister scratch, size_t size);
- void Copy(ManagedRegister dest, Offset dest_offset,
- ManagedRegister src, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Move(ManagedRegister dest, ManagedRegister src, size_t size) OVERRIDE;
+ void CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs,
+ ManagedRegister scratch) OVERRIDE;
+ void CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs, ManagedRegister scratch)
+ OVERRIDE;
+ void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE;
+ void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE;
+ void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch,
+ size_t size) OVERRIDE;
+ void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch,
+ size_t size) OVERRIDE;
+ void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch,
+ size_t size) OVERRIDE;
+ void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
+ ManagedRegister scratch, size_t size) OVERRIDE;
void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
- ManagedRegister scratch, size_t size);
- void MemoryBarrier(ManagedRegister scratch);
+ ManagedRegister scratch, size_t size) OVERRIDE;
+ void MemoryBarrier(ManagedRegister scratch) OVERRIDE;
// Sign extension.
- void SignExtend(ManagedRegister mreg, size_t size);
+ void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Zero extension.
- void ZeroExtend(ManagedRegister mreg, size_t size);
+ void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Exploit fast access in managed code to Thread::Current().
- void GetCurrentThread(ManagedRegister tr);
- void GetCurrentThread(FrameOffset dest_offset,
- ManagedRegister scratch);
+ void GetCurrentThread(ManagedRegister tr) OVERRIDE;
+ void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE;
// Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed. in_reg holds a possibly stale reference
// that can be used to avoid loading the SIRT entry to see if the value is
// NULL.
void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
- ManagedRegister in_reg, bool null_allowed);
+ ManagedRegister in_reg, bool null_allowed) OVERRIDE;
// Set up out_off to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed.
void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
- ManagedRegister scratch, bool null_allowed);
+ ManagedRegister scratch, bool null_allowed) OVERRIDE;
// src holds a SIRT entry (Object**) load this into dst.
- void LoadReferenceFromSirt(ManagedRegister dst,
- ManagedRegister src);
+ void LoadReferenceFromSirt(ManagedRegister dst, ManagedRegister src) OVERRIDE;
// Heap::VerifyObject on src. In some cases (such as a reference to this) we
// know that src may not be null.
- void VerifyObject(ManagedRegister src, bool could_be_null);
- void VerifyObject(FrameOffset src, bool could_be_null);
+ void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
+ void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
// Call to address held at [base+offset].
- void Call(ManagedRegister base, Offset offset, ManagedRegister scratch);
- void Call(FrameOffset base, Offset offset, ManagedRegister scratch);
- void Call(ThreadOffset offset, ManagedRegister scratch);
+ void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
+ void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
+ void CallFromThread32(ThreadOffset<4> offset, ManagedRegister scratch) OVERRIDE;
// Jump to address (not setting link register)
void JumpTo(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch);
// Generate code to check if Thread::Current()->exception_ is non-null
// and branch to a ExceptionSlowPath if it is.
- void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust);
+ void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE;
private:
static vixl::Register reg_x(int code) {
diff --git a/compiler/utils/arm64/constants_arm64.h b/compiler/utils/arm64/constants_arm64.h
index c05c2f1..ecf9fbe 100644
--- a/compiler/utils/arm64/constants_arm64.h
+++ b/compiler/utils/arm64/constants_arm64.h
@@ -29,7 +29,7 @@
namespace art {
namespace arm64 {
- constexpr unsigned int kCalleeSavedRegsSize = 20;
+constexpr unsigned int kCalleeSavedRegsSize = 20;
} // arm64
} // art
diff --git a/compiler/utils/assembler.cc b/compiler/utils/assembler.cc
index 1921b28..26bdceb 100644
--- a/compiler/utils/assembler.cc
+++ b/compiler/utils/assembler.cc
@@ -122,4 +122,78 @@
}
}
+void Assembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm,
+ ManagedRegister scratch) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm,
+ ManagedRegister scratch) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::StoreStackOffsetToThread32(ThreadOffset<4> thr_offs,
+ FrameOffset fr_offs,
+ ManagedRegister scratch) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::StoreStackOffsetToThread64(ThreadOffset<8> thr_offs,
+ FrameOffset fr_offs,
+ ManagedRegister scratch) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::StoreStackPointerToThread32(ThreadOffset<4> thr_offs) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::StoreStackPointerToThread64(ThreadOffset<8> thr_offs) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::LoadFromThread32(ManagedRegister dest, ThreadOffset<4> src, size_t size) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::LoadFromThread64(ManagedRegister dest, ThreadOffset<8> src, size_t size) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::LoadRawPtrFromThread32(ManagedRegister dest, ThreadOffset<4> offs) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::LoadRawPtrFromThread64(ManagedRegister dest, ThreadOffset<8> offs) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs,
+ ManagedRegister scratch) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::CopyRawPtrFromThread64(FrameOffset fr_offs, ThreadOffset<8> thr_offs,
+ ManagedRegister scratch) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
+ ManagedRegister scratch) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::CopyRawPtrToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs,
+ ManagedRegister scratch) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::CallFromThread32(ThreadOffset<4> offset, ManagedRegister scratch) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void Assembler::CallFromThread64(ThreadOffset<8> offset, ManagedRegister scratch) {
+ UNIMPLEMENTED(FATAL);
+}
+
} // namespace art
diff --git a/compiler/utils/assembler.h b/compiler/utils/assembler.h
index c23fd44..219c87f 100644
--- a/compiler/utils/assembler.h
+++ b/compiler/utils/assembler.h
@@ -374,14 +374,20 @@
virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
ManagedRegister scratch) = 0;
- virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
- ManagedRegister scratch) = 0;
+ virtual void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm,
+ ManagedRegister scratch);
+ virtual void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm,
+ ManagedRegister scratch);
- virtual void StoreStackOffsetToThread(ThreadOffset thr_offs,
- FrameOffset fr_offs,
- ManagedRegister scratch) = 0;
+ virtual void StoreStackOffsetToThread32(ThreadOffset<4> thr_offs,
+ FrameOffset fr_offs,
+ ManagedRegister scratch);
+ virtual void StoreStackOffsetToThread64(ThreadOffset<8> thr_offs,
+ FrameOffset fr_offs,
+ ManagedRegister scratch);
- virtual void StoreStackPointerToThread(ThreadOffset thr_offs) = 0;
+ virtual void StoreStackPointerToThread32(ThreadOffset<4> thr_offs);
+ virtual void StoreStackPointerToThread64(ThreadOffset<8> thr_offs);
virtual void StoreSpanning(FrameOffset dest, ManagedRegister src,
FrameOffset in_off, ManagedRegister scratch) = 0;
@@ -389,27 +395,29 @@
// Load routines
virtual void Load(ManagedRegister dest, FrameOffset src, size_t size) = 0;
- virtual void Load(ManagedRegister dest, ThreadOffset src, size_t size) = 0;
+ virtual void LoadFromThread32(ManagedRegister dest, ThreadOffset<4> src, size_t size);
+ virtual void LoadFromThread64(ManagedRegister dest, ThreadOffset<8> src, size_t size);
virtual void LoadRef(ManagedRegister dest, FrameOffset src) = 0;
+ virtual void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) = 0;
- virtual void LoadRef(ManagedRegister dest, ManagedRegister base,
- MemberOffset offs) = 0;
+ virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) = 0;
- virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
- Offset offs) = 0;
-
- virtual void LoadRawPtrFromThread(ManagedRegister dest,
- ThreadOffset offs) = 0;
+ virtual void LoadRawPtrFromThread32(ManagedRegister dest, ThreadOffset<4> offs);
+ virtual void LoadRawPtrFromThread64(ManagedRegister dest, ThreadOffset<8> offs);
// Copying routines
virtual void Move(ManagedRegister dest, ManagedRegister src, size_t size) = 0;
- virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
- ManagedRegister scratch) = 0;
+ virtual void CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs,
+ ManagedRegister scratch);
+ virtual void CopyRawPtrFromThread64(FrameOffset fr_offs, ThreadOffset<8> thr_offs,
+ ManagedRegister scratch);
- virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
- ManagedRegister scratch) = 0;
+ virtual void CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
+ ManagedRegister scratch);
+ virtual void CopyRawPtrToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs,
+ ManagedRegister scratch);
virtual void CopyRef(FrameOffset dest, FrameOffset src,
ManagedRegister scratch) = 0;
@@ -471,7 +479,8 @@
ManagedRegister scratch) = 0;
virtual void Call(FrameOffset base, Offset offset,
ManagedRegister scratch) = 0;
- virtual void Call(ThreadOffset offset, ManagedRegister scratch) = 0;
+ virtual void CallFromThread32(ThreadOffset<4> offset, ManagedRegister scratch);
+ virtual void CallFromThread64(ThreadOffset<8> offset, ManagedRegister scratch);
// Generate code to check if Thread::Current()->exception_ is non-null
// and branch to a ExceptionSlowPath if it is.
diff --git a/compiler/utils/mips/assembler_mips.cc b/compiler/utils/mips/assembler_mips.cc
index dfd3306..99c29f1 100644
--- a/compiler/utils/mips/assembler_mips.cc
+++ b/compiler/utils/mips/assembler_mips.cc
@@ -633,7 +633,7 @@
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
}
-void MipsAssembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
+void MipsAssembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm,
ManagedRegister mscratch) {
MipsManagedRegister scratch = mscratch.AsMips();
CHECK(scratch.IsCoreRegister()) << scratch;
@@ -641,7 +641,7 @@
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S1, dest.Int32Value());
}
-void MipsAssembler::StoreStackOffsetToThread(ThreadOffset thr_offs,
+void MipsAssembler::StoreStackOffsetToThread32(ThreadOffset<4> thr_offs,
FrameOffset fr_offs,
ManagedRegister mscratch) {
MipsManagedRegister scratch = mscratch.AsMips();
@@ -651,7 +651,7 @@
S1, thr_offs.Int32Value());
}
-void MipsAssembler::StoreStackPointerToThread(ThreadOffset thr_offs) {
+void MipsAssembler::StoreStackPointerToThread32(ThreadOffset<4> thr_offs) {
StoreToOffset(kStoreWord, SP, S1, thr_offs.Int32Value());
}
@@ -668,7 +668,7 @@
return EmitLoad(mdest, SP, src.Int32Value(), size);
}
-void MipsAssembler::Load(ManagedRegister mdest, ThreadOffset src, size_t size) {
+void MipsAssembler::LoadFromThread32(ManagedRegister mdest, ThreadOffset<4> src, size_t size) {
return EmitLoad(mdest, S1, src.Int32Value(), size);
}
@@ -697,8 +697,8 @@
base.AsMips().AsCoreRegister(), offs.Int32Value());
}
-void MipsAssembler::LoadRawPtrFromThread(ManagedRegister mdest,
- ThreadOffset offs) {
+void MipsAssembler::LoadRawPtrFromThread32(ManagedRegister mdest,
+ ThreadOffset<4> offs) {
MipsManagedRegister dest = mdest.AsMips();
CHECK(dest.IsCoreRegister());
LoadFromOffset(kLoadWord, dest.AsCoreRegister(), S1, offs.Int32Value());
@@ -748,8 +748,8 @@
StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value());
}
-void MipsAssembler::CopyRawPtrFromThread(FrameOffset fr_offs,
- ThreadOffset thr_offs,
+void MipsAssembler::CopyRawPtrFromThread32(FrameOffset fr_offs,
+ ThreadOffset<4> thr_offs,
ManagedRegister mscratch) {
MipsManagedRegister scratch = mscratch.AsMips();
CHECK(scratch.IsCoreRegister()) << scratch;
@@ -759,7 +759,7 @@
SP, fr_offs.Int32Value());
}
-void MipsAssembler::CopyRawPtrToThread(ThreadOffset thr_offs,
+void MipsAssembler::CopyRawPtrToThread32(ThreadOffset<4> thr_offs,
FrameOffset fr_offs,
ManagedRegister mscratch) {
MipsManagedRegister scratch = mscratch.AsMips();
@@ -923,7 +923,7 @@
// TODO: place reference map on call
}
-void MipsAssembler::Call(ThreadOffset /*offset*/, ManagedRegister /*mscratch*/) {
+void MipsAssembler::CallFromThread32(ThreadOffset<4> /*offset*/, ManagedRegister /*mscratch*/) {
UNIMPLEMENTED(FATAL) << "no mips implementation";
}
@@ -941,7 +941,7 @@
MipsExceptionSlowPath* slow = new MipsExceptionSlowPath(scratch, stack_adjust);
buffer_.EnqueueSlowPath(slow);
LoadFromOffset(kLoadWord, scratch.AsCoreRegister(),
- S1, Thread::ExceptionOffset().Int32Value());
+ S1, Thread::ExceptionOffset<4>().Int32Value());
EmitBranch(scratch.AsCoreRegister(), ZERO, slow->Entry(), false);
}
@@ -956,7 +956,7 @@
// Don't care about preserving A0 as this call won't return
__ Move(A0, scratch_.AsCoreRegister());
// Set up call to Thread::Current()->pDeliverException
- __ LoadFromOffset(kLoadWord, T9, S1, QUICK_ENTRYPOINT_OFFSET(pDeliverException).Int32Value());
+ __ LoadFromOffset(kLoadWord, T9, S1, QUICK_ENTRYPOINT_OFFSET(4, pDeliverException).Int32Value());
__ Jr(T9);
// Call never returns
__ Break();
diff --git a/compiler/utils/mips/assembler_mips.h b/compiler/utils/mips/assembler_mips.h
index 0d1a94c..75ee8b9 100644
--- a/compiler/utils/mips/assembler_mips.h
+++ b/compiler/utils/mips/assembler_mips.h
@@ -29,171 +29,6 @@
namespace art {
namespace mips {
-#if 0
-class Operand {
- public:
- uint8_t mod() const {
- return (encoding_at(0) >> 6) & 3;
- }
-
- Register rm() const {
- return static_cast<Register>(encoding_at(0) & 7);
- }
-
- ScaleFactor scale() const {
- return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
- }
-
- Register index() const {
- return static_cast<Register>((encoding_at(1) >> 3) & 7);
- }
-
- Register base() const {
- return static_cast<Register>(encoding_at(1) & 7);
- }
-
- int8_t disp8() const {
- CHECK_GE(length_, 2);
- return static_cast<int8_t>(encoding_[length_ - 1]);
- }
-
- int32_t disp32() const {
- CHECK_GE(length_, 5);
- int32_t value;
- memcpy(&value, &encoding_[length_ - 4], sizeof(value));
- return value;
- }
-
- bool IsRegister(Register reg) const {
- return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only.
- && ((encoding_[0] & 0x07) == reg); // Register codes match.
- }
-
- protected:
- // Operand can be sub classed (e.g: Address).
- Operand() : length_(0) { }
-
- void SetModRM(int mod, Register rm) {
- CHECK_EQ(mod & ~3, 0);
- encoding_[0] = (mod << 6) | rm;
- length_ = 1;
- }
-
- void SetSIB(ScaleFactor scale, Register index, Register base) {
- CHECK_EQ(length_, 1);
- CHECK_EQ(scale & ~3, 0);
- encoding_[1] = (scale << 6) | (index << 3) | base;
- length_ = 2;
- }
-
- void SetDisp8(int8_t disp) {
- CHECK(length_ == 1 || length_ == 2);
- encoding_[length_++] = static_cast<uint8_t>(disp);
- }
-
- void SetDisp32(int32_t disp) {
- CHECK(length_ == 1 || length_ == 2);
- int disp_size = sizeof(disp);
- memmove(&encoding_[length_], &disp, disp_size);
- length_ += disp_size;
- }
-
- private:
- byte length_;
- byte encoding_[6];
- byte padding_;
-
- explicit Operand(Register reg) { SetModRM(3, reg); }
-
- // Get the operand encoding byte at the given index.
- uint8_t encoding_at(int index) const {
- CHECK_GE(index, 0);
- CHECK_LT(index, length_);
- return encoding_[index];
- }
-
- friend class MipsAssembler;
-
- DISALLOW_COPY_AND_ASSIGN(Operand);
-};
-
-
-class Address : public Operand {
- public:
- Address(Register base, int32_t disp) {
- Init(base, disp);
- }
-
- Address(Register base, Offset disp) {
- Init(base, disp.Int32Value());
- }
-
- Address(Register base, FrameOffset disp) {
- CHECK_EQ(base, ESP);
- Init(ESP, disp.Int32Value());
- }
-
- Address(Register base, MemberOffset disp) {
- Init(base, disp.Int32Value());
- }
-
- void Init(Register base, int32_t disp) {
- if (disp == 0 && base != EBP) {
- SetModRM(0, base);
- if (base == ESP) SetSIB(TIMES_1, ESP, base);
- } else if (disp >= -128 && disp <= 127) {
- SetModRM(1, base);
- if (base == ESP) SetSIB(TIMES_1, ESP, base);
- SetDisp8(disp);
- } else {
- SetModRM(2, base);
- if (base == ESP) SetSIB(TIMES_1, ESP, base);
- SetDisp32(disp);
- }
- }
-
-
- Address(Register index, ScaleFactor scale, int32_t disp) {
- CHECK_NE(index, ESP); // Illegal addressing mode.
- SetModRM(0, ESP);
- SetSIB(scale, index, EBP);
- SetDisp32(disp);
- }
-
- Address(Register base, Register index, ScaleFactor scale, int32_t disp) {
- CHECK_NE(index, ESP); // Illegal addressing mode.
- if (disp == 0 && base != EBP) {
- SetModRM(0, ESP);
- SetSIB(scale, index, base);
- } else if (disp >= -128 && disp <= 127) {
- SetModRM(1, ESP);
- SetSIB(scale, index, base);
- SetDisp8(disp);
- } else {
- SetModRM(2, ESP);
- SetSIB(scale, index, base);
- SetDisp32(disp);
- }
- }
-
- static Address Absolute(uword addr) {
- Address result;
- result.SetModRM(0, EBP);
- result.SetDisp32(addr);
- return result;
- }
-
- static Address Absolute(ThreadOffset addr) {
- return Absolute(addr.Int32Value());
- }
-
- private:
- Address() {}
-
- DISALLOW_COPY_AND_ASSIGN(Address);
-};
-
-#endif
enum LoadOperandType {
kLoadSignedByte,
@@ -215,7 +50,7 @@
kStoreDWord
};
-class MipsAssembler : public Assembler {
+class MipsAssembler FINAL : public Assembler {
public:
MipsAssembler() {}
virtual ~MipsAssembler() {}
@@ -310,40 +145,6 @@
void StoreFToOffset(FRegister reg, Register base, int32_t offset);
void StoreDToOffset(DRegister reg, Register base, int32_t offset);
-#if 0
- MipsAssembler* lock();
-
- void mfence();
-
- MipsAssembler* fs();
-
- //
- // Macros for High-level operations.
- //
-
- void AddImmediate(Register reg, const Immediate& imm);
-
- void LoadDoubleConstant(XmmRegister dst, double value);
-
- void DoubleNegate(XmmRegister d);
- void FloatNegate(XmmRegister f);
-
- void DoubleAbs(XmmRegister reg);
-
- void LockCmpxchgl(const Address& address, Register reg) {
- lock()->cmpxchgl(address, reg);
- }
-
- //
- // Misc. functionality
- //
- int PreferredLoopAlignment() { return 16; }
- void Align(int alignment, int offset);
-
- // Debugging and bringup support.
- void Stop(const char* message);
-#endif
-
// Emit data (e.g. encoded instruction or immediate) to the instruction stream.
void Emit(int32_t value);
void EmitBranch(Register rt, Register rs, Label* label, bool equal);
@@ -355,127 +156,116 @@
//
// Emit code that will create an activation on the stack
- virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
- const std::vector<ManagedRegister>& callee_save_regs,
- const ManagedRegisterEntrySpills& entry_spills);
+ void BuildFrame(size_t frame_size, ManagedRegister method_reg,
+ const std::vector<ManagedRegister>& callee_save_regs,
+ const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
// Emit code that will remove an activation from the stack
- virtual void RemoveFrame(size_t frame_size,
- const std::vector<ManagedRegister>& callee_save_regs);
+ void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
+ OVERRIDE;
- virtual void IncreaseFrameSize(size_t adjust);
- virtual void DecreaseFrameSize(size_t adjust);
+ void IncreaseFrameSize(size_t adjust) OVERRIDE;
+ void DecreaseFrameSize(size_t adjust) OVERRIDE;
// Store routines
- virtual void Store(FrameOffset offs, ManagedRegister msrc, size_t size);
- virtual void StoreRef(FrameOffset dest, ManagedRegister msrc);
- virtual void StoreRawPtr(FrameOffset dest, ManagedRegister msrc);
+ void Store(FrameOffset offs, ManagedRegister msrc, size_t size) OVERRIDE;
+ void StoreRef(FrameOffset dest, ManagedRegister msrc) OVERRIDE;
+ void StoreRawPtr(FrameOffset dest, ManagedRegister msrc) OVERRIDE;
- virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
- ManagedRegister mscratch);
+ void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister mscratch) OVERRIDE;
- virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
- ManagedRegister mscratch);
+ void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister mscratch)
+ OVERRIDE;
- virtual void StoreStackOffsetToThread(ThreadOffset thr_offs,
- FrameOffset fr_offs,
- ManagedRegister mscratch);
+ void StoreStackOffsetToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
+ ManagedRegister mscratch) OVERRIDE;
- virtual void StoreStackPointerToThread(ThreadOffset thr_offs);
+ void StoreStackPointerToThread32(ThreadOffset<4> thr_offs) OVERRIDE;
- virtual void StoreSpanning(FrameOffset dest, ManagedRegister msrc,
- FrameOffset in_off, ManagedRegister mscratch);
+ void StoreSpanning(FrameOffset dest, ManagedRegister msrc, FrameOffset in_off,
+ ManagedRegister mscratch) OVERRIDE;
// Load routines
- virtual void Load(ManagedRegister mdest, FrameOffset src, size_t size);
+ void Load(ManagedRegister mdest, FrameOffset src, size_t size) OVERRIDE;
- virtual void Load(ManagedRegister mdest, ThreadOffset src, size_t size);
+ void LoadFromThread32(ManagedRegister mdest, ThreadOffset<4> src, size_t size) OVERRIDE;
- virtual void LoadRef(ManagedRegister dest, FrameOffset src);
+ void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE;
- virtual void LoadRef(ManagedRegister mdest, ManagedRegister base,
- MemberOffset offs);
+ void LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs) OVERRIDE;
- virtual void LoadRawPtr(ManagedRegister mdest, ManagedRegister base,
- Offset offs);
+ void LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) OVERRIDE;
- virtual void LoadRawPtrFromThread(ManagedRegister mdest,
- ThreadOffset offs);
+ void LoadRawPtrFromThread32(ManagedRegister mdest, ThreadOffset<4> offs) OVERRIDE;
// Copying routines
- virtual void Move(ManagedRegister mdest, ManagedRegister msrc, size_t size);
+ void Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) OVERRIDE;
- virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
- ManagedRegister mscratch);
+ void CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs,
+ ManagedRegister mscratch) OVERRIDE;
- virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
- ManagedRegister mscratch);
+ void CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
+ ManagedRegister mscratch) OVERRIDE;
- virtual void CopyRef(FrameOffset dest, FrameOffset src,
- ManagedRegister mscratch);
+ void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister mscratch) OVERRIDE;
- virtual void Copy(FrameOffset dest, FrameOffset src, ManagedRegister mscratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src, ManagedRegister mscratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
- ManagedRegister mscratch, size_t size);
+ void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister mscratch,
+ size_t size) OVERRIDE;
- virtual void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
- ManagedRegister mscratch, size_t size);
+ void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
+ ManagedRegister mscratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
- ManagedRegister mscratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister mscratch,
+ size_t size) OVERRIDE;
- virtual void Copy(ManagedRegister dest, Offset dest_offset,
- ManagedRegister src, Offset src_offset,
- ManagedRegister mscratch, size_t size);
+ void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
+ ManagedRegister mscratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
- ManagedRegister mscratch, size_t size);
+ void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
+ ManagedRegister mscratch, size_t size) OVERRIDE;
- virtual void MemoryBarrier(ManagedRegister);
+ void MemoryBarrier(ManagedRegister) OVERRIDE;
// Sign extension
- virtual void SignExtend(ManagedRegister mreg, size_t size);
+ void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Zero extension
- virtual void ZeroExtend(ManagedRegister mreg, size_t size);
+ void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Exploit fast access in managed code to Thread::Current()
- virtual void GetCurrentThread(ManagedRegister tr);
- virtual void GetCurrentThread(FrameOffset dest_offset,
- ManagedRegister mscratch);
+ void GetCurrentThread(ManagedRegister tr) OVERRIDE;
+ void GetCurrentThread(FrameOffset dest_offset, ManagedRegister mscratch) OVERRIDE;
// Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed. in_reg holds a possibly stale reference
// that can be used to avoid loading the SIRT entry to see if the value is
// NULL.
- virtual void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
- ManagedRegister in_reg, bool null_allowed);
+ void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset, ManagedRegister in_reg,
+ bool null_allowed) OVERRIDE;
// Set up out_off to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed.
- virtual void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
- ManagedRegister mscratch, bool null_allowed);
+ void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset, ManagedRegister mscratch,
+ bool null_allowed) OVERRIDE;
// src holds a SIRT entry (Object**) load this into dst
- virtual void LoadReferenceFromSirt(ManagedRegister dst,
- ManagedRegister src);
+ void LoadReferenceFromSirt(ManagedRegister dst, ManagedRegister src) OVERRIDE;
// Heap::VerifyObject on src. In some cases (such as a reference to this) we
// know that src may not be null.
- virtual void VerifyObject(ManagedRegister src, bool could_be_null);
- virtual void VerifyObject(FrameOffset src, bool could_be_null);
+ void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
+ void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
// Call to address held at [base+offset]
- virtual void Call(ManagedRegister base, Offset offset,
- ManagedRegister mscratch);
- virtual void Call(FrameOffset base, Offset offset,
- ManagedRegister mscratch);
- virtual void Call(ThreadOffset offset, ManagedRegister mscratch);
+ void Call(ManagedRegister base, Offset offset, ManagedRegister mscratch) OVERRIDE;
+ void Call(FrameOffset base, Offset offset, ManagedRegister mscratch) OVERRIDE;
+ void CallFromThread32(ThreadOffset<4> offset, ManagedRegister mscratch) OVERRIDE;
// Generate code to check if Thread::Current()->exception_ is non-null
// and branch to a ExceptionSlowPath if it is.
- virtual void ExceptionPoll(ManagedRegister mscratch, size_t stack_adjust);
+ void ExceptionPoll(ManagedRegister mscratch, size_t stack_adjust) OVERRIDE;
private:
void EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct);
@@ -491,11 +281,11 @@
};
// Slowpath entered when Thread::Current()->_exception is non-null
-class MipsExceptionSlowPath : public SlowPath {
+class MipsExceptionSlowPath FINAL : public SlowPath {
public:
explicit MipsExceptionSlowPath(MipsManagedRegister scratch, size_t stack_adjust)
: scratch_(scratch), stack_adjust_(stack_adjust) {}
- virtual void Emit(Assembler *sp_asm);
+ virtual void Emit(Assembler *sp_asm) OVERRIDE;
private:
const MipsManagedRegister scratch_;
const size_t stack_adjust_;
diff --git a/compiler/utils/x86/assembler_x86.cc b/compiler/utils/x86/assembler_x86.cc
index ebbb43a..aac8b01 100644
--- a/compiler/utils/x86/assembler_x86.cc
+++ b/compiler/utils/x86/assembler_x86.cc
@@ -1478,12 +1478,12 @@
movl(Address(ESP, dest), Immediate(imm));
}
-void X86Assembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
+void X86Assembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm,
ManagedRegister) {
fs()->movl(Address::Absolute(dest), Immediate(imm));
}
-void X86Assembler::StoreStackOffsetToThread(ThreadOffset thr_offs,
+void X86Assembler::StoreStackOffsetToThread32(ThreadOffset<4> thr_offs,
FrameOffset fr_offs,
ManagedRegister mscratch) {
X86ManagedRegister scratch = mscratch.AsX86();
@@ -1492,14 +1492,10 @@
fs()->movl(Address::Absolute(thr_offs), scratch.AsCpuRegister());
}
-void X86Assembler::StoreStackPointerToThread(ThreadOffset thr_offs) {
+void X86Assembler::StoreStackPointerToThread32(ThreadOffset<4> thr_offs) {
fs()->movl(Address::Absolute(thr_offs), ESP);
}
-void X86Assembler::StoreLabelToThread(ThreadOffset thr_offs, Label* lbl) {
- fs()->movl(Address::Absolute(thr_offs), lbl);
-}
-
void X86Assembler::StoreSpanning(FrameOffset /*dst*/, ManagedRegister /*src*/,
FrameOffset /*in_off*/, ManagedRegister /*scratch*/) {
UNIMPLEMENTED(FATAL); // this case only currently exists for ARM
@@ -1532,7 +1528,7 @@
}
}
-void X86Assembler::Load(ManagedRegister mdest, ThreadOffset src, size_t size) {
+void X86Assembler::LoadFromThread32(ManagedRegister mdest, ThreadOffset<4> src, size_t size) {
X86ManagedRegister dest = mdest.AsX86();
if (dest.IsNoRegister()) {
CHECK_EQ(0u, size);
@@ -1542,7 +1538,7 @@
} else if (dest.IsRegisterPair()) {
CHECK_EQ(8u, size);
fs()->movl(dest.AsRegisterPairLow(), Address::Absolute(src));
- fs()->movl(dest.AsRegisterPairHigh(), Address::Absolute(ThreadOffset(src.Int32Value()+4)));
+ fs()->movl(dest.AsRegisterPairHigh(), Address::Absolute(ThreadOffset<4>(src.Int32Value()+4)));
} else if (dest.IsX87Register()) {
if (size == 4) {
fs()->flds(Address::Absolute(src));
@@ -1582,8 +1578,8 @@
movl(dest.AsCpuRegister(), Address(base.AsX86().AsCpuRegister(), offs));
}
-void X86Assembler::LoadRawPtrFromThread(ManagedRegister mdest,
- ThreadOffset offs) {
+void X86Assembler::LoadRawPtrFromThread32(ManagedRegister mdest,
+ ThreadOffset<4> offs) {
X86ManagedRegister dest = mdest.AsX86();
CHECK(dest.IsCpuRegister());
fs()->movl(dest.AsCpuRegister(), Address::Absolute(offs));
@@ -1645,8 +1641,8 @@
movl(Address(ESP, dest), scratch.AsCpuRegister());
}
-void X86Assembler::CopyRawPtrFromThread(FrameOffset fr_offs,
- ThreadOffset thr_offs,
+void X86Assembler::CopyRawPtrFromThread32(FrameOffset fr_offs,
+ ThreadOffset<4> thr_offs,
ManagedRegister mscratch) {
X86ManagedRegister scratch = mscratch.AsX86();
CHECK(scratch.IsCpuRegister());
@@ -1654,7 +1650,7 @@
Store(fr_offs, scratch, 4);
}
-void X86Assembler::CopyRawPtrToThread(ThreadOffset thr_offs,
+void X86Assembler::CopyRawPtrToThread32(ThreadOffset<4> thr_offs,
FrameOffset fr_offs,
ManagedRegister mscratch) {
X86ManagedRegister scratch = mscratch.AsX86();
@@ -1804,26 +1800,26 @@
call(Address(scratch, offset));
}
-void X86Assembler::Call(ThreadOffset offset, ManagedRegister /*mscratch*/) {
+void X86Assembler::CallFromThread32(ThreadOffset<4> offset, ManagedRegister /*mscratch*/) {
fs()->call(Address::Absolute(offset));
}
void X86Assembler::GetCurrentThread(ManagedRegister tr) {
fs()->movl(tr.AsX86().AsCpuRegister(),
- Address::Absolute(Thread::SelfOffset()));
+ Address::Absolute(Thread::SelfOffset<4>()));
}
void X86Assembler::GetCurrentThread(FrameOffset offset,
ManagedRegister mscratch) {
X86ManagedRegister scratch = mscratch.AsX86();
- fs()->movl(scratch.AsCpuRegister(), Address::Absolute(Thread::SelfOffset()));
+ fs()->movl(scratch.AsCpuRegister(), Address::Absolute(Thread::SelfOffset<4>()));
movl(Address(ESP, offset), scratch.AsCpuRegister());
}
void X86Assembler::ExceptionPoll(ManagedRegister /*scratch*/, size_t stack_adjust) {
X86ExceptionSlowPath* slow = new X86ExceptionSlowPath(stack_adjust);
buffer_.EnqueueSlowPath(slow);
- fs()->cmpl(Address::Absolute(Thread::ExceptionOffset()), Immediate(0));
+ fs()->cmpl(Address::Absolute(Thread::ExceptionOffset<4>()), Immediate(0));
j(kNotEqual, slow->Entry());
}
@@ -1836,8 +1832,8 @@
__ DecreaseFrameSize(stack_adjust_);
}
// Pass exception as argument in EAX
- __ fs()->movl(EAX, Address::Absolute(Thread::ExceptionOffset()));
- __ fs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(pDeliverException)));
+ __ fs()->movl(EAX, Address::Absolute(Thread::ExceptionOffset<4>()));
+ __ fs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(4, pDeliverException)));
// this call should never return
__ int3();
#undef __
diff --git a/compiler/utils/x86/assembler_x86.h b/compiler/utils/x86/assembler_x86.h
index f906a6f..f8fc4c0 100644
--- a/compiler/utils/x86/assembler_x86.h
+++ b/compiler/utils/x86/assembler_x86.h
@@ -117,7 +117,6 @@
private:
byte length_;
byte encoding_[6];
- byte padding_;
explicit Operand(Register reg) { SetModRM(3, reg); }
@@ -192,21 +191,15 @@
}
}
- static Address Absolute(uword addr, bool has_rip = false) {
+ static Address Absolute(uword addr) {
Address result;
- if (has_rip) {
- result.SetModRM(0, ESP);
- result.SetSIB(TIMES_1, ESP, EBP);
- result.SetDisp32(addr);
- } else {
- result.SetModRM(0, EBP);
- result.SetDisp32(addr);
- }
+ result.SetModRM(0, EBP);
+ result.SetDisp32(addr);
return result;
}
- static Address Absolute(ThreadOffset addr, bool has_rip = false) {
- return Absolute(addr.Int32Value(), has_rip);
+ static Address Absolute(ThreadOffset<4> addr) {
+ return Absolute(addr.Int32Value());
}
private:
@@ -465,129 +458,116 @@
//
// Emit code that will create an activation on the stack
- virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
- const std::vector<ManagedRegister>& callee_save_regs,
- const ManagedRegisterEntrySpills& entry_spills);
+ void BuildFrame(size_t frame_size, ManagedRegister method_reg,
+ const std::vector<ManagedRegister>& callee_save_regs,
+ const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
// Emit code that will remove an activation from the stack
- virtual void RemoveFrame(size_t frame_size,
- const std::vector<ManagedRegister>& callee_save_regs);
+ void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
+ OVERRIDE;
- virtual void IncreaseFrameSize(size_t adjust);
- virtual void DecreaseFrameSize(size_t adjust);
+ void IncreaseFrameSize(size_t adjust) OVERRIDE;
+ void DecreaseFrameSize(size_t adjust) OVERRIDE;
// Store routines
- virtual void Store(FrameOffset offs, ManagedRegister src, size_t size);
- virtual void StoreRef(FrameOffset dest, ManagedRegister src);
- virtual void StoreRawPtr(FrameOffset dest, ManagedRegister src);
+ void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE;
+ void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE;
+ void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE;
- virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
- ManagedRegister scratch);
+ void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
- virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
- ManagedRegister scratch);
+ void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister scratch)
+ OVERRIDE;
- virtual void StoreStackOffsetToThread(ThreadOffset thr_offs,
- FrameOffset fr_offs,
- ManagedRegister scratch);
+ void StoreStackOffsetToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs,
+ ManagedRegister scratch) OVERRIDE;
- virtual void StoreStackPointerToThread(ThreadOffset thr_offs);
+ void StoreStackPointerToThread32(ThreadOffset<4> thr_offs) OVERRIDE;
- void StoreLabelToThread(ThreadOffset thr_offs, Label* lbl);
-
- virtual void StoreSpanning(FrameOffset dest, ManagedRegister src,
- FrameOffset in_off, ManagedRegister scratch);
+ void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
+ ManagedRegister scratch) OVERRIDE;
// Load routines
- virtual void Load(ManagedRegister dest, FrameOffset src, size_t size);
+ void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE;
- virtual void Load(ManagedRegister dest, ThreadOffset src, size_t size);
+ void LoadFromThread32(ManagedRegister dest, ThreadOffset<4> src, size_t size) OVERRIDE;
- virtual void LoadRef(ManagedRegister dest, FrameOffset src);
+ void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE;
- virtual void LoadRef(ManagedRegister dest, ManagedRegister base,
- MemberOffset offs);
+ void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE;
- virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
- Offset offs);
+ void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
- virtual void LoadRawPtrFromThread(ManagedRegister dest,
- ThreadOffset offs);
+ void LoadRawPtrFromThread32(ManagedRegister dest, ThreadOffset<4> offs) OVERRIDE;
// Copying routines
- virtual void Move(ManagedRegister dest, ManagedRegister src, size_t size);
+ void Move(ManagedRegister dest, ManagedRegister src, size_t size) OVERRIDE;
- virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
- ManagedRegister scratch);
+ void CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs,
+ ManagedRegister scratch) OVERRIDE;
- virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
- ManagedRegister scratch);
+ void CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs, ManagedRegister scratch)
+ OVERRIDE;
- virtual void CopyRef(FrameOffset dest, FrameOffset src,
- ManagedRegister scratch);
+ void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE;
- virtual void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
- ManagedRegister scratch, size_t size);
+ void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(ManagedRegister dest, Offset dest_offset,
- ManagedRegister src, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
+ ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
+ ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void MemoryBarrier(ManagedRegister);
+ void MemoryBarrier(ManagedRegister) OVERRIDE;
// Sign extension
- virtual void SignExtend(ManagedRegister mreg, size_t size);
+ void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Zero extension
- virtual void ZeroExtend(ManagedRegister mreg, size_t size);
+ void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Exploit fast access in managed code to Thread::Current()
- virtual void GetCurrentThread(ManagedRegister tr);
- virtual void GetCurrentThread(FrameOffset dest_offset,
- ManagedRegister scratch);
+ void GetCurrentThread(ManagedRegister tr) OVERRIDE;
+ void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE;
// Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed. in_reg holds a possibly stale reference
// that can be used to avoid loading the SIRT entry to see if the value is
// NULL.
- virtual void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
- ManagedRegister in_reg, bool null_allowed);
+ void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset, ManagedRegister in_reg,
+ bool null_allowed) OVERRIDE;
// Set up out_off to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed.
- virtual void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
- ManagedRegister scratch, bool null_allowed);
+ void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset, ManagedRegister scratch,
+ bool null_allowed) OVERRIDE;
// src holds a SIRT entry (Object**) load this into dst
- virtual void LoadReferenceFromSirt(ManagedRegister dst,
- ManagedRegister src);
+ void LoadReferenceFromSirt(ManagedRegister dst, ManagedRegister src) OVERRIDE;
// Heap::VerifyObject on src. In some cases (such as a reference to this) we
// know that src may not be null.
- virtual void VerifyObject(ManagedRegister src, bool could_be_null);
- virtual void VerifyObject(FrameOffset src, bool could_be_null);
+ void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
+ void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
// Call to address held at [base+offset]
- virtual void Call(ManagedRegister base, Offset offset,
- ManagedRegister scratch);
- virtual void Call(FrameOffset base, Offset offset,
- ManagedRegister scratch);
- virtual void Call(ThreadOffset offset, ManagedRegister scratch);
+ void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
+ void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
+ void CallFromThread32(ThreadOffset<4> offset, ManagedRegister scratch) OVERRIDE;
// Generate code to check if Thread::Current()->exception_ is non-null
// and branch to a ExceptionSlowPath if it is.
- virtual void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust);
+ void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE;
private:
inline void EmitUint8(uint8_t value);
@@ -637,10 +617,10 @@
}
// Slowpath entered when Thread::Current()->_exception is non-null
-class X86ExceptionSlowPath : public SlowPath {
+class X86ExceptionSlowPath FINAL : public SlowPath {
public:
explicit X86ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {}
- virtual void Emit(Assembler *sp_asm);
+ virtual void Emit(Assembler *sp_asm) OVERRIDE;
private:
const size_t stack_adjust_;
};
diff --git a/compiler/utils/x86_64/assembler_x86_64.cc b/compiler/utils/x86_64/assembler_x86_64.cc
index fa302c9..52b9382 100644
--- a/compiler/utils/x86_64/assembler_x86_64.cc
+++ b/compiler/utils/x86_64/assembler_x86_64.cc
@@ -24,23 +24,29 @@
namespace art {
namespace x86_64 {
+std::ostream& operator<<(std::ostream& os, const CpuRegister& reg) {
+ return os << reg.AsRegister();
+}
+
std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) {
- return os << "XMM" << static_cast<int>(reg);
+ return os << reg.AsFloatRegister();
}
std::ostream& operator<<(std::ostream& os, const X87Register& reg) {
return os << "ST" << static_cast<int>(reg);
}
-void X86_64Assembler::call(Register reg) {
+void X86_64Assembler::call(CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg);
EmitUint8(0xFF);
- EmitRegisterOperand(2, reg);
+ EmitRegisterOperand(2, reg.LowBits());
}
void X86_64Assembler::call(const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(address);
EmitUint8(0xFF);
EmitOperand(2, address);
}
@@ -54,15 +60,16 @@
}
-void X86_64Assembler::pushq(Register reg) {
+void X86_64Assembler::pushq(CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- rex_rm(reg);
- EmitUint8(0x50 + reg);
+ EmitOptionalRex32(reg);
+ EmitUint8(0x50 + reg.LowBits());
}
void X86_64Assembler::pushq(const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(address);
EmitUint8(0xFF);
EmitOperand(6, address);
}
@@ -80,332 +87,335 @@
}
-void X86_64Assembler::popq(Register reg) {
+void X86_64Assembler::popq(CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- rex_rm(reg);
- EmitUint8(0x58 + reg);
+ EmitOptionalRex32(reg);
+ EmitUint8(0x58 + reg.LowBits());
}
void X86_64Assembler::popq(const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(address);
EmitUint8(0x8F);
EmitOperand(0, address);
}
-void X86_64Assembler::movq(Register dst, const Immediate& imm) {
+void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x48); // REX.W
- EmitUint8(0xB8 + dst);
+ EmitRex64(dst);
+ EmitUint8(0xB8 + dst.LowBits());
EmitImmediate(imm);
}
-void X86_64Assembler::movl(Register dst, const Immediate& imm) {
+void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0xB8 + dst);
+ EmitOptionalRex32(dst);
+ EmitUint8(0xB8 + dst.LowBits());
EmitImmediate(imm);
}
-void X86_64Assembler::movq(Register dst, Register src) {
+void X86_64Assembler::movq(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x48); // REX.W
+ EmitRex64(dst, src);
EmitUint8(0x89);
- EmitRegisterOperand(src, dst);
+ EmitRegisterOperand(src.LowBits(), dst.LowBits());
}
-void X86_64Assembler::movl(Register dst, Register src) {
+void X86_64Assembler::movl(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x89);
- EmitRegisterOperand(src, dst);
+ EmitRegisterOperand(src.LowBits(), dst.LowBits());
}
-void X86_64Assembler::movq(Register dst, const Address& src) {
+void X86_64Assembler::movq(CpuRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- rex_reg(dst, 8);
+ EmitRex64(dst, src);
EmitUint8(0x8B);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
-void X86_64Assembler::movl(Register dst, const Address& src) {
+void X86_64Assembler::movl(CpuRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- rex_reg(dst, 4);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x8B);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
-void X86_64Assembler::movq(const Address& dst, Register src) {
+void X86_64Assembler::movq(const Address& dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- rex_reg(src, 8);
+ EmitRex64(src, dst);
EmitUint8(0x89);
- EmitOperand(src, dst);
+ EmitOperand(src.LowBits(), dst);
}
-void X86_64Assembler::movl(const Address& dst, Register src) {
+void X86_64Assembler::movl(const Address& dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- rex_reg(src, 4);
+ EmitOptionalRex32(src, dst);
EmitUint8(0x89);
- EmitOperand(src, dst);
+ EmitOperand(src.LowBits(), dst);
}
-
void X86_64Assembler::movl(const Address& dst, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst);
EmitUint8(0xC7);
EmitOperand(0, dst);
EmitImmediate(imm);
}
-void X86_64Assembler::movl(const Address& dst, Label* lbl) {
+void X86_64Assembler::movzxb(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0xC7);
- EmitOperand(0, dst);
- EmitLabel(lbl, dst.length_ + 5);
-}
-
-void X86_64Assembler::movzxb(Register dst, ByteRegister src) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalByteRegNormalizingRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0xB6);
- EmitRegisterOperand(dst, src);
+ EmitRegisterOperand(dst.LowBits(), src.LowBits());
}
-void X86_64Assembler::movzxb(Register dst, const Address& src) {
+void X86_64Assembler::movzxb(CpuRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalByteRegNormalizingRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0xB6);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
-void X86_64Assembler::movsxb(Register dst, ByteRegister src) {
+void X86_64Assembler::movsxb(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalByteRegNormalizingRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0xBE);
- EmitRegisterOperand(dst, src);
+ EmitRegisterOperand(dst.LowBits(), src.LowBits());
}
-void X86_64Assembler::movsxb(Register dst, const Address& src) {
+void X86_64Assembler::movsxb(CpuRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalByteRegNormalizingRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0xBE);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
-void X86_64Assembler::movb(Register /*dst*/, const Address& /*src*/) {
+void X86_64Assembler::movb(CpuRegister /*dst*/, const Address& /*src*/) {
LOG(FATAL) << "Use movzxb or movsxb instead.";
}
-void X86_64Assembler::movb(const Address& dst, ByteRegister src) {
+void X86_64Assembler::movb(const Address& dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalByteRegNormalizingRex32(src, dst);
EmitUint8(0x88);
- EmitOperand(src, dst);
+ EmitOperand(src.LowBits(), dst);
}
void X86_64Assembler::movb(const Address& dst, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xC6);
- EmitOperand(RAX, dst);
+ EmitOperand(Register::RAX, dst);
CHECK(imm.is_int8());
EmitUint8(imm.value() & 0xFF);
}
-void X86_64Assembler::movzxw(Register dst, Register src) {
+void X86_64Assembler::movzxw(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0xB7);
- EmitRegisterOperand(dst, src);
+ EmitRegisterOperand(dst.LowBits(), src.LowBits());
}
-void X86_64Assembler::movzxw(Register dst, const Address& src) {
+void X86_64Assembler::movzxw(CpuRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0xB7);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
-void X86_64Assembler::movsxw(Register dst, Register src) {
+void X86_64Assembler::movsxw(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0xBF);
- EmitRegisterOperand(dst, src);
+ EmitRegisterOperand(dst.LowBits(), src.LowBits());
}
-void X86_64Assembler::movsxw(Register dst, const Address& src) {
+void X86_64Assembler::movsxw(CpuRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0xBF);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
-void X86_64Assembler::movw(Register /*dst*/, const Address& /*src*/) {
+void X86_64Assembler::movw(CpuRegister /*dst*/, const Address& /*src*/) {
LOG(FATAL) << "Use movzxw or movsxw instead.";
}
-void X86_64Assembler::movw(const Address& dst, Register src) {
+void X86_64Assembler::movw(const Address& dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(src, dst);
EmitOperandSizeOverride();
EmitUint8(0x89);
- EmitOperand(src, dst);
+ EmitOperand(src.LowBits(), dst);
}
-void X86_64Assembler::leaq(Register dst, const Address& src) {
+void X86_64Assembler::leaq(CpuRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- rex_reg(dst, 8);
+ EmitRex64(dst, src);
EmitUint8(0x8D);
- EmitOperand(dst, src);
-}
-
-
-void X86_64Assembler::cmovl(Condition condition, Register dst, Register src) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x0F);
- EmitUint8(0x40 + condition);
- EmitRegisterOperand(dst, src);
-}
-
-
-void X86_64Assembler::setb(Condition condition, Register dst) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x0F);
- EmitUint8(0x90 + condition);
- EmitOperand(0, Operand(dst));
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::movss(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x10);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::movss(const Address& dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(src, dst);
EmitUint8(0x0F);
EmitUint8(0x11);
- EmitOperand(src, dst);
+ EmitOperand(src.LowBits(), dst);
}
void X86_64Assembler::movss(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x11);
- EmitXmmRegisterOperand(src, dst);
+ EmitXmmRegisterOperand(src.LowBits(), dst);
}
-void X86_64Assembler::movd(XmmRegister dst, Register src) {
+void X86_64Assembler::movd(XmmRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0x66);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x6E);
- EmitOperand(dst, Operand(src));
+ EmitOperand(dst.LowBits(), Operand(src));
}
-void X86_64Assembler::movd(Register dst, XmmRegister src) {
+void X86_64Assembler::movd(CpuRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0x66);
+ EmitOptionalRex32(src, dst);
EmitUint8(0x0F);
EmitUint8(0x7E);
- EmitOperand(src, Operand(dst));
+ EmitOperand(src.LowBits(), Operand(dst));
}
void X86_64Assembler::addss(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x58);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::addss(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x58);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::subss(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x5C);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::subss(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x5C);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::mulss(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x59);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::mulss(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x59);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::divss(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x5E);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::divss(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x5E);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
@@ -426,258 +436,287 @@
void X86_64Assembler::movsd(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x10);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::movsd(const Address& dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(src, dst);
EmitUint8(0x0F);
EmitUint8(0x11);
- EmitOperand(src, dst);
+ EmitOperand(src.LowBits(), dst);
}
void X86_64Assembler::movsd(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x11);
- EmitXmmRegisterOperand(src, dst);
+ EmitXmmRegisterOperand(src.LowBits(), dst);
}
void X86_64Assembler::addsd(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x58);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::addsd(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x58);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::subsd(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x5C);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::subsd(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x5C);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::mulsd(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x59);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::mulsd(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x59);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::divsd(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x5E);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::divsd(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x5E);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
-void X86_64Assembler::cvtsi2ss(XmmRegister dst, Register src) {
+void X86_64Assembler::cvtsi2ss(XmmRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x2A);
- EmitOperand(dst, Operand(src));
+ EmitOperand(dst.LowBits(), Operand(src));
}
-void X86_64Assembler::cvtsi2sd(XmmRegister dst, Register src) {
+void X86_64Assembler::cvtsi2sd(XmmRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x2A);
- EmitOperand(dst, Operand(src));
+ EmitOperand(dst.LowBits(), Operand(src));
}
-void X86_64Assembler::cvtss2si(Register dst, XmmRegister src) {
+void X86_64Assembler::cvtss2si(CpuRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x2D);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x5A);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
-void X86_64Assembler::cvtsd2si(Register dst, XmmRegister src) {
+void X86_64Assembler::cvtsd2si(CpuRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x2D);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
-void X86_64Assembler::cvttss2si(Register dst, XmmRegister src) {
+void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x2C);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
-void X86_64Assembler::cvttsd2si(Register dst, XmmRegister src) {
+void X86_64Assembler::cvttsd2si(CpuRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x2C);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x5A);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0xE6);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::comiss(XmmRegister a, XmmRegister b) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(a, b);
EmitUint8(0x0F);
EmitUint8(0x2F);
- EmitXmmRegisterOperand(a, b);
+ EmitXmmRegisterOperand(a.LowBits(), b);
}
void X86_64Assembler::comisd(XmmRegister a, XmmRegister b) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0x66);
+ EmitOptionalRex32(a, b);
EmitUint8(0x0F);
EmitUint8(0x2F);
- EmitXmmRegisterOperand(a, b);
+ EmitXmmRegisterOperand(a.LowBits(), b);
}
void X86_64Assembler::sqrtsd(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF2);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x51);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::sqrtss(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0xF3);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x51);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::xorpd(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0x66);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x57);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::xorpd(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0x66);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x57);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::xorps(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x57);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
void X86_64Assembler::xorps(XmmRegister dst, XmmRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x57);
- EmitXmmRegisterOperand(dst, src);
+ EmitXmmRegisterOperand(dst.LowBits(), src);
}
void X86_64Assembler::andpd(XmmRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0x66);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0x54);
- EmitOperand(dst, src);
+ EmitOperand(dst.LowBits(), src);
}
@@ -766,92 +805,102 @@
}
-void X86_64Assembler::xchgl(Register dst, Register src) {
+void X86_64Assembler::xchgl(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x87);
- EmitRegisterOperand(dst, src);
+ EmitRegisterOperand(dst.LowBits(), src.LowBits());
}
-void X86_64Assembler::xchgl(Register reg, const Address& address) {
+void X86_64Assembler::xchgl(CpuRegister reg, const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg, address);
EmitUint8(0x87);
- EmitOperand(reg, address);
+ EmitOperand(reg.LowBits(), address);
}
-void X86_64Assembler::cmpl(Register reg, const Immediate& imm) {
+void X86_64Assembler::cmpl(CpuRegister reg, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg);
EmitComplex(7, Operand(reg), imm);
}
-void X86_64Assembler::cmpl(Register reg0, Register reg1) {
+void X86_64Assembler::cmpl(CpuRegister reg0, CpuRegister reg1) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg0, reg1);
EmitUint8(0x3B);
- EmitOperand(reg0, Operand(reg1));
+ EmitOperand(reg0.LowBits(), Operand(reg1));
}
-void X86_64Assembler::cmpl(Register reg, const Address& address) {
+void X86_64Assembler::cmpl(CpuRegister reg, const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg, address);
EmitUint8(0x3B);
- EmitOperand(reg, address);
+ EmitOperand(reg.LowBits(), address);
}
-void X86_64Assembler::addl(Register dst, Register src) {
+void X86_64Assembler::addl(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x03);
- EmitRegisterOperand(dst, src);
+ EmitRegisterOperand(dst.LowBits(), src.LowBits());
}
-void X86_64Assembler::addl(Register reg, const Address& address) {
+void X86_64Assembler::addl(CpuRegister reg, const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg, address);
EmitUint8(0x03);
- EmitOperand(reg, address);
+ EmitOperand(reg.LowBits(), address);
}
-void X86_64Assembler::cmpl(const Address& address, Register reg) {
+void X86_64Assembler::cmpl(const Address& address, CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg, address);
EmitUint8(0x39);
- EmitOperand(reg, address);
+ EmitOperand(reg.LowBits(), address);
}
void X86_64Assembler::cmpl(const Address& address, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(address);
EmitComplex(7, address, imm);
}
-void X86_64Assembler::testl(Register reg1, Register reg2) {
+void X86_64Assembler::testl(CpuRegister reg1, CpuRegister reg2) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- rex(reg1, reg2, 4);
+ EmitOptionalRex32(reg1, reg2);
EmitUint8(0x85);
- EmitRegisterOperand(reg1, reg2);
+ EmitRegisterOperand(reg1.LowBits(), reg2.LowBits());
}
-void X86_64Assembler::testl(Register reg, const Immediate& immediate) {
+void X86_64Assembler::testl(CpuRegister reg, const Immediate& immediate) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
// For registers that have a byte variant (RAX, RBX, RCX, and RDX)
- // we only test the byte register to keep the encoding short.
- if (immediate.is_uint8() && reg < 4) {
+ // we only test the byte CpuRegister to keep the encoding short.
+ if (immediate.is_uint8() && reg.AsRegister() < 4) {
// Use zero-extended 8-bit immediate.
- if (reg == RAX) {
+ if (reg.AsRegister() == RAX) {
EmitUint8(0xA8);
} else {
EmitUint8(0xF6);
- EmitUint8(0xC0 + reg);
+ EmitUint8(0xC0 + reg.AsRegister());
}
EmitUint8(immediate.value() & 0xFF);
- } else if (reg == RAX) {
+ } else if (reg.AsRegister() == RAX) {
// Use short form if the destination is RAX.
EmitUint8(0xA9);
EmitImmediate(immediate);
} else {
+ EmitOptionalRex32(reg);
EmitUint8(0xF7);
EmitOperand(0, Operand(reg));
EmitImmediate(immediate);
@@ -859,136 +908,145 @@
}
-void X86_64Assembler::andl(Register dst, Register src) {
+void X86_64Assembler::andl(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x23);
- EmitOperand(dst, Operand(src));
+ EmitOperand(dst.LowBits(), Operand(src));
}
-void X86_64Assembler::andl(Register dst, const Immediate& imm) {
+void X86_64Assembler::andl(CpuRegister dst, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst);
EmitComplex(4, Operand(dst), imm);
}
-void X86_64Assembler::orl(Register dst, Register src) {
+void X86_64Assembler::orl(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0B);
- EmitOperand(dst, Operand(src));
+ EmitOperand(dst.LowBits(), Operand(src));
}
-void X86_64Assembler::orl(Register dst, const Immediate& imm) {
+void X86_64Assembler::orl(CpuRegister dst, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst);
EmitComplex(1, Operand(dst), imm);
}
-void X86_64Assembler::xorl(Register dst, Register src) {
+void X86_64Assembler::xorl(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- rex(dst, src, 4);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x33);
- EmitOperand(dst, Operand(src));
+ EmitOperand(dst.LowBits(), Operand(src));
}
-void X86_64Assembler::rex_reg(Register &dst, size_t size) {
- Register src = kNoRegister;
- rex(dst, src, size);
-}
-
-void X86_64Assembler::rex_rm(Register &src, size_t size) {
- Register dst = kNoRegister;
- rex(dst, src, size);
-}
-
-void X86_64Assembler::rex(Register &dst, Register &src, size_t size) {
- uint8_t rex = 0;
+#if 0
+void X86_64Assembler::rex(bool force, bool w, Register* r, Register* x, Register* b) {
// REX.WRXB
// W - 64-bit operand
// R - MODRM.reg
// X - SIB.index
// B - MODRM.rm/SIB.base
- if (size == 8) {
+ uint8_t rex = force ? 0x40 : 0;
+ if (w) {
rex |= 0x48; // REX.W000
}
- if (dst >= Register::R8 && dst < Register::kNumberOfCpuRegisters) {
+ if (r != nullptr && *r >= Register::R8 && *r < Register::kNumberOfCpuRegisters) {
rex |= 0x44; // REX.0R00
- dst = static_cast<Register>(dst - 8);
+ *r = static_cast<Register>(*r - 8);
}
- if (src >= Register::R8 && src < Register::kNumberOfCpuRegisters) {
+ if (x != nullptr && *x >= Register::R8 && *x < Register::kNumberOfCpuRegisters) {
+ rex |= 0x42; // REX.00X0
+ *x = static_cast<Register>(*x - 8);
+ }
+ if (b != nullptr && *b >= Register::R8 && *b < Register::kNumberOfCpuRegisters) {
rex |= 0x41; // REX.000B
- src = static_cast<Register>(src - 8);
+ *b = static_cast<Register>(*b - 8);
}
if (rex != 0) {
EmitUint8(rex);
}
}
-void X86_64Assembler::addl(Register reg, const Immediate& imm) {
+void X86_64Assembler::rex_reg_mem(bool force, bool w, Register* dst, const Address& mem) {
+ // REX.WRXB
+ // W - 64-bit operand
+ // R - MODRM.reg
+ // X - SIB.index
+ // B - MODRM.rm/SIB.base
+ uint8_t rex = mem->rex();
+ if (force) {
+ rex |= 0x40; // REX.0000
+ }
+ if (w) {
+ rex |= 0x48; // REX.W000
+ }
+ if (dst != nullptr && *dst >= Register::R8 && *dst < Register::kNumberOfCpuRegisters) {
+ rex |= 0x44; // REX.0R00
+ *dst = static_cast<Register>(*dst - 8);
+ }
+ if (rex != 0) {
+ EmitUint8(rex);
+ }
+}
+
+void rex_mem_reg(bool force, bool w, Address* mem, Register* src);
+#endif
+
+void X86_64Assembler::addl(CpuRegister reg, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg);
EmitComplex(0, Operand(reg), imm);
}
-void X86_64Assembler::addq(Register reg, const Immediate& imm) {
+void X86_64Assembler::addq(CpuRegister reg, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x48); // REX.W
+ EmitRex64(reg);
EmitComplex(0, Operand(reg), imm);
}
-void X86_64Assembler::addl(const Address& address, Register reg) {
+void X86_64Assembler::addl(const Address& address, CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg, address);
EmitUint8(0x01);
- EmitOperand(reg, address);
+ EmitOperand(reg.LowBits(), address);
}
void X86_64Assembler::addl(const Address& address, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(address);
EmitComplex(0, address, imm);
}
-void X86_64Assembler::adcl(Register reg, const Immediate& imm) {
+void X86_64Assembler::subl(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitComplex(2, Operand(reg), imm);
-}
-
-
-void X86_64Assembler::adcl(Register dst, Register src) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x13);
- EmitOperand(dst, Operand(src));
-}
-
-
-void X86_64Assembler::adcl(Register dst, const Address& address) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x13);
- EmitOperand(dst, address);
-}
-
-
-void X86_64Assembler::subl(Register dst, Register src) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x2B);
- EmitOperand(dst, Operand(src));
+ EmitOperand(dst.LowBits(), Operand(src));
}
-void X86_64Assembler::subl(Register reg, const Immediate& imm) {
+void X86_64Assembler::subl(CpuRegister reg, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x48); // REX.W
+ EmitOptionalRex32(reg);
EmitComplex(5, Operand(reg), imm);
}
-void X86_64Assembler::subl(Register reg, const Address& address) {
+void X86_64Assembler::subl(CpuRegister reg, const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg, address);
EmitUint8(0x2B);
- EmitOperand(reg, address);
+ EmitOperand(reg.LowBits(), address);
}
@@ -998,39 +1056,44 @@
}
-void X86_64Assembler::idivl(Register reg) {
+void X86_64Assembler::idivl(CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg);
EmitUint8(0xF7);
- EmitUint8(0xF8 | reg);
+ EmitUint8(0xF8 | reg.LowBits());
}
-void X86_64Assembler::imull(Register dst, Register src) {
+void X86_64Assembler::imull(CpuRegister dst, CpuRegister src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(dst, src);
EmitUint8(0x0F);
EmitUint8(0xAF);
- EmitOperand(dst, Operand(src));
+ EmitOperand(dst.LowBits(), Operand(src));
}
-void X86_64Assembler::imull(Register reg, const Immediate& imm) {
+void X86_64Assembler::imull(CpuRegister reg, const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg);
EmitUint8(0x69);
- EmitOperand(reg, Operand(reg));
+ EmitOperand(reg.LowBits(), Operand(reg));
EmitImmediate(imm);
}
-void X86_64Assembler::imull(Register reg, const Address& address) {
+void X86_64Assembler::imull(CpuRegister reg, const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg, address);
EmitUint8(0x0F);
EmitUint8(0xAF);
- EmitOperand(reg, address);
+ EmitOperand(reg.LowBits(), address);
}
-void X86_64Assembler::imull(Register reg) {
+void X86_64Assembler::imull(CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg);
EmitUint8(0xF7);
EmitOperand(5, Operand(reg));
}
@@ -1038,13 +1101,15 @@
void X86_64Assembler::imull(const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(address);
EmitUint8(0xF7);
EmitOperand(5, address);
}
-void X86_64Assembler::mull(Register reg) {
+void X86_64Assembler::mull(CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg);
EmitUint8(0xF7);
EmitOperand(4, Operand(reg));
}
@@ -1052,106 +1117,56 @@
void X86_64Assembler::mull(const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(address);
EmitUint8(0xF7);
EmitOperand(4, address);
}
-void X86_64Assembler::sbbl(Register dst, Register src) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x1B);
- EmitOperand(dst, Operand(src));
-}
-
-void X86_64Assembler::sbbl(Register reg, const Immediate& imm) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitComplex(3, Operand(reg), imm);
-}
-
-
-void X86_64Assembler::sbbl(Register dst, const Address& address) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x1B);
- EmitOperand(dst, address);
-}
-
-
-void X86_64Assembler::incl(Register reg) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x40 + reg);
-}
-
-
-void X86_64Assembler::incl(const Address& address) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0xFF);
- EmitOperand(0, address);
-}
-
-
-void X86_64Assembler::decl(Register reg) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x48 + reg);
-}
-
-
-void X86_64Assembler::decl(const Address& address) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0xFF);
- EmitOperand(1, address);
-}
-
-
-void X86_64Assembler::shll(Register reg, const Immediate& imm) {
+void X86_64Assembler::shll(CpuRegister reg, const Immediate& imm) {
EmitGenericShift(4, reg, imm);
}
-void X86_64Assembler::shll(Register operand, Register shifter) {
+void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) {
EmitGenericShift(4, operand, shifter);
}
-void X86_64Assembler::shrl(Register reg, const Immediate& imm) {
+void X86_64Assembler::shrl(CpuRegister reg, const Immediate& imm) {
EmitGenericShift(5, reg, imm);
}
-void X86_64Assembler::shrl(Register operand, Register shifter) {
+void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) {
EmitGenericShift(5, operand, shifter);
}
-void X86_64Assembler::sarl(Register reg, const Immediate& imm) {
+void X86_64Assembler::sarl(CpuRegister reg, const Immediate& imm) {
EmitGenericShift(7, reg, imm);
}
-void X86_64Assembler::sarl(Register operand, Register shifter) {
+void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) {
EmitGenericShift(7, operand, shifter);
}
-void X86_64Assembler::shld(Register dst, Register src) {
+void X86_64Assembler::negl(CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitUint8(0x0F);
- EmitUint8(0xA5);
- EmitRegisterOperand(src, dst);
-}
-
-
-void X86_64Assembler::negl(Register reg) {
- AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg);
EmitUint8(0xF7);
EmitOperand(3, Operand(reg));
}
-void X86_64Assembler::notl(Register reg) {
+void X86_64Assembler::notl(CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg);
EmitUint8(0xF7);
- EmitUint8(0xD0 | reg);
+ EmitUint8(0xD0 | reg.LowBits());
}
@@ -1228,14 +1243,16 @@
}
-void X86_64Assembler::jmp(Register reg) {
+void X86_64Assembler::jmp(CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(reg);
EmitUint8(0xFF);
- EmitRegisterOperand(4, reg);
+ EmitRegisterOperand(4, reg.LowBits());
}
void X86_64Assembler::jmp(const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+ EmitOptionalRex32(address);
EmitUint8(0xFF);
EmitOperand(4, address);
}
@@ -1268,11 +1285,11 @@
}
-void X86_64Assembler::cmpxchgl(const Address& address, Register reg) {
+void X86_64Assembler::cmpxchgl(const Address& address, CpuRegister reg) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
EmitUint8(0x0F);
EmitUint8(0xB1);
- EmitOperand(reg, address);
+ EmitOperand(reg.LowBits(), address);
}
void X86_64Assembler::mfence() {
@@ -1289,19 +1306,12 @@
return this;
}
-void X86_64Assembler::AddImmediate(Register reg, const Immediate& imm) {
+void X86_64Assembler::AddImmediate(CpuRegister reg, const Immediate& imm) {
int value = imm.value();
- if (value > 0) {
- if (value == 1) {
- incl(reg);
- } else if (value != 0) {
+ if (value != 0) {
+ if (value > 0) {
addl(reg, imm);
- }
- } else if (value < 0) {
- value = -value;
- if (value == 1) {
- decl(reg);
- } else if (value != 0) {
+ } else {
subl(reg, Immediate(value));
}
}
@@ -1313,8 +1323,8 @@
int64_t constant = bit_cast<int64_t, double>(value);
pushq(Immediate(High32Bits(constant)));
pushq(Immediate(Low32Bits(constant)));
- movsd(dst, Address(RSP, 0));
- addq(RSP, Immediate(2 * kWordSize));
+ movsd(dst, Address(CpuRegister(RSP), 0));
+ addq(CpuRegister(RSP), Immediate(2 * kWordSize));
}
@@ -1372,7 +1382,7 @@
}
-void X86_64Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) {
+void X86_64Assembler::EmitOperand(uint8_t reg_or_opcode, const Operand& operand) {
CHECK_GE(reg_or_opcode, 0);
CHECK_LT(reg_or_opcode, 8);
const int length = operand.length_;
@@ -1392,9 +1402,9 @@
}
-void X86_64Assembler::EmitComplex(int reg_or_opcode,
- const Operand& operand,
- const Immediate& immediate) {
+void X86_64Assembler::EmitComplex(uint8_t reg_or_opcode,
+ const Operand& operand,
+ const Immediate& immediate) {
CHECK_GE(reg_or_opcode, 0);
CHECK_LT(reg_or_opcode, 8);
if (immediate.is_int8()) {
@@ -1402,7 +1412,7 @@
EmitUint8(0x83);
EmitOperand(reg_or_opcode, operand);
EmitUint8(immediate.value() & 0xFF);
- } else if (operand.IsRegister(RAX)) {
+ } else if (operand.IsRegister(CpuRegister(RAX))) {
// Use short form if the destination is eax.
EmitUint8(0x05 + (reg_or_opcode << 3));
EmitImmediate(immediate);
@@ -1434,7 +1444,7 @@
void X86_64Assembler::EmitGenericShift(int reg_or_opcode,
- Register reg,
+ CpuRegister reg,
const Immediate& imm) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
CHECK(imm.is_int8());
@@ -1450,14 +1460,89 @@
void X86_64Assembler::EmitGenericShift(int reg_or_opcode,
- Register operand,
- Register shifter) {
+ CpuRegister operand,
+ CpuRegister shifter) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- CHECK_EQ(shifter, RCX);
+ CHECK_EQ(shifter.AsRegister(), RCX);
EmitUint8(0xD3);
EmitOperand(reg_or_opcode, Operand(operand));
}
+void X86_64Assembler::EmitOptionalRex(bool force, bool w, bool r, bool x, bool b) {
+ // REX.WRXB
+ // W - 64-bit operand
+ // R - MODRM.reg
+ // X - SIB.index
+ // B - MODRM.rm/SIB.base
+ uint8_t rex = force ? 0x40 : 0;
+ if (w) {
+ rex |= 0x48; // REX.W000
+ }
+ if (r) {
+ rex |= 0x44; // REX.0R00
+ }
+ if (x) {
+ rex |= 0x42; // REX.00X0
+ }
+ if (b) {
+ rex |= 0x41; // REX.000B
+ }
+ if (rex != 0) {
+ EmitUint8(rex);
+ }
+}
+
+void X86_64Assembler::EmitOptionalRex32(CpuRegister reg) {
+ EmitOptionalRex(false, false, reg.NeedsRex(), false, false);
+}
+
+void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, CpuRegister src) {
+ EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
+}
+
+void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, XmmRegister src) {
+ EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
+}
+
+void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, XmmRegister src) {
+ EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
+}
+
+void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, CpuRegister src) {
+ EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex());
+}
+
+void X86_64Assembler::EmitOptionalRex32(const Operand& operand) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, const Operand& operand) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, const Operand& operand) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void X86_64Assembler::EmitRex64(CpuRegister reg) {
+ EmitOptionalRex(false, true, reg.NeedsRex(), false, false);
+}
+void X86_64Assembler::EmitRex64(CpuRegister dst, CpuRegister src) {
+ EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex());
+}
+
+void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) {
+ UNIMPLEMENTED(FATAL);
+}
+
+void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src) {
+ EmitOptionalRex(true, false, dst.NeedsRex(), false, src.NeedsRex());
+}
+
+void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) {
+ UNIMPLEMENTED(FATAL);
+}
+
void X86_64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
const std::vector<ManagedRegister>& spill_regs,
const ManagedRegisterEntrySpills& entry_spills) {
@@ -1466,25 +1551,26 @@
pushq(spill_regs.at(i).AsX86_64().AsCpuRegister());
}
// return address then method on stack
- addq(RSP, Immediate(-frame_size + (spill_regs.size() * kPointerSize) +
- kPointerSize /*method*/ + kPointerSize /*return address*/));
+ addq(CpuRegister(RSP), Immediate(-frame_size + (spill_regs.size() * kPointerSize) +
+ kPointerSize /*method*/ + kPointerSize /*return address*/));
pushq(method_reg.AsX86_64().AsCpuRegister());
for (size_t i = 0; i < entry_spills.size(); ++i) {
ManagedRegisterSpill spill = entry_spills.at(i);
if (spill.AsX86_64().IsCpuRegister()) {
if (spill.getSize() == 8) {
- movq(Address(RSP, frame_size + spill.getSpillOffset()), spill.AsX86_64().AsCpuRegister());
+ movq(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()),
+ spill.AsX86_64().AsCpuRegister());
} else {
CHECK_EQ(spill.getSize(), 4);
- movl(Address(RSP, frame_size + spill.getSpillOffset()), spill.AsX86_64().AsCpuRegister());
+ movl(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsCpuRegister());
}
} else {
if (spill.getSize() == 8) {
- movsd(Address(RSP, frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
+ movsd(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
} else {
CHECK_EQ(spill.getSize(), 4);
- movss(Address(RSP, frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
+ movss(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
}
}
}
@@ -1493,7 +1579,7 @@
void X86_64Assembler::RemoveFrame(size_t frame_size,
const std::vector<ManagedRegister>& spill_regs) {
CHECK_ALIGNED(frame_size, kStackAlignment);
- addq(RSP, Immediate(frame_size - (spill_regs.size() * kPointerSize) - kPointerSize));
+ addq(CpuRegister(RSP), Immediate(frame_size - (spill_regs.size() * kPointerSize) - kPointerSize));
for (size_t i = 0; i < spill_regs.size(); ++i) {
popq(spill_regs.at(i).AsX86_64().AsCpuRegister());
}
@@ -1502,12 +1588,12 @@
void X86_64Assembler::IncreaseFrameSize(size_t adjust) {
CHECK_ALIGNED(adjust, kStackAlignment);
- addq(RSP, Immediate(-adjust));
+ addq(CpuRegister(RSP), Immediate(-adjust));
}
void X86_64Assembler::DecreaseFrameSize(size_t adjust) {
CHECK_ALIGNED(adjust, kStackAlignment);
- addq(RSP, Immediate(adjust));
+ addq(CpuRegister(RSP), Immediate(adjust));
}
void X86_64Assembler::Store(FrameOffset offs, ManagedRegister msrc, size_t size) {
@@ -1517,28 +1603,28 @@
} else if (src.IsCpuRegister()) {
if (size == 4) {
CHECK_EQ(4u, size);
- movl(Address(RSP, offs), src.AsCpuRegister());
+ movl(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
} else {
CHECK_EQ(8u, size);
- movq(Address(RSP, offs), src.AsCpuRegister());
+ movq(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
}
} else if (src.IsRegisterPair()) {
CHECK_EQ(0u, size);
- movq(Address(RSP, offs), src.AsRegisterPairLow());
- movq(Address(RSP, FrameOffset(offs.Int32Value()+4)),
+ movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow());
+ movq(Address(CpuRegister(RSP), FrameOffset(offs.Int32Value()+4)),
src.AsRegisterPairHigh());
} else if (src.IsX87Register()) {
if (size == 4) {
- fstps(Address(RSP, offs));
+ fstps(Address(CpuRegister(RSP), offs));
} else {
- fstpl(Address(RSP, offs));
+ fstpl(Address(CpuRegister(RSP), offs));
}
} else {
CHECK(src.IsXmmRegister());
if (size == 4) {
- movss(Address(RSP, offs), src.AsXmmRegister());
+ movss(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
} else {
- movsd(Address(RSP, offs), src.AsXmmRegister());
+ movsd(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
}
}
}
@@ -1546,40 +1632,36 @@
void X86_64Assembler::StoreRef(FrameOffset dest, ManagedRegister msrc) {
X86_64ManagedRegister src = msrc.AsX86_64();
CHECK(src.IsCpuRegister());
- movq(Address(RSP, dest), src.AsCpuRegister());
+ movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
}
void X86_64Assembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) {
X86_64ManagedRegister src = msrc.AsX86_64();
CHECK(src.IsCpuRegister());
- movq(Address(RSP, dest), src.AsCpuRegister());
+ movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
}
void X86_64Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
- ManagedRegister) {
- movl(Address(RSP, dest), Immediate(imm)); // TODO(64) movq?
+ ManagedRegister) {
+ movl(Address(CpuRegister(RSP), dest), Immediate(imm)); // TODO(64) movq?
}
-void X86_64Assembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
- ManagedRegister) {
+void X86_64Assembler::StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm,
+ ManagedRegister) {
gs()->movl(Address::Absolute(dest, true), Immediate(imm)); // TODO(64) movq?
}
-void X86_64Assembler::StoreStackOffsetToThread(ThreadOffset thr_offs,
- FrameOffset fr_offs,
- ManagedRegister mscratch) {
+void X86_64Assembler::StoreStackOffsetToThread64(ThreadOffset<8> thr_offs,
+ FrameOffset fr_offs,
+ ManagedRegister mscratch) {
X86_64ManagedRegister scratch = mscratch.AsX86_64();
CHECK(scratch.IsCpuRegister());
- leaq(scratch.AsCpuRegister(), Address(RSP, fr_offs));
+ leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), fr_offs));
gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister());
}
-void X86_64Assembler::StoreStackPointerToThread(ThreadOffset thr_offs) {
- gs()->movq(Address::Absolute(thr_offs, true), RSP);
-}
-
-void X86_64Assembler::StoreLabelToThread(ThreadOffset thr_offs, Label* lbl) {
- gs()->movl(Address::Absolute(thr_offs, true), lbl); // TODO(64) movq?
+void X86_64Assembler::StoreStackPointerToThread64(ThreadOffset<8> thr_offs) {
+ gs()->movq(Address::Absolute(thr_offs, true), CpuRegister(RSP));
}
void X86_64Assembler::StoreSpanning(FrameOffset /*dst*/, ManagedRegister /*src*/,
@@ -1594,42 +1676,41 @@
} else if (dest.IsCpuRegister()) {
if (size == 4) {
CHECK_EQ(4u, size);
- movl(dest.AsCpuRegister(), Address(RSP, src));
+ movl(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
} else {
CHECK_EQ(8u, size);
- movq(dest.AsCpuRegister(), Address(RSP, src));
+ movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
}
} else if (dest.IsRegisterPair()) {
CHECK_EQ(0u, size);
- movq(dest.AsRegisterPairLow(), Address(RSP, src));
- movq(dest.AsRegisterPairHigh(), Address(RSP, FrameOffset(src.Int32Value()+4)));
+ movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src));
+ movq(dest.AsRegisterPairHigh(), Address(CpuRegister(RSP), FrameOffset(src.Int32Value()+4)));
} else if (dest.IsX87Register()) {
if (size == 4) {
- flds(Address(RSP, src));
+ flds(Address(CpuRegister(RSP), src));
} else {
- fldl(Address(RSP, src));
+ fldl(Address(CpuRegister(RSP), src));
}
} else {
CHECK(dest.IsXmmRegister());
if (size == 4) {
- movss(dest.AsXmmRegister(), Address(RSP, src));
+ movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
} else {
- movsd(dest.AsXmmRegister(), Address(RSP, src));
+ movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
}
}
}
-void X86_64Assembler::Load(ManagedRegister mdest, ThreadOffset src, size_t size) {
+void X86_64Assembler::LoadFromThread64(ManagedRegister mdest, ThreadOffset<8> src, size_t size) {
X86_64ManagedRegister dest = mdest.AsX86_64();
if (dest.IsNoRegister()) {
CHECK_EQ(0u, size);
} else if (dest.IsCpuRegister()) {
CHECK_EQ(4u, size);
- gs()->movq(dest.AsCpuRegister(), Address::Absolute(src, true));
+ gs()->movl(dest.AsCpuRegister(), Address::Absolute(src, true));
} else if (dest.IsRegisterPair()) {
CHECK_EQ(8u, size);
gs()->movq(dest.AsRegisterPairLow(), Address::Absolute(src, true));
- gs()->movq(dest.AsRegisterPairHigh(), Address::Absolute(ThreadOffset(src.Int32Value()+4), true));
} else if (dest.IsX87Register()) {
if (size == 4) {
gs()->flds(Address::Absolute(src, true));
@@ -1649,7 +1730,7 @@
void X86_64Assembler::LoadRef(ManagedRegister mdest, FrameOffset src) {
X86_64ManagedRegister dest = mdest.AsX86_64();
CHECK(dest.IsCpuRegister());
- movq(dest.AsCpuRegister(), Address(RSP, src));
+ movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
}
void X86_64Assembler::LoadRef(ManagedRegister mdest, ManagedRegister base,
@@ -1666,8 +1747,7 @@
movq(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs));
}
-void X86_64Assembler::LoadRawPtrFromThread(ManagedRegister mdest,
- ThreadOffset offs) {
+void X86_64Assembler::LoadRawPtrFromThread64(ManagedRegister mdest, ThreadOffset<8> offs) {
X86_64ManagedRegister dest = mdest.AsX86_64();
CHECK(dest.IsCpuRegister());
gs()->movq(dest.AsCpuRegister(), Address::Absolute(offs, true));
@@ -1678,7 +1758,7 @@
CHECK(size == 1 || size == 2) << size;
CHECK(reg.IsCpuRegister()) << reg;
if (size == 1) {
- movsxb(reg.AsCpuRegister(), reg.AsByteRegister());
+ movsxb(reg.AsCpuRegister(), reg.AsCpuRegister());
} else {
movsxw(reg.AsCpuRegister(), reg.AsCpuRegister());
}
@@ -1689,7 +1769,7 @@
CHECK(size == 1 || size == 2) << size;
CHECK(reg.IsCpuRegister()) << reg;
if (size == 1) {
- movzxb(reg.AsCpuRegister(), reg.AsByteRegister());
+ movzxb(reg.AsCpuRegister(), reg.AsCpuRegister());
} else {
movzxw(reg.AsCpuRegister(), reg.AsCpuRegister());
}
@@ -1703,17 +1783,17 @@
movq(dest.AsCpuRegister(), src.AsCpuRegister());
} else if (src.IsX87Register() && dest.IsXmmRegister()) {
// Pass via stack and pop X87 register
- subl(RSP, Immediate(16));
+ subl(CpuRegister(RSP), Immediate(16));
if (size == 4) {
CHECK_EQ(src.AsX87Register(), ST0);
- fstps(Address(RSP, 0));
- movss(dest.AsXmmRegister(), Address(RSP, 0));
+ fstps(Address(CpuRegister(RSP), 0));
+ movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
} else {
CHECK_EQ(src.AsX87Register(), ST0);
- fstpl(Address(RSP, 0));
- movsd(dest.AsXmmRegister(), Address(RSP, 0));
+ fstpl(Address(CpuRegister(RSP), 0));
+ movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
}
- addq(RSP, Immediate(16));
+ addq(CpuRegister(RSP), Immediate(16));
} else {
// TODO: x87, SSE
UNIMPLEMENTED(FATAL) << ": Move " << dest << ", " << src;
@@ -1725,22 +1805,22 @@
ManagedRegister mscratch) {
X86_64ManagedRegister scratch = mscratch.AsX86_64();
CHECK(scratch.IsCpuRegister());
- movl(scratch.AsCpuRegister(), Address(RSP, src));
- movl(Address(RSP, dest), scratch.AsCpuRegister());
+ movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), src));
+ movl(Address(CpuRegister(RSP), dest), scratch.AsCpuRegister());
}
-void X86_64Assembler::CopyRawPtrFromThread(FrameOffset fr_offs,
- ThreadOffset thr_offs,
- ManagedRegister mscratch) {
+void X86_64Assembler::CopyRawPtrFromThread64(FrameOffset fr_offs,
+ ThreadOffset<8> thr_offs,
+ ManagedRegister mscratch) {
X86_64ManagedRegister scratch = mscratch.AsX86_64();
CHECK(scratch.IsCpuRegister());
gs()->movq(scratch.AsCpuRegister(), Address::Absolute(thr_offs, true));
Store(fr_offs, scratch, 8);
}
-void X86_64Assembler::CopyRawPtrToThread(ThreadOffset thr_offs,
- FrameOffset fr_offs,
- ManagedRegister mscratch) {
+void X86_64Assembler::CopyRawPtrToThread64(ThreadOffset<8> thr_offs,
+ FrameOffset fr_offs,
+ ManagedRegister mscratch) {
X86_64ManagedRegister scratch = mscratch.AsX86_64();
CHECK(scratch.IsCpuRegister());
Load(scratch, fr_offs, 8);
@@ -1771,17 +1851,17 @@
ManagedRegister scratch, size_t size) {
CHECK(scratch.IsNoRegister());
CHECK_EQ(size, 4u);
- pushq(Address(RSP, src));
+ pushq(Address(CpuRegister(RSP), src));
popq(Address(dest_base.AsX86_64().AsCpuRegister(), dest_offset));
}
void X86_64Assembler::Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
ManagedRegister mscratch, size_t size) {
- Register scratch = mscratch.AsX86_64().AsCpuRegister();
+ CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
CHECK_EQ(size, 4u);
- movq(scratch, Address(RSP, src_base));
+ movq(scratch, Address(CpuRegister(RSP), src_base));
movq(scratch, Address(scratch, src_offset));
- movq(Address(RSP, dest), scratch);
+ movq(Address(CpuRegister(RSP), dest), scratch);
}
void X86_64Assembler::Copy(ManagedRegister dest, Offset dest_offset,
@@ -1795,10 +1875,10 @@
void X86_64Assembler::Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
ManagedRegister mscratch, size_t size) {
- Register scratch = mscratch.AsX86_64().AsCpuRegister();
+ CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
CHECK_EQ(size, 4u);
CHECK_EQ(dest.Int32Value(), src.Int32Value());
- movq(scratch, Address(RSP, src));
+ movq(scratch, Address(CpuRegister(RSP), src));
pushq(Address(scratch, src_offset));
popq(Address(scratch, dest_offset));
}
@@ -1818,7 +1898,7 @@
// Use out_reg as indicator of NULL
in_reg = out_reg;
// TODO: movzwl
- movl(in_reg.AsCpuRegister(), Address(RSP, sirt_offset));
+ movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), sirt_offset));
}
CHECK(in_reg.IsCpuRegister());
CHECK(out_reg.IsCpuRegister());
@@ -1830,10 +1910,10 @@
}
testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister());
j(kZero, &null_arg);
- leaq(out_reg.AsCpuRegister(), Address(RSP, sirt_offset));
+ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), sirt_offset));
Bind(&null_arg);
} else {
- leaq(out_reg.AsCpuRegister(), Address(RSP, sirt_offset));
+ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), sirt_offset));
}
}
@@ -1845,13 +1925,13 @@
CHECK(scratch.IsCpuRegister());
if (null_allowed) {
Label null_arg;
- movl(scratch.AsCpuRegister(), Address(RSP, sirt_offset));
+ movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), sirt_offset));
testl(scratch.AsCpuRegister(), scratch.AsCpuRegister());
j(kZero, &null_arg);
- leaq(scratch.AsCpuRegister(), Address(RSP, sirt_offset));
+ leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), sirt_offset));
Bind(&null_arg);
} else {
- leaq(scratch.AsCpuRegister(), Address(RSP, sirt_offset));
+ leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), sirt_offset));
}
Store(out_off, scratch, 8);
}
@@ -1889,35 +1969,42 @@
}
void X86_64Assembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) {
- Register scratch = mscratch.AsX86_64().AsCpuRegister();
- movq(scratch, Address(RSP, base));
+ CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
+ movq(scratch, Address(CpuRegister(RSP), base));
call(Address(scratch, offset));
}
-void X86_64Assembler::Call(ThreadOffset offset, ManagedRegister /*mscratch*/) {
+void X86_64Assembler::CallFromThread64(ThreadOffset<8> offset, ManagedRegister /*mscratch*/) {
gs()->call(Address::Absolute(offset, true));
}
void X86_64Assembler::GetCurrentThread(ManagedRegister tr) {
- gs()->movq(tr.AsX86_64().AsCpuRegister(),
- Address::Absolute(Thread::SelfOffset(), true));
+ gs()->movq(tr.AsX86_64().AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true));
}
-void X86_64Assembler::GetCurrentThread(FrameOffset offset,
- ManagedRegister mscratch) {
+void X86_64Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister mscratch) {
X86_64ManagedRegister scratch = mscratch.AsX86_64();
- gs()->movq(scratch.AsCpuRegister(), Address::Absolute(Thread::SelfOffset(), true));
- movq(Address(RSP, offset), scratch.AsCpuRegister());
+ gs()->movq(scratch.AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true));
+ movq(Address(CpuRegister(RSP), offset), scratch.AsCpuRegister());
}
+// Slowpath entered when Thread::Current()->_exception is non-null
+class X86_64ExceptionSlowPath FINAL : public SlowPath {
+ public:
+ explicit X86_64ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {}
+ virtual void Emit(Assembler *sp_asm) OVERRIDE;
+ private:
+ const size_t stack_adjust_;
+};
+
void X86_64Assembler::ExceptionPoll(ManagedRegister /*scratch*/, size_t stack_adjust) {
- X86ExceptionSlowPath* slow = new X86ExceptionSlowPath(stack_adjust);
+ X86_64ExceptionSlowPath* slow = new X86_64ExceptionSlowPath(stack_adjust);
buffer_.EnqueueSlowPath(slow);
- gs()->cmpl(Address::Absolute(Thread::ExceptionOffset(), true), Immediate(0));
+ gs()->cmpl(Address::Absolute(Thread::ExceptionOffset<8>(), true), Immediate(0));
j(kNotEqual, slow->Entry());
}
-void X86ExceptionSlowPath::Emit(Assembler *sasm) {
+void X86_64ExceptionSlowPath::Emit(Assembler *sasm) {
X86_64Assembler* sp_asm = down_cast<X86_64Assembler*>(sasm);
#define __ sp_asm->
__ Bind(&entry_);
@@ -1925,27 +2012,14 @@
if (stack_adjust_ != 0) { // Fix up the frame.
__ DecreaseFrameSize(stack_adjust_);
}
- // Pass exception as argument in RAX
- __ gs()->movq(RAX, Address::Absolute(Thread::ExceptionOffset(), true)); // TODO(64): Pass argument via RDI
- __ gs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(pDeliverException), true));
+ // Pass exception as argument in RDI
+ __ gs()->movq(CpuRegister(RDI), Address::Absolute(Thread::ExceptionOffset<8>(), true));
+ __ gs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), true));
// this call should never return
__ int3();
#undef __
}
-static const char* kRegisterNames[] = {
- "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
-};
-
-std::ostream& operator<<(std::ostream& os, const Register& rhs) {
- if (rhs >= RAX && rhs <= R15) {
- os << kRegisterNames[rhs];
- } else {
- os << "Register[" << static_cast<int>(rhs) << "]";
- }
- return os;
-}
} // namespace x86_64
} // namespace art
diff --git a/compiler/utils/x86_64/assembler_x86_64.h b/compiler/utils/x86_64/assembler_x86_64.h
index d48ba72..1d42d89 100644
--- a/compiler/utils/x86_64/assembler_x86_64.h
+++ b/compiler/utils/x86_64/assembler_x86_64.h
@@ -80,25 +80,30 @@
return value;
}
- bool IsRegister(Register reg) const {
+ bool IsRegister(CpuRegister reg) const {
+ CHECK(!reg.NeedsRex()) << "TODO: rex support:" << reg;
return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only.
- && ((encoding_[0] & 0x07) == reg); // Register codes match.
+ && ((encoding_[0] & 0x07) == reg.LowBits()); // Register codes match.
}
protected:
// Operand can be sub classed (e.g: Address).
Operand() : length_(0) { }
- void SetModRM(int mod, Register rm) {
+ void SetModRM(int mod, CpuRegister rm) {
CHECK_EQ(mod & ~3, 0);
- encoding_[0] = (mod << 6) | rm;
+ CHECK(!rm.NeedsRex());
+ encoding_[0] = (mod << 6) | static_cast<uint8_t>(rm.AsRegister());
length_ = 1;
}
- void SetSIB(ScaleFactor scale, Register index, Register base) {
+ void SetSIB(ScaleFactor scale, CpuRegister index, CpuRegister base) {
+ CHECK(!index.NeedsRex()) << "TODO: rex support: " << index;
+ CHECK(!base.NeedsRex()) << "TODO: rex support: " << base;
CHECK_EQ(length_, 1);
CHECK_EQ(scale & ~3, 0);
- encoding_[1] = (scale << 6) | (index << 3) | base;
+ encoding_[1] = (scale << 6) | (static_cast<uint8_t>(index.AsRegister()) << 3) |
+ static_cast<uint8_t>(base.AsRegister());
length_ = 2;
}
@@ -117,9 +122,8 @@
private:
byte length_;
byte encoding_[6];
- byte padding_;
- explicit Operand(Register reg) { SetModRM(3, reg); }
+ explicit Operand(CpuRegister reg) { SetModRM(3, reg); }
// Get the operand encoding byte at the given index.
uint8_t encoding_at(int index) const {
@@ -136,77 +140,85 @@
class Address : public Operand {
public:
- Address(Register base, int32_t disp) {
+ Address(CpuRegister base, int32_t disp) {
Init(base, disp);
}
- Address(Register base, Offset disp) {
+ Address(CpuRegister base, Offset disp) {
Init(base, disp.Int32Value());
}
- Address(Register base, FrameOffset disp) {
- CHECK_EQ(base, RSP);
- Init(RSP, disp.Int32Value());
+ Address(CpuRegister base, FrameOffset disp) {
+ CHECK_EQ(base.AsRegister(), RSP);
+ Init(CpuRegister(RSP), disp.Int32Value());
}
- Address(Register base, MemberOffset disp) {
+ Address(CpuRegister base, MemberOffset disp) {
Init(base, disp.Int32Value());
}
- void Init(Register base, int32_t disp) {
- if (disp == 0 && base != RBP) {
+ void Init(CpuRegister base, int32_t disp) {
+ if (disp == 0 && base.AsRegister() != RBP) {
SetModRM(0, base);
- if (base == RSP) SetSIB(TIMES_1, RSP, base);
+ if (base.AsRegister() == RSP) {
+ SetSIB(TIMES_1, CpuRegister(RSP), base);
+ }
} else if (disp >= -128 && disp <= 127) {
SetModRM(1, base);
- if (base == RSP) SetSIB(TIMES_1, RSP, base);
+ if (base.AsRegister() == RSP) {
+ SetSIB(TIMES_1, CpuRegister(RSP), base);
+ }
SetDisp8(disp);
} else {
SetModRM(2, base);
- if (base == RSP) SetSIB(TIMES_1, RSP, base);
+ if (base.AsRegister() == RSP) {
+ SetSIB(TIMES_1, CpuRegister(RSP), base);
+ }
SetDisp32(disp);
}
}
- Address(Register index, ScaleFactor scale, int32_t disp) {
- CHECK_NE(index, RSP); // Illegal addressing mode.
- SetModRM(0, RSP);
- SetSIB(scale, index, RBP);
+ Address(CpuRegister index, ScaleFactor scale, int32_t disp) {
+ CHECK_NE(index.AsRegister(), RSP); // Illegal addressing mode.
+ SetModRM(0, CpuRegister(RSP));
+ SetSIB(scale, index, CpuRegister(RBP));
SetDisp32(disp);
}
- Address(Register base, Register index, ScaleFactor scale, int32_t disp) {
- CHECK_NE(index, RSP); // Illegal addressing mode.
- if (disp == 0 && base != RBP) {
- SetModRM(0, RSP);
+ Address(CpuRegister base, CpuRegister index, ScaleFactor scale, int32_t disp) {
+ CHECK_NE(index.AsRegister(), RSP); // Illegal addressing mode.
+ if (disp == 0 && base.AsRegister() != RBP) {
+ SetModRM(0, CpuRegister(RSP));
SetSIB(scale, index, base);
} else if (disp >= -128 && disp <= 127) {
- SetModRM(1, RSP);
+ SetModRM(1, CpuRegister(RSP));
SetSIB(scale, index, base);
SetDisp8(disp);
} else {
- SetModRM(2, RSP);
+ SetModRM(2, CpuRegister(RSP));
SetSIB(scale, index, base);
SetDisp32(disp);
}
}
- static Address Absolute(uword addr, bool has_rip = false) {
+ // If no_rip is true then the Absolute address isn't RIP relative.
+ static Address Absolute(uword addr, bool no_rip = false) {
Address result;
- if (has_rip) {
- result.SetModRM(0, RSP);
- result.SetSIB(TIMES_1, RSP, RBP);
+ if (no_rip) {
+ result.SetModRM(0, CpuRegister(RSP));
+ result.SetSIB(TIMES_1, CpuRegister(RSP), CpuRegister(RBP));
result.SetDisp32(addr);
} else {
- result.SetModRM(0, RBP);
+ result.SetModRM(0, CpuRegister(RBP));
result.SetDisp32(addr);
}
return result;
}
- static Address Absolute(ThreadOffset addr, bool has_rip = false) {
- return Absolute(addr.Int32Value(), has_rip);
+ // If no_rip is true then the Absolute address isn't RIP relative.
+ static Address Absolute(ThreadOffset<8> addr, bool no_rip = false) {
+ return Absolute(addr.Int32Value(), no_rip);
}
private:
@@ -216,7 +228,7 @@
};
-class X86_64Assembler : public Assembler {
+class X86_64Assembler FINAL : public Assembler {
public:
X86_64Assembler() {}
virtual ~X86_64Assembler() {}
@@ -224,56 +236,51 @@
/*
* Emit Machine Instructions.
*/
- void call(Register reg);
+ void call(CpuRegister reg);
void call(const Address& address);
void call(Label* label);
- void pushq(Register reg);
+ void pushq(CpuRegister reg);
void pushq(const Address& address);
void pushq(const Immediate& imm);
- void popq(Register reg);
+ void popq(CpuRegister reg);
void popq(const Address& address);
- void movq(Register dst, const Immediate& src);
- void movl(Register dst, const Immediate& src);
- void movq(Register dst, Register src);
- void movl(Register dst, Register src);
+ void movq(CpuRegister dst, const Immediate& src);
+ void movl(CpuRegister dst, const Immediate& src);
+ void movq(CpuRegister dst, CpuRegister src);
+ void movl(CpuRegister dst, CpuRegister src);
- void movq(Register dst, const Address& src);
- void movl(Register dst, const Address& src);
- void movq(const Address& dst, Register src);
- void movl(const Address& dst, Register src);
+ void movq(CpuRegister dst, const Address& src);
+ void movl(CpuRegister dst, const Address& src);
+ void movq(const Address& dst, CpuRegister src);
+ void movl(const Address& dst, CpuRegister src);
void movl(const Address& dst, const Immediate& imm);
- void movl(const Address& dst, Label* lbl);
- void movzxb(Register dst, ByteRegister src);
- void movzxb(Register dst, const Address& src);
- void movsxb(Register dst, ByteRegister src);
- void movsxb(Register dst, const Address& src);
- void movb(Register dst, const Address& src);
- void movb(const Address& dst, ByteRegister src);
+ void movzxb(CpuRegister dst, CpuRegister src);
+ void movzxb(CpuRegister dst, const Address& src);
+ void movsxb(CpuRegister dst, CpuRegister src);
+ void movsxb(CpuRegister dst, const Address& src);
+ void movb(CpuRegister dst, const Address& src);
+ void movb(const Address& dst, CpuRegister src);
void movb(const Address& dst, const Immediate& imm);
- void movzxw(Register dst, Register src);
- void movzxw(Register dst, const Address& src);
- void movsxw(Register dst, Register src);
- void movsxw(Register dst, const Address& src);
- void movw(Register dst, const Address& src);
- void movw(const Address& dst, Register src);
+ void movzxw(CpuRegister dst, CpuRegister src);
+ void movzxw(CpuRegister dst, const Address& src);
+ void movsxw(CpuRegister dst, CpuRegister src);
+ void movsxw(CpuRegister dst, const Address& src);
+ void movw(CpuRegister dst, const Address& src);
+ void movw(const Address& dst, CpuRegister src);
- void leaq(Register dst, const Address& src);
-
- void cmovl(Condition condition, Register dst, Register src);
-
- void setb(Condition condition, Register dst);
+ void leaq(CpuRegister dst, const Address& src);
void movss(XmmRegister dst, const Address& src);
void movss(const Address& dst, XmmRegister src);
void movss(XmmRegister dst, XmmRegister src);
- void movd(XmmRegister dst, Register src);
- void movd(Register dst, XmmRegister src);
+ void movd(XmmRegister dst, CpuRegister src);
+ void movd(CpuRegister dst, XmmRegister src);
void addss(XmmRegister dst, XmmRegister src);
void addss(XmmRegister dst, const Address& src);
@@ -297,17 +304,17 @@
void divsd(XmmRegister dst, XmmRegister src);
void divsd(XmmRegister dst, const Address& src);
- void cvtsi2ss(XmmRegister dst, Register src);
- void cvtsi2sd(XmmRegister dst, Register src);
+ void cvtsi2ss(XmmRegister dst, CpuRegister src);
+ void cvtsi2sd(XmmRegister dst, CpuRegister src);
- void cvtss2si(Register dst, XmmRegister src);
+ void cvtss2si(CpuRegister dst, XmmRegister src);
void cvtss2sd(XmmRegister dst, XmmRegister src);
- void cvtsd2si(Register dst, XmmRegister src);
+ void cvtsd2si(CpuRegister dst, XmmRegister src);
void cvtsd2ss(XmmRegister dst, XmmRegister src);
- void cvttss2si(Register dst, XmmRegister src);
- void cvttsd2si(Register dst, XmmRegister src);
+ void cvttss2si(CpuRegister dst, XmmRegister src);
+ void cvttsd2si(CpuRegister dst, XmmRegister src);
void cvtdq2pd(XmmRegister dst, XmmRegister src);
@@ -344,77 +351,62 @@
void fcos();
void fptan();
- void xchgl(Register dst, Register src);
- void xchgl(Register reg, const Address& address);
+ void xchgl(CpuRegister dst, CpuRegister src);
+ void xchgl(CpuRegister reg, const Address& address);
- void cmpl(Register reg, const Immediate& imm);
- void cmpl(Register reg0, Register reg1);
- void cmpl(Register reg, const Address& address);
+ void cmpl(CpuRegister reg, const Immediate& imm);
+ void cmpl(CpuRegister reg0, CpuRegister reg1);
+ void cmpl(CpuRegister reg, const Address& address);
- void cmpl(const Address& address, Register reg);
+ void cmpl(const Address& address, CpuRegister reg);
void cmpl(const Address& address, const Immediate& imm);
- void testl(Register reg1, Register reg2);
- void testl(Register reg, const Immediate& imm);
+ void testl(CpuRegister reg1, CpuRegister reg2);
+ void testl(CpuRegister reg, const Immediate& imm);
- void andl(Register dst, const Immediate& imm);
- void andl(Register dst, Register src);
+ void andl(CpuRegister dst, const Immediate& imm);
+ void andl(CpuRegister dst, CpuRegister src);
- void orl(Register dst, const Immediate& imm);
- void orl(Register dst, Register src);
+ void orl(CpuRegister dst, const Immediate& imm);
+ void orl(CpuRegister dst, CpuRegister src);
- void xorl(Register dst, Register src);
+ void xorl(CpuRegister dst, CpuRegister src);
- void addl(Register dst, Register src);
- void addq(Register reg, const Immediate& imm);
- void addl(Register reg, const Immediate& imm);
- void addl(Register reg, const Address& address);
+ void addl(CpuRegister dst, CpuRegister src);
+ void addq(CpuRegister reg, const Immediate& imm);
+ void addl(CpuRegister reg, const Immediate& imm);
+ void addl(CpuRegister reg, const Address& address);
- void addl(const Address& address, Register reg);
+ void addl(const Address& address, CpuRegister reg);
void addl(const Address& address, const Immediate& imm);
- void adcl(Register dst, Register src);
- void adcl(Register reg, const Immediate& imm);
- void adcl(Register dst, const Address& address);
-
- void subl(Register dst, Register src);
- void subl(Register reg, const Immediate& imm);
- void subl(Register reg, const Address& address);
+ void subl(CpuRegister dst, CpuRegister src);
+ void subl(CpuRegister reg, const Immediate& imm);
+ void subl(CpuRegister reg, const Address& address);
void cdq();
- void idivl(Register reg);
+ void idivl(CpuRegister reg);
- void imull(Register dst, Register src);
- void imull(Register reg, const Immediate& imm);
- void imull(Register reg, const Address& address);
+ void imull(CpuRegister dst, CpuRegister src);
+ void imull(CpuRegister reg, const Immediate& imm);
+ void imull(CpuRegister reg, const Address& address);
- void imull(Register reg);
+ void imull(CpuRegister reg);
void imull(const Address& address);
- void mull(Register reg);
+ void mull(CpuRegister reg);
void mull(const Address& address);
- void sbbl(Register dst, Register src);
- void sbbl(Register reg, const Immediate& imm);
- void sbbl(Register reg, const Address& address);
+ void shll(CpuRegister reg, const Immediate& imm);
+ void shll(CpuRegister operand, CpuRegister shifter);
+ void shrl(CpuRegister reg, const Immediate& imm);
+ void shrl(CpuRegister operand, CpuRegister shifter);
+ void sarl(CpuRegister reg, const Immediate& imm);
+ void sarl(CpuRegister operand, CpuRegister shifter);
- void incl(Register reg);
- void incl(const Address& address);
-
- void decl(Register reg);
- void decl(const Address& address);
-
- void shll(Register reg, const Immediate& imm);
- void shll(Register operand, Register shifter);
- void shrl(Register reg, const Immediate& imm);
- void shrl(Register operand, Register shifter);
- void sarl(Register reg, const Immediate& imm);
- void sarl(Register operand, Register shifter);
- void shld(Register dst, Register src);
-
- void negl(Register reg);
- void notl(Register reg);
+ void negl(CpuRegister reg);
+ void notl(CpuRegister reg);
void enter(const Immediate& imm);
void leave();
@@ -428,12 +420,12 @@
void j(Condition condition, Label* label);
- void jmp(Register reg);
+ void jmp(CpuRegister reg);
void jmp(const Address& address);
void jmp(Label* label);
X86_64Assembler* lock();
- void cmpxchgl(const Address& address, Register reg);
+ void cmpxchgl(const Address& address, CpuRegister reg);
void mfence();
@@ -443,7 +435,7 @@
// Macros for High-level operations.
//
- void AddImmediate(Register reg, const Immediate& imm);
+ void AddImmediate(CpuRegister reg, const Immediate& imm);
void LoadDoubleConstant(XmmRegister dst, double value);
@@ -452,7 +444,7 @@
void DoubleAbs(XmmRegister reg);
- void LockCmpxchgl(const Address& address, Register reg) {
+ void LockCmpxchgl(const Address& address, CpuRegister reg) {
lock()->cmpxchgl(address, reg);
}
@@ -468,109 +460,99 @@
//
// Emit code that will create an activation on the stack
- virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
- const std::vector<ManagedRegister>& callee_save_regs,
- const ManagedRegisterEntrySpills& entry_spills);
+ void BuildFrame(size_t frame_size, ManagedRegister method_reg,
+ const std::vector<ManagedRegister>& callee_save_regs,
+ const ManagedRegisterEntrySpills& entry_spills) OVERRIDE;
// Emit code that will remove an activation from the stack
- virtual void RemoveFrame(size_t frame_size,
- const std::vector<ManagedRegister>& callee_save_regs);
+ void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs)
+ OVERRIDE;
- virtual void IncreaseFrameSize(size_t adjust);
- virtual void DecreaseFrameSize(size_t adjust);
+ void IncreaseFrameSize(size_t adjust) OVERRIDE;
+ void DecreaseFrameSize(size_t adjust) OVERRIDE;
// Store routines
- virtual void Store(FrameOffset offs, ManagedRegister src, size_t size);
- virtual void StoreRef(FrameOffset dest, ManagedRegister src);
- virtual void StoreRawPtr(FrameOffset dest, ManagedRegister src);
+ void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE;
+ void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE;
+ void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE;
- virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
- ManagedRegister scratch);
+ void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
- virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm,
- ManagedRegister scratch);
+ void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister scratch)
+ OVERRIDE;
- virtual void StoreStackOffsetToThread(ThreadOffset thr_offs,
- FrameOffset fr_offs,
- ManagedRegister scratch);
+ void StoreStackOffsetToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs,
+ ManagedRegister scratch) OVERRIDE;
- virtual void StoreStackPointerToThread(ThreadOffset thr_offs);
+ void StoreStackPointerToThread64(ThreadOffset<8> thr_offs) OVERRIDE;
- void StoreLabelToThread(ThreadOffset thr_offs, Label* lbl);
-
- virtual void StoreSpanning(FrameOffset dest, ManagedRegister src,
- FrameOffset in_off, ManagedRegister scratch);
+ void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off,
+ ManagedRegister scratch) OVERRIDE;
// Load routines
- virtual void Load(ManagedRegister dest, FrameOffset src, size_t size);
+ void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE;
- virtual void Load(ManagedRegister dest, ThreadOffset src, size_t size);
+ void LoadFromThread64(ManagedRegister dest, ThreadOffset<8> src, size_t size) OVERRIDE;
- virtual void LoadRef(ManagedRegister dest, FrameOffset src);
+ void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE;
- virtual void LoadRef(ManagedRegister dest, ManagedRegister base,
- MemberOffset offs);
+ void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE;
- virtual void LoadRawPtr(ManagedRegister dest, ManagedRegister base,
- Offset offs);
+ void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE;
- virtual void LoadRawPtrFromThread(ManagedRegister dest,
- ThreadOffset offs);
+ void LoadRawPtrFromThread64(ManagedRegister dest, ThreadOffset<8> offs) OVERRIDE;
// Copying routines
- virtual void Move(ManagedRegister dest, ManagedRegister src, size_t size);
+ void Move(ManagedRegister dest, ManagedRegister src, size_t size);
- virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs,
- ManagedRegister scratch);
+ void CopyRawPtrFromThread64(FrameOffset fr_offs, ThreadOffset<8> thr_offs,
+ ManagedRegister scratch) OVERRIDE;
- virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs,
- ManagedRegister scratch);
+ void CopyRawPtrToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs, ManagedRegister scratch)
+ OVERRIDE;
- virtual void CopyRef(FrameOffset dest, FrameOffset src,
- ManagedRegister scratch);
+ void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE;
- virtual void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src,
- ManagedRegister scratch, size_t size);
+ void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch,
+ size_t size) OVERRIDE;
- virtual void Copy(ManagedRegister dest, Offset dest_offset,
- ManagedRegister src, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset,
+ ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
- ManagedRegister scratch, size_t size);
+ void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset,
+ ManagedRegister scratch, size_t size) OVERRIDE;
- virtual void MemoryBarrier(ManagedRegister);
+ void MemoryBarrier(ManagedRegister) OVERRIDE;
// Sign extension
- virtual void SignExtend(ManagedRegister mreg, size_t size);
+ void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Zero extension
- virtual void ZeroExtend(ManagedRegister mreg, size_t size);
+ void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE;
// Exploit fast access in managed code to Thread::Current()
- virtual void GetCurrentThread(ManagedRegister tr);
- virtual void GetCurrentThread(FrameOffset dest_offset,
- ManagedRegister scratch);
+ void GetCurrentThread(ManagedRegister tr) OVERRIDE;
+ void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE;
// Set up out_reg to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed. in_reg holds a possibly stale reference
// that can be used to avoid loading the SIRT entry to see if the value is
// NULL.
- virtual void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset,
- ManagedRegister in_reg, bool null_allowed);
+ void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset, ManagedRegister in_reg,
+ bool null_allowed) OVERRIDE;
// Set up out_off to hold a Object** into the SIRT, or to be NULL if the
// value is null and null_allowed.
- virtual void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset,
- ManagedRegister scratch, bool null_allowed);
+ void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset, ManagedRegister scratch,
+ bool null_allowed) OVERRIDE;
// src holds a SIRT entry (Object**) load this into dst
virtual void LoadReferenceFromSirt(ManagedRegister dst,
@@ -578,40 +560,57 @@
// Heap::VerifyObject on src. In some cases (such as a reference to this) we
// know that src may not be null.
- virtual void VerifyObject(ManagedRegister src, bool could_be_null);
- virtual void VerifyObject(FrameOffset src, bool could_be_null);
+ void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE;
+ void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE;
// Call to address held at [base+offset]
- virtual void Call(ManagedRegister base, Offset offset,
- ManagedRegister scratch);
- virtual void Call(FrameOffset base, Offset offset,
- ManagedRegister scratch);
- virtual void Call(ThreadOffset offset, ManagedRegister scratch);
+ void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE;
+ void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE;
+ void CallFromThread64(ThreadOffset<8> offset, ManagedRegister scratch) OVERRIDE;
// Generate code to check if Thread::Current()->exception_ is non-null
// and branch to a ExceptionSlowPath if it is.
- virtual void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust);
+ void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE;
private:
- inline void EmitUint8(uint8_t value);
- inline void EmitInt32(int32_t value);
- inline void EmitRegisterOperand(int rm, int reg);
- inline void EmitXmmRegisterOperand(int rm, XmmRegister reg);
- inline void EmitFixup(AssemblerFixup* fixup);
- inline void EmitOperandSizeOverride();
+ void EmitUint8(uint8_t value);
+ void EmitInt32(int32_t value);
+ void EmitRegisterOperand(uint8_t rm, uint8_t reg);
+ void EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg);
+ void EmitFixup(AssemblerFixup* fixup);
+ void EmitOperandSizeOverride();
- void EmitOperand(int rm, const Operand& operand);
+ void EmitOperand(uint8_t rm, const Operand& operand);
void EmitImmediate(const Immediate& imm);
- void EmitComplex(int rm, const Operand& operand, const Immediate& immediate);
+ void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate);
void EmitLabel(Label* label, int instruction_size);
void EmitLabelLink(Label* label);
void EmitNearLabelLink(Label* label);
- void EmitGenericShift(int rm, Register reg, const Immediate& imm);
- void EmitGenericShift(int rm, Register operand, Register shifter);
- void rex(Register &dst, Register &src, size_t size = 4);
- void rex_reg(Register &dst, size_t size = 4);
- void rex_rm(Register &src, size_t size = 4);
+ void EmitGenericShift(int rm, CpuRegister reg, const Immediate& imm);
+ void EmitGenericShift(int rm, CpuRegister operand, CpuRegister shifter);
+
+ // If any input is not false, output the necessary rex prefix.
+ void EmitOptionalRex(bool force, bool w, bool r, bool x, bool b);
+
+ // Emit a rex prefix byte if necessary for reg. ie if reg is a register in the range R8 to R15.
+ void EmitOptionalRex32(CpuRegister reg);
+ void EmitOptionalRex32(CpuRegister dst, CpuRegister src);
+ void EmitOptionalRex32(XmmRegister dst, XmmRegister src);
+ void EmitOptionalRex32(CpuRegister dst, XmmRegister src);
+ void EmitOptionalRex32(XmmRegister dst, CpuRegister src);
+ void EmitOptionalRex32(const Operand& operand);
+ void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
+ void EmitOptionalRex32(XmmRegister dst, const Operand& operand);
+
+ // Emit a REX.W prefix plus necessary register bit encodings.
+ void EmitRex64(CpuRegister reg);
+ void EmitRex64(CpuRegister dst, CpuRegister src);
+ void EmitRex64(CpuRegister dst, const Operand& operand);
+
+ // Emit a REX prefix to normalize byte registers plus necessary register bit encodings.
+ void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src);
+ void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand);
DISALLOW_COPY_AND_ASSIGN(X86_64Assembler);
};
@@ -624,14 +623,14 @@
buffer_.Emit<int32_t>(value);
}
-inline void X86_64Assembler::EmitRegisterOperand(int rm, int reg) {
+inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) {
CHECK_GE(rm, 0);
CHECK_LT(rm, 8);
buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg);
}
-inline void X86_64Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) {
- EmitRegisterOperand(rm, static_cast<Register>(reg));
+inline void X86_64Assembler::EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) {
+ EmitRegisterOperand(rm, static_cast<uint8_t>(reg.AsFloatRegister()));
}
inline void X86_64Assembler::EmitFixup(AssemblerFixup* fixup) {
@@ -642,15 +641,6 @@
EmitUint8(0x66);
}
-// Slowpath entered when Thread::Current()->_exception is non-null
-class X86ExceptionSlowPath : public SlowPath {
- public:
- explicit X86ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {}
- virtual void Emit(Assembler *sp_asm);
- private:
- const size_t stack_adjust_;
-};
-
} // namespace x86_64
} // namespace art
diff --git a/compiler/utils/x86_64/constants_x86_64.h b/compiler/utils/x86_64/constants_x86_64.h
index 3340802..58a0379 100644
--- a/compiler/utils/x86_64/constants_x86_64.h
+++ b/compiler/utils/x86_64/constants_x86_64.h
@@ -27,30 +27,37 @@
namespace art {
namespace x86_64 {
-enum ByteRegister {
- AL = 0,
- CL = 1,
- DL = 2,
- BL = 3,
- AH = 4,
- CH = 5,
- DH = 6,
- BH = 7,
- kNoByteRegister = -1 // Signals an illegal register.
+class CpuRegister {
+ public:
+ explicit CpuRegister(Register r) : reg_(r) {}
+ Register AsRegister() const {
+ return reg_;
+ }
+ uint8_t LowBits() const {
+ return reg_ & 7;
+ }
+ bool NeedsRex() const {
+ return reg_ > 7;
+ }
+ private:
+ const Register reg_;
};
+std::ostream& operator<<(std::ostream& os, const CpuRegister& reg);
-
-enum XmmRegister {
- _XMM0 = 0,
- _XMM1 = 1,
- _XMM2 = 2,
- _XMM3 = 3,
- _XMM4 = 4,
- _XMM5 = 5,
- _XMM6 = 6,
- _XMM7 = 7,
- kNumberOfXmmRegisters = 8,
- kNoXmmRegister = -1 // Signals an illegal register.
+class XmmRegister {
+ public:
+ explicit XmmRegister(FloatRegister r) : reg_(r) {}
+ FloatRegister AsFloatRegister() const {
+ return reg_;
+ }
+ uint8_t LowBits() const {
+ return reg_ & 7;
+ }
+ bool NeedsRex() const {
+ return reg_ > 7;
+ }
+ private:
+ const FloatRegister reg_;
};
std::ostream& operator<<(std::ostream& os, const XmmRegister& reg);
diff --git a/compiler/utils/x86_64/managed_register_x86_64.cc b/compiler/utils/x86_64/managed_register_x86_64.cc
index 057a894..b8c2db2 100644
--- a/compiler/utils/x86_64/managed_register_x86_64.cc
+++ b/compiler/utils/x86_64/managed_register_x86_64.cc
@@ -60,8 +60,8 @@
CHECK(other.IsValidManagedRegister());
if (Equals(other)) return true;
if (IsRegisterPair()) {
- Register low = AsRegisterPairLow();
- Register high = AsRegisterPairHigh();
+ Register low = AsRegisterPairLow().AsRegister();
+ Register high = AsRegisterPairHigh().AsRegister();
return X86_64ManagedRegister::FromCpuRegister(low).Overlaps(other) ||
X86_64ManagedRegister::FromCpuRegister(high).Overlaps(other);
}
@@ -94,11 +94,11 @@
if (!IsValidManagedRegister()) {
os << "No Register";
} else if (IsXmmRegister()) {
- os << "XMM: " << static_cast<int>(AsXmmRegister());
+ os << "XMM: " << static_cast<int>(AsXmmRegister().AsFloatRegister());
} else if (IsX87Register()) {
os << "X87: " << static_cast<int>(AsX87Register());
} else if (IsCpuRegister()) {
- os << "CPU: " << static_cast<int>(AsCpuRegister());
+ os << "CPU: " << static_cast<int>(AsCpuRegister().AsRegister());
} else if (IsRegisterPair()) {
os << "Pair: " << AsRegisterPairLow() << ", " << AsRegisterPairHigh();
} else {
diff --git a/compiler/utils/x86_64/managed_register_x86_64.h b/compiler/utils/x86_64/managed_register_x86_64.h
index d68c59d..822659f 100644
--- a/compiler/utils/x86_64/managed_register_x86_64.h
+++ b/compiler/utils/x86_64/managed_register_x86_64.h
@@ -46,8 +46,8 @@
const int kNumberOfCpuRegIds = kNumberOfCpuRegisters;
const int kNumberOfCpuAllocIds = kNumberOfCpuRegisters;
-const int kNumberOfXmmRegIds = kNumberOfXmmRegisters;
-const int kNumberOfXmmAllocIds = kNumberOfXmmRegisters;
+const int kNumberOfXmmRegIds = kNumberOfFloatRegisters;
+const int kNumberOfXmmAllocIds = kNumberOfFloatRegisters;
const int kNumberOfX87RegIds = kNumberOfX87Registers;
const int kNumberOfX87AllocIds = kNumberOfX87Registers;
@@ -87,20 +87,14 @@
// There is a one-to-one mapping between ManagedRegister and register id.
class X86_64ManagedRegister : public ManagedRegister {
public:
- ByteRegister AsByteRegister() const {
+ CpuRegister AsCpuRegister() const {
CHECK(IsCpuRegister());
- CHECK_LT(AsCpuRegister(), RSP); // RSP, RBP, ESI and RDI cannot be encoded as byte registers.
- return static_cast<ByteRegister>(id_);
- }
-
- Register AsCpuRegister() const {
- CHECK(IsCpuRegister());
- return static_cast<Register>(id_);
+ return CpuRegister(static_cast<Register>(id_));
}
XmmRegister AsXmmRegister() const {
CHECK(IsXmmRegister());
- return static_cast<XmmRegister>(id_ - kNumberOfCpuRegIds);
+ return XmmRegister(static_cast<FloatRegister>(id_ - kNumberOfCpuRegIds));
}
X87Register AsX87Register() const {
@@ -109,13 +103,13 @@
(kNumberOfCpuRegIds + kNumberOfXmmRegIds));
}
- Register AsRegisterPairLow() const {
+ CpuRegister AsRegisterPairLow() const {
CHECK(IsRegisterPair());
// Appropriate mapping of register ids allows to use AllocIdLow().
return FromRegId(AllocIdLow()).AsCpuRegister();
}
- Register AsRegisterPairHigh() const {
+ CpuRegister AsRegisterPairHigh() const {
CHECK(IsRegisterPair());
// Appropriate mapping of register ids allows to use AllocIdHigh().
return FromRegId(AllocIdHigh()).AsCpuRegister();
@@ -157,8 +151,7 @@
return FromRegId(r);
}
- static X86_64ManagedRegister FromXmmRegister(XmmRegister r) {
- CHECK_NE(r, kNoXmmRegister);
+ static X86_64ManagedRegister FromXmmRegister(FloatRegister r) {
return FromRegId(r + kNumberOfCpuRegIds);
}