| commit | 8ba4de1a5684686447a578bdc425321fd3bccca6 | [log] [tgz] |
|---|---|---|
| author | Artem Serov <artem.serov@linaro.org> | Wed Dec 04 21:10:23 2019 +0000 |
| committer | Ulyana Trafimovich <skvadrik@google.com> | Thu Feb 04 06:16:33 2021 +0000 |
| tree | 20c24450b24950266ccc235306e3ad2109c57497 | |
| parent | 32bf6d39bc020cacfc655ce60630f4a0da3b45cf [diff] |
ART: Implement predicated SIMD vectorization. This CL brings support for predicated execution for auto-vectorizer and implements arm64 SVE vector backend. This version passes all the VIXL simulator-runnable tests in SVE mode with checker off (as all VecOp CHECKs need to be adjusted for an extra input) and all tests in NEON mode. Test: art SIMD tests on VIXL simulator. Test: art tests on FVP (steps in test/README.arm_fvp.md) Change-Id: Ib78bde31a15e6713d875d6668ad4458f5519605f