tree 20c24450b24950266ccc235306e3ad2109c57497
parent 32bf6d39bc020cacfc655ce60630f4a0da3b45cf
author Artem Serov <artem.serov@linaro.org> 1575493823 +0000
committer Ulyana Trafimovich <skvadrik@google.com> 1612419393 +0000

ART: Implement predicated SIMD vectorization.

This CL brings support for predicated execution for
auto-vectorizer and implements arm64 SVE vector backend.

This version passes all the VIXL simulator-runnable tests in
SVE mode with checker off (as all VecOp CHECKs need to be
adjusted for an extra input) and all tests in NEON mode.

Test: art SIMD tests on VIXL simulator.
Test: art tests on FVP (steps in test/README.arm_fvp.md)

Change-Id: Ib78bde31a15e6713d875d6668ad4458f5519605f