Multi-target Codegen cleanup
Trying to get a bit more consistent in the abstraction layer
naming:
genXXX -> high-level codegen, for ex: genIGet()
opXXX -> instruction-level output, for ex: opRegImm()
Also more fleshing out of the Mips codegen support.
Change-Id: Iafdf397cbb5015bfe3aa2c38680d96c7c05f8bc4
diff --git a/src/compiler/codegen/CodegenFactory.cc b/src/compiler/codegen/CodegenFactory.cc
index 232cbf5..a42ebc3 100644
--- a/src/compiler/codegen/CodegenFactory.cc
+++ b/src/compiler/codegen/CodegenFactory.cc
@@ -63,7 +63,7 @@
{
rlSrc = oatUpdateLoc(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
- genRegCopy(cUnit, reg1, rlSrc.lowReg);
+ opRegCopy(cUnit, reg1, rlSrc.lowReg);
} else {
DCHECK(rlSrc.location == kLocDalvikFrame);
loadWordDisp(cUnit, rSP, oatSRegOffset(cUnit, rlSrc.sRegLow), reg1);
@@ -92,7 +92,7 @@
{
rlSrc = oatUpdateLocWide(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
- genRegCopyWide(cUnit, regLo, regHi, rlSrc.lowReg, rlSrc.highReg);
+ opRegCopyWide(cUnit, regLo, regHi, rlSrc.lowReg, rlSrc.highReg);
} else {
DCHECK(rlSrc.location == kLocDalvikFrame);
loadBaseDispWide(cUnit, NULL, rSP,
@@ -142,7 +142,7 @@
(rlDest.location == kLocPhysReg)) {
// Src is live/promoted or Dest has assigned reg.
rlDest = oatEvalLoc(cUnit, rlDest, kAnyReg, false);
- genRegCopy(cUnit, rlDest.lowReg, rlSrc.lowReg);
+ opRegCopy(cUnit, rlDest.lowReg, rlSrc.lowReg);
} else {
// Just re-assign the registers. Dest gets Src's regs
rlDest.lowReg = rlSrc.lowReg;
@@ -202,7 +202,7 @@
(rlDest.location == kLocPhysReg)) {
// Src is live or promoted or Dest has assigned reg.
rlDest = oatEvalLoc(cUnit, rlDest, kAnyReg, false);
- genRegCopyWide(cUnit, rlDest.lowReg, rlDest.highReg,
+ opRegCopyWide(cUnit, rlDest.lowReg, rlDest.highReg,
rlSrc.lowReg, rlSrc.highReg);
} else {
// Just re-assign the registers. Dest gets Src's regs
@@ -249,7 +249,7 @@
{
int regCardBase = oatAllocTemp(cUnit);
int regCardNo = oatAllocTemp(cUnit);
- LIR* branchOver = genCmpImmBranch(cUnit, kCondEq, valReg, 0);
+ LIR* branchOver = opCmpImmBranch(cUnit, kCondEq, valReg, 0, NULL);
loadWordDisp(cUnit, rSELF, Thread::CardTableOffset().Int32Value(),
regCardBase);
opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, GC_CARD_SHIFT);
@@ -270,7 +270,7 @@
void loadCurrMethodDirect(CompilationUnit *cUnit, int rTgt)
{
#if defined(METHOD_IN_REG)
- genRegCopy(cUnit, rTgt, rMETHOD);
+ opRegCopy(cUnit, rTgt, rMETHOD);
#else
loadWordDisp(cUnit, rSP, 0, rTgt);
#endif
diff --git a/src/compiler/codegen/CodegenUtil.cc b/src/compiler/codegen/CodegenUtil.cc
index 96a9b21..9e7f8c8 100644
--- a/src/compiler/codegen/CodegenUtil.cc
+++ b/src/compiler/codegen/CodegenUtil.cc
@@ -304,7 +304,7 @@
} else {
std::string op_name(buildInsnString(EncodingMap[lir->opcode].name, lir, baseAddr));
std::string op_operands(buildInsnString(EncodingMap[lir->opcode].fmt, lir, baseAddr));
- LOG(INFO) << StringPrintf("%p (%04x): %-9s%s%s", baseAddr + offset, offset,
+ LOG(INFO) << StringPrintf("%05x: %-9s%s%s", (intptr_t)baseAddr + offset,
op_name.c_str(), op_operands.c_str(), lir->flags.isNop ? "(nop)" : "");
}
break;
@@ -402,7 +402,7 @@
std::replace(line.begin(), line.end(), ';', '_');
LOG(INFO) << line;
for (uint32_t i = 0; i < cUnit->mappingTable.size(); i+=2) {
- line = StringPrintf(" {0x%08x, 0x%04x},",
+ line = StringPrintf(" {0x%05x, 0x%04x},",
cUnit->mappingTable[i], cUnit->mappingTable[i+1]);
LOG(INFO) << line;
}
diff --git a/src/compiler/codegen/GenCommon.cc b/src/compiler/codegen/GenCommon.cc
index 511c47b..66950d2 100644
--- a/src/compiler/codegen/GenCommon.cc
+++ b/src/compiler/codegen/GenCommon.cc
@@ -23,7 +23,7 @@
*/
#if defined(TARGET_ARM)
-LIR* genIT(CompilationUnit* cUnit, ArmConditionCode cond, const char* guide);
+LIR* opIT(CompilationUnit* cUnit, ArmConditionCode cond, const char* guide);
#endif
LIR* callRuntimeHelper(CompilationUnit* cUnit, int reg)
@@ -45,7 +45,7 @@
/* Generate unconditional branch instructions */
-LIR* genUnconditionalBranch(CompilationUnit* cUnit, LIR* target)
+LIR* opUnconditionalBranch(CompilationUnit* cUnit, LIR* target)
{
LIR* branch = opNone(cUnit, kOpUncondBr);
branch->target = (LIR*) target;
@@ -55,15 +55,6 @@
// FIXME: need to do some work to split out targets with
// condition codes and those without
#if defined(TARGET_ARM) || defined(TARGET_X86)
-/* Generate conditional branch instructions */
-LIR* genConditionalBranch(CompilationUnit* cUnit, ConditionCode cond,
- LIR* target)
-{
- LIR* branch = opCondBranch(cUnit, cond);
- branch->target = (LIR*) target;
- return branch;
-}
-
LIR* genCheck(CompilationUnit* cUnit, ConditionCode cCode, MIR* mir,
ThrowKind kind)
{
@@ -71,7 +62,7 @@
tgt->opcode = kPseudoThrowTarget;
tgt->operands[0] = kind;
tgt->operands[1] = mir ? mir->offset : 0;
- LIR* branch = genConditionalBranch(cUnit, cCode, tgt);
+ LIR* branch = opCondBranch(cUnit, cCode, tgt);
// Remember branch target - will process later
oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, (intptr_t)tgt);
return branch;
@@ -87,10 +78,9 @@
tgt->operands[1] = mir->offset;
LIR* branch;
if (cCode == kCondAl) {
- branch = genUnconditionalBranch(cUnit, tgt);
+ branch = opUnconditionalBranch(cUnit, tgt);
} else {
- branch = genCmpImmBranch(cUnit, cCode, reg, immVal);
- branch->target = (LIR*)tgt;
+ branch = opCmpImmBranch(cUnit, cCode, reg, immVal, tgt);
}
// Remember branch target - will process later
oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, (intptr_t)tgt);
@@ -118,10 +108,10 @@
tgt->operands[2] = reg1;
tgt->operands[3] = reg2;
#if defined(TARGET_MIPS)
- LIR* branch = genCompareBranch(cUnit, cCode, reg1, reg2);
+ LIR* branch = opCmpBranch(cUnit, cCode, reg1, reg2, tgt);
#else
opRegReg(cUnit, kOpCmp, reg1, reg2);
- LIR* branch = genConditionalBranch(cUnit, cCode, tgt);
+ LIR* branch = opCondBranch(cUnit, cCode, tgt);
#endif
// Remember branch target - will process later
oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, (intptr_t)tgt);
@@ -159,13 +149,13 @@
LOG(FATAL) << "Unexpected opcode " << (int)opcode;
}
#if defined(TARGET_MIPS)
- LIR* branch = genCompareBranch(cUnit, cond, rlSrc1.lowReg, rlSrc2.lowReg);
- branch->target = &labelList[bb->taken->id];
+ opCmpBranch(cUnit, cond, rlSrc1.lowReg, rlSrc2.lowReg,
+ &labelList[bb->taken->id]);
#else
opRegReg(cUnit, kOpCmp, rlSrc1.lowReg, rlSrc2.lowReg);
- genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]);
+ opCondBranch(cUnit, cond, &labelList[bb->taken->id]);
#endif
- genUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
+ opUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
}
void genCompareZeroAndBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
@@ -198,13 +188,12 @@
LOG(FATAL) << "Unexpected opcode " << (int)opcode;
}
#if defined(TARGET_MIPS)
- LIR* branch = genCmpImmBranch(cUnit, cond, rlSrc.lowReg, 0);
- branch->target = &labelList[bb->taken->id];
+ opCmpImmBranch(cUnit, cond, rlSrc.lowReg, 0, &labelList[bb->taken->id]);
#else
opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0);
- genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]);
+ opCondBranch(cUnit, cond, &labelList[bb->taken->id]);
#endif
- genUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
+ opUnconditionalBranch(cUnit, &labelList[bb->fallThrough->id]);
}
void genIntToLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
@@ -212,7 +201,7 @@
{
RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
if (rlSrc.location == kLocPhysReg) {
- genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
+ opRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
} else {
loadValueDirect(cUnit, rlSrc, rlResult.lowReg);
}
@@ -361,13 +350,12 @@
#if defined(TARGET_ARM)
// Combine sub & test using sub setflags encoding here
newLIR3(cUnit, kThumb2SubsRRI12, rIdx, rIdx, 1);
- LIR* branch = opCondBranch(cUnit, kCondGe);
+ opCondBranch(cUnit, kCondGe, target);
#else
oatFreeTemp(cUnit, rVal);
opRegImm(cUnit, kOpSub, rIdx, 1);
- LIR* branch = genCmpImmBranch(cUnit, kCondGe, rIdx, 0);
+ opCmpImmBranch(cUnit, kCondGe, rIdx, 0, target);
#endif
- branch->target = (LIR*)target;
} else if (!isRange) {
// TUNING: interleave
for (unsigned int i = 0; i < dInsn->vA; i++) {
@@ -434,14 +422,14 @@
// rBase now points at appropriate static storage base (Class*)
// or NULL if not initialized. Check for NULL and call helper if NULL.
// TUNING: fast path should fall through
- LIR* branchOver = genCmpImmBranch(cUnit, kCondNe, rBase, 0);
+ LIR* branchOver = opCmpImmBranch(cUnit, kCondNe, rBase, 0, NULL);
int rTgt = loadHelper(cUnit, OFFSETOF_MEMBER(Thread,
pInitializeStaticStorage));
loadConstant(cUnit, rARG0, ssbIndex);
callRuntimeHelper(cUnit, rTgt);
#if defined(TARGET_MIPS)
// For Arm, rRET0 = rARG0 = rBASE, for Mips, we need to copy
- genRegCopy(cUnit, rBase, rRET0);
+ opRegCopy(cUnit, rBase, rRET0);
#endif
LIR* skipTarget = newLIR0(cUnit, kPseudoTargetLabel);
skipTarget->defMask = ENCODE_ALL;
@@ -541,14 +529,14 @@
// rBase now points at appropriate static storage base (Class*)
// or NULL if not initialized. Check for NULL and call helper if NULL.
// TUNING: fast path should fall through
- LIR* branchOver = genCmpImmBranch(cUnit, kCondNe, rBase, 0);
+ LIR* branchOver = opCmpImmBranch(cUnit, kCondNe, rBase, 0, NULL);
int rTgt = loadHelper(cUnit, OFFSETOF_MEMBER(Thread,
pInitializeStaticStorage));
loadConstant(cUnit, rARG0, ssbIndex);
callRuntimeHelper(cUnit, rTgt);
#if defined(TARGET_MIPS)
// For Arm, rRET0 = rARG0 = rBASE, for Mips, we need to copy
- genRegCopy(cUnit, rBase, rRET0);
+ opRegCopy(cUnit, rBase, rRET0);
#endif
LIR* skipTarget = newLIR0(cUnit, kPseudoTargetLabel);
skipTarget->defMask = ENCODE_ALL;
@@ -596,7 +584,7 @@
// Debugging routine - if null target, branch to DebugMe
void genShowTarget(CompilationUnit* cUnit)
{
- LIR* branchOver = genCmpImmBranch(cUnit, kCondNe, rLINK, 0);
+ LIR* branchOver = opCmpImmBranch(cUnit, kCondNe, rLINK, 0, NULL);
loadWordDisp(cUnit, rSELF,
OFFSETOF_MEMBER(Thread, pDebugMe), rLINK);
LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
@@ -639,7 +627,7 @@
OFFSETOF_MEMBER(Thread, pUpdateDebuggerFromCode),
rSUSPEND);
}
- genUnconditionalBranch(cUnit, resumeLab);
+ opUnconditionalBranch(cUnit, resumeLab);
}
}
@@ -662,8 +650,8 @@
break;
case kThrowArrayBounds:
if (v2 != rARG0) {
- genRegCopy(cUnit, rARG0, v1);
- genRegCopy(cUnit, rARG1, v2);
+ opRegCopy(cUnit, rARG0, v1);
+ opRegCopy(cUnit, rARG1, v2);
} else {
if (v1 == rARG1) {
#if defined(TARGET_ARM)
@@ -671,15 +659,15 @@
#else
int rTmp = oatAllocTemp(cUnit);
#endif
- genRegCopy(cUnit, rTmp, v1);
- genRegCopy(cUnit, rARG1, v2);
- genRegCopy(cUnit, rARG0, rTmp);
+ opRegCopy(cUnit, rTmp, v1);
+ opRegCopy(cUnit, rARG1, v2);
+ opRegCopy(cUnit, rARG0, rTmp);
#if !(defined(TARGET_ARM))
oatFreeTemp(cUnit, rTmp);
#endif
} else {
- genRegCopy(cUnit, rARG1, v2);
- genRegCopy(cUnit, rARG0, v1);
+ opRegCopy(cUnit, rARG1, v2);
+ opRegCopy(cUnit, rARG0, v1);
}
}
funcOffset = OFFSETOF_MEMBER(Thread, pThrowArrayBoundsFromCode);
@@ -694,12 +682,12 @@
OFFSETOF_MEMBER(Thread, pThrowVerificationErrorFromCode);
break;
case kThrowNegArraySize:
- genRegCopy(cUnit, rARG0, v1);
+ opRegCopy(cUnit, rARG0, v1);
funcOffset =
OFFSETOF_MEMBER(Thread, pThrowNegArraySizeFromCode);
break;
case kThrowNoSuchMethod:
- genRegCopy(cUnit, rARG0, v1);
+ opRegCopy(cUnit, rARG0, v1);
funcOffset =
OFFSETOF_MEMBER(Thread, pThrowNoSuchMethodFromCode);
break;
@@ -859,7 +847,7 @@
// Resolved type returned in rRET0.
int rTgt = loadHelper(cUnit, OFFSETOF_MEMBER(Thread,
pInitializeTypeAndVerifyAccessFromCode));
- genRegCopy(cUnit, rARG1, mReg);
+ opRegCopy(cUnit, rARG1, mReg);
loadConstant(cUnit, rARG0, type_idx);
callRuntimeHelper(cUnit, rTgt);
RegLocation rlResult = oatGetReturn(cUnit);
@@ -877,17 +865,18 @@
type_idx) || SLOW_TYPE_PATH) {
// Slow path, at runtime test if type is null and if so initialize
oatFlushAllRegs(cUnit);
- LIR* branch1 = genCmpImmBranch(cUnit, kCondEq, rlResult.lowReg, 0);
+ LIR* branch1 = opCmpImmBranch(cUnit, kCondEq, rlResult.lowReg, 0,
+ NULL);
// Resolved, store and hop over following code
storeValue(cUnit, rlDest, rlResult);
- LIR* branch2 = genUnconditionalBranch(cUnit,0);
+ LIR* branch2 = opUnconditionalBranch(cUnit,0);
// TUNING: move slow path to end & remove unconditional branch
LIR* target1 = newLIR0(cUnit, kPseudoTargetLabel);
target1->defMask = ENCODE_ALL;
// Call out to helper, which will return resolved type in rARG0
int rTgt = loadHelper(cUnit, OFFSETOF_MEMBER(Thread,
pInitializeTypeFromCode));
- genRegCopy(cUnit, rARG1, mReg);
+ opRegCopy(cUnit, rARG1, mReg);
loadConstant(cUnit, rARG0, type_idx);
callRuntimeHelper(cUnit, rTgt);
RegLocation rlResult = oatGetReturn(cUnit);
@@ -928,13 +917,13 @@
genBarrier(cUnit);
// For testing, always force through helper
if (!EXERCISE_SLOWEST_STRING_PATH) {
- genIT(cUnit, kArmCondEq, "T");
+ opIT(cUnit, kArmCondEq, "T");
}
- genRegCopy(cUnit, rARG0, rARG2); // .eq
+ opRegCopy(cUnit, rARG0, rARG2); // .eq
opReg(cUnit, kOpBlx, rTgt); // .eq, helper(Method*, string_idx)
#else
- LIR* branch = genCmpImmBranch(cUnit, kCondNe, rRET0, 0);
- genRegCopy(cUnit, rARG0, rARG2); // .eq
+ LIR* branch = opCmpImmBranch(cUnit, kCondNe, rRET0, 0, NULL);
+ opRegCopy(cUnit, rARG0, rARG2); // .eq
opReg(cUnit, kOpBlx, rTgt);
LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
target->defMask = ENCODE_ALL;
@@ -997,7 +986,7 @@
pInitializeTypeAndVerifyAccessFromCode));
loadConstant(cUnit, rARG0, type_idx);
callRuntimeHelper(cUnit, rTgt); // InitializeTypeAndVerifyAccess(idx, method)
- genRegCopy(cUnit, classReg, rRET0); // Align usage with fast path
+ opRegCopy(cUnit, classReg, rRET0); // Align usage with fast path
loadValueDirectFixed(cUnit, rlSrc, rARG0); // rARG0 <= ref
} else {
// Load dex cache entry into classReg (rARG2)
@@ -1012,14 +1001,14 @@
if (!cUnit->compiler->CanAssumeTypeIsPresentInDexCache(
cUnit->dex_cache, type_idx)) {
// Need to test presence of type in dex cache at runtime
- LIR* hopBranch = genCmpImmBranch(cUnit, kCondNe, classReg, 0);
+ LIR* hopBranch = opCmpImmBranch(cUnit, kCondNe, classReg, 0, NULL);
// Not resolved
// Call out to helper, which will return resolved type in rRET0
int rTgt = loadHelper(cUnit, OFFSETOF_MEMBER(Thread,
pInitializeTypeFromCode));
loadConstant(cUnit, rARG0, type_idx);
callRuntimeHelper(cUnit, rTgt); // InitializeTypeFromCode(idx, method)
- genRegCopy(cUnit, rARG2, rRET0); // Align usage with fast path
+ opRegCopy(cUnit, rARG2, rRET0); // Align usage with fast path
loadValueDirectFixed(cUnit, rlSrc, rARG0); /* reload Ref */
// Rejoin code paths
LIR* hopTarget = newLIR0(cUnit, kPseudoTargetLabel);
@@ -1028,7 +1017,7 @@
}
}
/* rARG0 is ref, rARG2 is class. If ref==null, use directly as bool result */
- LIR* branch1 = genCmpImmBranch(cUnit, kCondEq, rARG0, 0);
+ LIR* branch1 = opCmpImmBranch(cUnit, kCondEq, rARG0, 0, NULL);
/* load object->clazz */
DCHECK_EQ(Object::ClassOffset().Int32Value(), 0);
loadWordDisp(cUnit, rARG0, Object::ClassOffset().Int32Value(), rARG1);
@@ -1038,9 +1027,9 @@
#if defined(TARGET_ARM)
opRegReg(cUnit, kOpCmp, rARG1, rARG2); // Same?
genBarrier(cUnit);
- genIT(cUnit, kArmCondEq, "EE"); // if-convert the test
+ opIT(cUnit, kArmCondEq, "EE"); // if-convert the test
loadConstant(cUnit, rARG0, 1); // .eq case - load true
- genRegCopy(cUnit, rARG0, rARG2); // .ne case - arg0 <= class
+ opRegCopy(cUnit, rARG0, rARG2); // .ne case - arg0 <= class
opReg(cUnit, kOpBlx, rTgt); // .ne case: helper(class, ref->class)
genBarrier(cUnit);
oatClobberCalleeSave(cUnit);
@@ -1075,7 +1064,7 @@
pInitializeTypeAndVerifyAccessFromCode));
loadConstant(cUnit, rARG0, type_idx);
callRuntimeHelper(cUnit, rTgt); // InitializeTypeAndVerifyAccess(idx, method)
- genRegCopy(cUnit, classReg, rRET0); // Align usage with fast path
+ opRegCopy(cUnit, classReg, rRET0); // Align usage with fast path
} else {
// Load dex cache entry into classReg (rARG2)
loadWordDisp(cUnit, rARG1,
@@ -1088,13 +1077,13 @@
if (!cUnit->compiler->CanAssumeTypeIsPresentInDexCache(
cUnit->dex_cache, type_idx)) {
// Need to test presence of type in dex cache at runtime
- LIR* hopBranch = genCmpImmBranch(cUnit, kCondNe, classReg, 0);
+ LIR* hopBranch = opCmpImmBranch(cUnit, kCondNe, classReg, 0, NULL);
// Not resolved
// Call out to helper, which will return resolved type in rARG0
int rTgt = loadHelper(cUnit, OFFSETOF_MEMBER(Thread, pInitializeTypeFromCode));
loadConstant(cUnit, rARG0, type_idx);
callRuntimeHelper(cUnit, rTgt); // InitializeTypeFromCode(idx, method)
- genRegCopy(cUnit, classReg, rARG0); // Align usage with fast path
+ opRegCopy(cUnit, classReg, rARG0); // Align usage with fast path
// Rejoin code paths
LIR* hopTarget = newLIR0(cUnit, kPseudoTargetLabel);
hopTarget->defMask = ENCODE_ALL;
@@ -1104,7 +1093,7 @@
// At this point, classReg (rARG2) has class
loadValueDirectFixed(cUnit, rlSrc, rARG0); // rARG0 <= ref
/* Null is OK - continue */
- LIR* branch1 = genCmpImmBranch(cUnit, kCondEq, rARG0, 0);
+ LIR* branch1 = opCmpImmBranch(cUnit, kCondEq, rARG0, 0, NULL);
/* load object->clazz */
DCHECK_EQ(Object::ClassOffset().Int32Value(), 0);
loadWordDisp(cUnit, rARG0, Object::ClassOffset().Int32Value(), rARG1);
@@ -1112,13 +1101,13 @@
int rTgt = loadHelper(cUnit, OFFSETOF_MEMBER(Thread,
pCheckCastFromCode));
#if defined(TARGET_MIPS)
- LIR* branch2 = genCompareBranch(cUnit, kCondEq, rARG1, classReg);
+ LIR* branch2 = opCmpBranch(cUnit, kCondEq, rARG1, classReg, NULL);
#else
opRegReg(cUnit, kOpCmp, rARG1, classReg);
- LIR* branch2 = opCondBranch(cUnit, kCondEq); /* If equal, trivial yes */
+ LIR* branch2 = opCondBranch(cUnit, kCondEq, NULL); /* If eq, trivial yes */
#endif
- genRegCopy(cUnit, rARG0, rARG1);
- genRegCopy(cUnit, rARG1, rARG2);
+ opRegCopy(cUnit, rARG0, rARG1);
+ opRegCopy(cUnit, rARG1, rARG2);
callRuntimeHelper(cUnit, rTgt);
/* branch target here */
LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
@@ -1173,7 +1162,7 @@
regPtr = rlArray.lowReg;
} else {
regPtr = oatAllocTemp(cUnit);
- genRegCopy(cUnit, regPtr, rlArray.lowReg);
+ opRegCopy(cUnit, regPtr, rlArray.lowReg);
}
if (!(mir->optimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
@@ -1290,7 +1279,7 @@
regPtr = rlArray.lowReg;
} else {
regPtr = oatAllocTemp(cUnit);
- genRegCopy(cUnit, regPtr, rlArray.lowReg);
+ opRegCopy(cUnit, regPtr, rlArray.lowReg);
}
/* null object? */
@@ -1357,7 +1346,7 @@
// The longs may overlap - use intermediate temp if so
if (rlResult.lowReg == rlSrc1.highReg) {
int tReg = oatAllocTemp(cUnit);
- genRegCopy(cUnit, tReg, rlSrc1.highReg);
+ opRegCopy(cUnit, tReg, rlSrc1.highReg);
opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc1.lowReg,
rlSrc2.lowReg);
opRegRegReg(cUnit, secondOp, rlResult.highReg, tReg,
@@ -1789,7 +1778,7 @@
rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
// Avoid shifts by literal 0 - no support in Thumb. Change to copy
if (shiftOp && (lit == 0)) {
- genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
+ opRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
} else {
opRegRegImm(cUnit, op, rlResult.lowReg, rlSrc.lowReg, lit);
}
@@ -1815,7 +1804,7 @@
// Check for destructive overlap
if (rlResult.lowReg == rlSrc2.highReg) {
int tReg = oatAllocTemp(cUnit);
- genRegCopy(cUnit, tReg, rlSrc2.highReg);
+ opRegCopy(cUnit, tReg, rlSrc2.highReg);
opRegReg(cUnit, kOpMvn, rlResult.lowReg, rlSrc2.lowReg);
opRegReg(cUnit, kOpMvn, rlResult.highReg, tReg);
oatFreeTemp(cUnit, tReg);
@@ -2117,11 +2106,11 @@
oatClobberCalleeSave(cUnit);
#if defined(TARGET_ARM)
opRegImm(cUnit, kOpCmp, rSUSPEND, 0);
- genIT(cUnit, kArmCondNe, "T");
+ opIT(cUnit, kArmCondNe, "T");
loadConstant(cUnit, rARG2, offset); // arg2 <- Entry code
opReg(cUnit, kOpBlx, rSUSPEND);
#else
- LIR* branch = genCmpImmBranch(cUnit, kCondEq, rSUSPEND, 0);
+ LIR* branch = opCmpImmBranch(cUnit, kCondEq, rSUSPEND, 0, NULL);
loadConstant(cUnit, rARG2, offset);
opReg(cUnit, kOpBlx, rSUSPEND);
LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
@@ -2141,15 +2130,15 @@
LIR* branch;
if (cUnit->genDebugger) {
// If generating code for the debugger, always check for suspension
- branch = genUnconditionalBranch(cUnit, NULL);
+ branch = opUnconditionalBranch(cUnit, NULL);
} else {
#if defined(TARGET_ARM)
// In non-debug case, only check periodically
newLIR2(cUnit, kThumbSubRI8, rSUSPEND, 1);
- branch = opCondBranch(cUnit, kCondEq);
+ branch = opCondBranch(cUnit, kCondEq, NULL);
#else
opRegImm(cUnit, kOpSub, rSUSPEND, 1);
- branch = genCmpImmBranch(cUnit, kCondEq, rSUSPEND, 0);
+ branch = opCmpImmBranch(cUnit, kCondEq, rSUSPEND, 0, NULL);
#endif
}
LIR* retLab = newLIR0(cUnit, kPseudoTargetLabel);
diff --git a/src/compiler/codegen/GenInvoke.cc b/src/compiler/codegen/GenInvoke.cc
index a201010..69df8fc 100644
--- a/src/compiler/codegen/GenInvoke.cc
+++ b/src/compiler/codegen/GenInvoke.cc
@@ -58,10 +58,10 @@
if (i <= (lastArgReg - firstArgReg)) {
// If arriving in register
if (vMap.coreLocation == kLocPhysReg) {
- genRegCopy(cUnit, vMap.coreReg, firstArgReg + i);
+ opRegCopy(cUnit, vMap.coreReg, firstArgReg + i);
}
if (vMap.fpLocation == kLocPhysReg) {
- genRegCopy(cUnit, vMap.fpReg, firstArgReg + i);
+ opRegCopy(cUnit, vMap.fpReg, firstArgReg + i);
}
// Also put a copy in memory in case we're partially promoted
storeBaseDisp(cUnit, rSP, oatSRegOffset(cUnit, startVReg + i),
diff --git a/src/compiler/codegen/MethodCodegenDriver.cc b/src/compiler/codegen/MethodCodegenDriver.cc
index 38c2117..a1eeeae 100644
--- a/src/compiler/codegen/MethodCodegenDriver.cc
+++ b/src/compiler/codegen/MethodCodegenDriver.cc
@@ -103,7 +103,7 @@
genShowTarget(cUnit);
}
#if defined(TARGET_MIPS)
- UNIMPLEMENTED(FATAL) << "Need to handle common target register";
+ UNIMPLEMENTED(WARNING) << "Need to handle common target register";
#else
opReg(cUnit, kOpBlx, rLR);
#endif
@@ -325,7 +325,7 @@
if (bb->taken->startOffset <= mir->offset) {
genSuspendTest(cUnit, mir);
}
- genUnconditionalBranch(cUnit, &labelList[bb->taken->id]);
+ opUnconditionalBranch(cUnit, &labelList[bb->taken->id]);
break;
case OP_PACKED_SWITCH:
@@ -830,8 +830,8 @@
* Generate an unconditional branch to the fallthrough block.
*/
if (bb->fallThrough) {
- genUnconditionalBranch(cUnit,
- &labelList[bb->fallThrough->id]);
+ opUnconditionalBranch(cUnit,
+ &labelList[bb->fallThrough->id]);
}
}
return false;
@@ -856,20 +856,20 @@
/* Needed by the ld/st optmizatons */
LIR* oatRegCopyNoInsert(CompilationUnit* cUnit, int rDest, int rSrc)
{
- return genRegCopyNoInsert(cUnit, rDest, rSrc);
+ return opRegCopyNoInsert(cUnit, rDest, rSrc);
}
/* Needed by the register allocator */
void oatRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
{
- genRegCopy(cUnit, rDest, rSrc);
+ opRegCopy(cUnit, rDest, rSrc);
}
/* Needed by the register allocator */
void oatRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
- genRegCopyWide(cUnit, destLo, destHi, srcLo, srcHi);
+ opRegCopyWide(cUnit, destLo, destHi, srcLo, srcHi);
}
void oatFlushRegImpl(CompilationUnit* cUnit, int rBase,
diff --git a/src/compiler/codegen/arm/ArchFactory.cc b/src/compiler/codegen/arm/ArchFactory.cc
index 5f75ef8..b47fae1 100644
--- a/src/compiler/codegen/arm/ArchFactory.cc
+++ b/src/compiler/codegen/arm/ArchFactory.cc
@@ -75,7 +75,7 @@
cUnit->frameSize - (spillCount * 4));
genRegRegCheck(cUnit, kCondCc, rLR, r12, NULL,
kThrowStackOverflow);
- genRegCopy(cUnit, rSP, rLR); // Establish stack
+ opRegCopy(cUnit, rSP, rLR); // Establish stack
} else {
opRegImm(cUnit, kOpSub, rSP,
cUnit->frameSize - (spillCount * 4));
diff --git a/src/compiler/codegen/arm/Codegen.h b/src/compiler/codegen/arm/Codegen.h
index 49e39db..b985e1b 100644
--- a/src/compiler/codegen/arm/Codegen.h
+++ b/src/compiler/codegen/arm/Codegen.h
@@ -29,6 +29,8 @@
#if defined(_CODEGEN_C)
LIR *opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int value);
LIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int rSrc2);
+LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
+ int checkValue, LIR* target);
/* Forward declaraton the portable versions due to circular dependency */
bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
@@ -47,11 +49,9 @@
LIR* callRuntimeHelper(CompilationUnit* cUnit, int reg);
RegLocation getRetLoc(CompilationUnit* cUnit);
LIR* loadConstant(CompilationUnit* cUnit, int reg, int immVal);
-void genRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
- int srcLo, int srcHi);
-LIR* genRegCopy(CompilationUnit* cUnit, int rDest, int rSrc);
-LIR* genCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
- int checkValue);
+void opRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
+ int srcLo, int srcHi);
+LIR* opRegCopy(CompilationUnit* cUnit, int rDest, int rSrc);
void freeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
RegLocation rlFree);
diff --git a/src/compiler/codegen/arm/FP/Thumb2VFP.cc b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
index 094b952..9ef7b7b 100644
--- a/src/compiler/codegen/arm/FP/Thumb2VFP.cc
+++ b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
@@ -228,12 +228,12 @@
DCHECK(!FPREG(rlResult.lowReg));
newLIR0(cUnit, kThumb2Fmstat);
- genIT(cUnit, (defaultResult == -1) ? kArmCondGt : kArmCondMi, "");
+ opIT(cUnit, (defaultResult == -1) ? kArmCondGt : kArmCondMi, "");
newLIR2(cUnit, kThumb2MovImmShift, rlResult.lowReg,
modifiedImmediate(-defaultResult)); // Must not alter ccodes
genBarrier(cUnit);
- genIT(cUnit, kArmCondEq, "");
+ opIT(cUnit, kArmCondEq, "");
loadConstant(cUnit, rlResult.lowReg, 0);
genBarrier(cUnit);
diff --git a/src/compiler/codegen/arm/Thumb2/Factory.cc b/src/compiler/codegen/arm/Thumb2/Factory.cc
index 77d6066..03a69d5 100644
--- a/src/compiler/codegen/arm/Thumb2/Factory.cc
+++ b/src/compiler/codegen/arm/Thumb2/Factory.cc
@@ -212,10 +212,12 @@
return newLIR0(cUnit, opcode);
}
-LIR* opCondBranch(CompilationUnit* cUnit, ConditionCode cc)
+LIR* opCondBranch(CompilationUnit* cUnit, ConditionCode cc, LIR* target)
{
- return newLIR2(cUnit, kThumb2BCond, 0 /* offset to be patched */,
- oatArmConditionEncoding(cc));
+ LIR* branch = newLIR2(cUnit, kThumb2BCond, 0 /* offset to be patched */,
+ oatArmConditionEncoding(cc));
+ branch->target = target;
+ return branch;
}
LIR* opReg(CompilationUnit* cUnit, OpKind op, int rDestSrc)
diff --git a/src/compiler/codegen/arm/Thumb2/Gen.cc b/src/compiler/codegen/arm/Thumb2/Gen.cc
index 1dfb90d..838fcaf 100644
--- a/src/compiler/codegen/arm/Thumb2/Gen.cc
+++ b/src/compiler/codegen/arm/Thumb2/Gen.cc
@@ -37,7 +37,7 @@
* met, and an "E" means the instruction is executed if the condition
* is not met.
*/
-LIR* genIT(CompilationUnit* cUnit, ArmConditionCode code, const char* guide)
+LIR* opIT(CompilationUnit* cUnit, ArmConditionCode code, const char* guide)
{
int mask;
int condBit = code & 1;
@@ -58,7 +58,7 @@
case 0:
break;
default:
- LOG(FATAL) << "OAT: bad case in genIT";
+ LOG(FATAL) << "OAT: bad case in opIT";
}
mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) |
(1 << (3 - strlen(guide)));
@@ -124,13 +124,12 @@
newLIR2(cUnit, kThumb2LdmiaWB, rBase, (1 << rKey) | (1 << rDisp));
opRegReg(cUnit, kOpCmp, rKey, rlSrc.lowReg);
// Go if match. NOTE: No instruction set switch here - must stay Thumb2
- genIT(cUnit, kArmCondEq, "");
+ opIT(cUnit, kArmCondEq, "");
LIR* switchBranch = newLIR1(cUnit, kThumb2AddPCR, rDisp);
tabRec->bxInst = switchBranch;
// Needs to use setflags encoding here
newLIR3(cUnit, kThumb2SubsRRI12, rIdx, rIdx, 1);
- LIR* branch = opCondBranch(cUnit, kCondNe);
- branch->target = (LIR*)target;
+ opCondBranch(cUnit, kCondNe, target);
}
@@ -166,7 +165,7 @@
}
// Bounds check - if < 0 or >= size continue following switch
opRegImm(cUnit, kOpCmp, keyReg, size-1);
- LIR* branchOver = opCondBranch(cUnit, kCondHi);
+ LIR* branchOver = opCondBranch(cUnit, kCondHi, NULL);
// Load the displacement from the switch table
int dispReg = oatAllocTemp(cUnit);
@@ -328,7 +327,7 @@
opRegImm(cUnit, kOpLsl, r2, LW_LOCK_OWNER_SHIFT);
newLIR3(cUnit, kThumb2Bfc, r1, LW_HASH_STATE_SHIFT, LW_LOCK_OWNER_SHIFT - 1);
opRegReg(cUnit, kOpSub, r1, r2);
- hopBranch = opCondBranch(cUnit, kCondNe);
+ hopBranch = opCondBranch(cUnit, kCondNe, NULL);
oatGenMemBarrier(cUnit, kSY);
storeWordDisp(cUnit, r0, Object::MonitorOffset().Int32Value(), r3);
branch = opNone(cUnit, kOpUncondBr);
@@ -373,12 +372,12 @@
int tReg = oatAllocTemp(cUnit);
loadConstant(cUnit, tReg, -1);
opRegReg(cUnit, kOpCmp, rlSrc1.highReg, rlSrc2.highReg);
- LIR* branch1 = opCondBranch(cUnit, kCondLt);
- LIR* branch2 = opCondBranch(cUnit, kCondGt);
+ LIR* branch1 = opCondBranch(cUnit, kCondLt, NULL);
+ LIR* branch2 = opCondBranch(cUnit, kCondGt, NULL);
opRegRegReg(cUnit, kOpSub, tReg, rlSrc1.lowReg, rlSrc2.lowReg);
- LIR* branch3 = opCondBranch(cUnit, kCondEq);
+ LIR* branch3 = opCondBranch(cUnit, kCondEq, NULL);
- genIT(cUnit, kArmCondHi, "E");
+ opIT(cUnit, kArmCondHi, "E");
newLIR2(cUnit, kThumb2MovImmShift, tReg, modifiedImmediate(-1));
loadConstant(cUnit, tReg, 1);
genBarrier(cUnit);
@@ -404,8 +403,8 @@
* Generate a register comparison to an immediate and branch. Caller
* is responsible for setting branch target field.
*/
-LIR* genCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
- int checkValue)
+LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
+ int checkValue, LIR* target)
{
LIR* branch;
int modImm;
@@ -428,9 +427,10 @@
}
branch = newLIR2(cUnit, kThumbBCond, 0, armCond);
}
+ branch->target = target;
return branch;
}
-LIR* genRegCopyNoInsert(CompilationUnit* cUnit, int rDest, int rSrc)
+LIR* opRegCopyNoInsert(CompilationUnit* cUnit, int rDest, int rSrc)
{
LIR* res;
ArmOpcode opcode;
@@ -457,14 +457,14 @@
return res;
}
-LIR* genRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
+LIR* opRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
{
- LIR* res = genRegCopyNoInsert(cUnit, rDest, rSrc);
+ LIR* res = opRegCopyNoInsert(cUnit, rDest, rSrc);
oatAppendLIR(cUnit, (LIR*)res);
return res;
}
-void genRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
+void opRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
bool destFP = FPREG(destLo) && FPREG(destHi);
@@ -473,7 +473,7 @@
DCHECK_EQ(FPREG(destLo), FPREG(destHi));
if (destFP) {
if (srcFP) {
- genRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
+ opRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
} else {
newLIR3(cUnit, kThumb2Fmdrr, S2D(destLo, destHi), srcLo, srcHi);
}
@@ -483,11 +483,11 @@
} else {
// Handle overlap
if (srcHi == destLo) {
- genRegCopy(cUnit, destHi, srcHi);
- genRegCopy(cUnit, destLo, srcLo);
+ opRegCopy(cUnit, destHi, srcHi);
+ opRegCopy(cUnit, destLo, srcLo);
} else {
- genRegCopy(cUnit, destLo, srcLo);
- genRegCopy(cUnit, destHi, srcHi);
+ opRegCopy(cUnit, destLo, srcLo);
+ opRegCopy(cUnit, destHi, srcHi);
}
}
}
diff --git a/src/compiler/codegen/mips/ArchFactory.cc b/src/compiler/codegen/mips/ArchFactory.cc
index 2cb0731..aaaa50f 100644
--- a/src/compiler/codegen/mips/ArchFactory.cc
+++ b/src/compiler/codegen/mips/ArchFactory.cc
@@ -109,7 +109,7 @@
cUnit->frameSize - (spillCount * 4));
genRegRegCheck(cUnit, kCondCc, newSP, checkReg, NULL,
kThrowStackOverflow);
- genRegCopy(cUnit, rSP, newSP); // Establish stack
+ opRegCopy(cUnit, rSP, newSP); // Establish stack
} else {
opRegImm(cUnit, kOpSub, rSP,
cUnit->frameSize - (spillCount * 4));
diff --git a/src/compiler/codegen/mips/ArchUtility.cc b/src/compiler/codegen/mips/ArchUtility.cc
index 7f7aeb3..40188ce 100644
--- a/src/compiler/codegen/mips/ArchUtility.cc
+++ b/src/compiler/codegen/mips/ArchUtility.cc
@@ -22,33 +22,6 @@
namespace art {
-MipsConditionCode oatMipsConditionEncoding(ConditionCode code)
-{
- MipsConditionCode res;
- switch(code) {
- case kCondEq: res = kMipsCondEq; break;
- case kCondNe: res = kMipsCondNe; break;
- case kCondCs: res = kMipsCondCs; break;
- case kCondCc: res = kMipsCondCc; break;
- case kCondMi: res = kMipsCondMi; break;
- case kCondPl: res = kMipsCondPl; break;
- case kCondVs: res = kMipsCondVs; break;
- case kCondVc: res = kMipsCondVc; break;
- case kCondHi: res = kMipsCondHi; break;
- case kCondLs: res = kMipsCondLs; break;
- case kCondGe: res = kMipsCondGe; break;
- case kCondLt: res = kMipsCondLt; break;
- case kCondGt: res = kMipsCondGt; break;
- case kCondLe: res = kMipsCondLe; break;
- case kCondAl: res = kMipsCondAl; break;
- case kCondNv: res = kMipsCondNv; break;
- default:
- LOG(FATAL) << "Bad condition code" << (int)code;
- res = (MipsConditionCode)0; // Quiet gcc
- }
- return res;
-}
-
/* For dumping instructions */
#define MIPS_REG_COUNT 32
static const char *mipsRegName[MIPS_REG_COUNT] = {
@@ -112,37 +85,6 @@
case 'F':
sprintf(tbuf,"%d", operand*2);
break;
- case 'c':
- switch (operand) {
- case kMipsCondEq:
- strcpy(tbuf, "eq");
- break;
- case kMipsCondNe:
- strcpy(tbuf, "ne");
- break;
- case kMipsCondLt:
- strcpy(tbuf, "lt");
- break;
- case kMipsCondGe:
- strcpy(tbuf, "ge");
- break;
- case kMipsCondGt:
- strcpy(tbuf, "gt");
- break;
- case kMipsCondLe:
- strcpy(tbuf, "le");
- break;
- case kMipsCondCs:
- strcpy(tbuf, "cs");
- break;
- case kMipsCondMi:
- strcpy(tbuf, "mi");
- break;
- default:
- strcpy(tbuf, "");
- break;
- }
- break;
case 't':
sprintf(tbuf,"0x%08x (L%p)",
(int) baseAddr + lir->offset + 4 +
@@ -172,6 +114,10 @@
DCHECK(operand >= 0 && operand < MIPS_REG_COUNT);
strcpy(tbuf, mipsRegName[operand]);
break;
+ case 'N':
+ // Placeholder for delay slot handling
+ strcpy(tbuf, "; nop");
+ break;
default:
strcpy(tbuf,"DecodeError");
break;
diff --git a/src/compiler/codegen/mips/Assemble.cc b/src/compiler/codegen/mips/Assemble.cc
index bf54d23..4deb8f5 100644
--- a/src/compiler/codegen/mips/Assemble.cc
+++ b/src/compiler/codegen/mips/Assemble.cc
@@ -72,10 +72,17 @@
* n -> complimented Thumb2 modified immediate
* M -> Thumb2 16-bit zero-extended immediate
* b -> 4-digit binary
+ * N -> append a NOP
*
* [!] escape. To insert "!", use "!!"
*/
/* NOTE: must be kept in sync with enum MipsOpcode from LIR.h */
+/*
+ * TUNING: We're currently punting on the branch delay slots. All branch
+ * instructions in this map are given a size of 8, which during assembly
+ * is expanded to include a nop. This scheme should be replaced with
+ * an assembler pass to fill those slots when possible.
+ */
MipsEncodingMap EncodingMap[kMipsLast] = {
ENCODING_MAP(kMips32BitData, 0x00000000,
kFmtBitBlt, 31, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
@@ -100,43 +107,43 @@
ENCODING_MAP(kMipsB, 0x10000000,
kFmtBitBlt, 15, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH,
- "b", "!0t", 4),
+ "b", "!0t!0N", 8),
ENCODING_MAP(kMipsBal, 0x04110000,
kFmtBitBlt, 15, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, NO_OPERAND | IS_BRANCH | REG_DEF_LR,
- "bal", "!0t", 4),
+ "bal", "!0t!0N", 8),
ENCODING_MAP(kMipsBeq, 0x10000000,
kFmtBitBlt, 25, 21, kFmtBitBlt, 20, 16, kFmtBitBlt, 15, 0,
kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_USE01,
- "beq", "!0r,!1r,!2t", 4),
+ "beq", "!0r,!1r,!2t!0N", 8),
ENCODING_MAP(kMipsBeqz, 0x10000000, /* same as beq above with t = $zero */
kFmtBitBlt, 25, 21, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_USE0,
- "beqz", "!0r,!1t", 4),
+ "beqz", "!0r,!1t!0N", 8),
ENCODING_MAP(kMipsBgez, 0x04010000,
kFmtBitBlt, 25, 21, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_USE0,
- "bgez", "!0r,!1t", 4),
+ "bgez", "!0r,!1t!0N", 8),
ENCODING_MAP(kMipsBgtz, 0x1C000000,
kFmtBitBlt, 25, 21, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_USE0,
- "bgtz", "!0r,!1t", 4),
+ "bgtz", "!0r,!1t!0N", 8),
ENCODING_MAP(kMipsBlez, 0x18000000,
kFmtBitBlt, 25, 21, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_USE0,
- "blez", "!0r,!1t", 4),
+ "blez", "!0r,!1t!0N", 8),
ENCODING_MAP(kMipsBltz, 0x04000000,
kFmtBitBlt, 25, 21, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_USE0,
- "bltz", "!0r,!1t", 4),
+ "bltz", "!0r,!1t!0N", 8),
ENCODING_MAP(kMipsBnez, 0x14000000, /* same as bne below with t = $zero */
kFmtBitBlt, 25, 21, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_USE0,
- "bnez", "!0r,!1t", 4),
+ "bnez", "!0r,!1t!0N", 8),
ENCODING_MAP(kMipsBne, 0x14000000,
kFmtBitBlt, 25, 21, kFmtBitBlt, 20, 16, kFmtBitBlt, 15, 0,
kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_USE01,
- "bne", "!0r,!1r,!2t", 4),
+ "bne", "!0r,!1r,!2t!0N", 8),
ENCODING_MAP(kMipsDiv, 0x0000001a,
kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtBitBlt, 25, 21,
kFmtBitBlt, 20, 16, IS_QUAD_OP | REG_DEF01 | REG_USE23,
@@ -150,15 +157,15 @@
ENCODING_MAP(kMipsJal, 0x0c000000,
kFmtBitBlt, 25, 0, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_DEF_LR,
- "jal", "!0T(!0E)", 4),
+ "jal", "!0T(!0E)!0N", 8),
ENCODING_MAP(kMipsJalr, 0x00000009,
kFmtBitBlt, 15, 11, kFmtBitBlt, 25, 21, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_BINARY_OP | IS_BRANCH | REG_DEF0_USE1,
- "jalr", "!0r,!1r", 4),
+ "jalr", "!0r,!1r!0N", 8),
ENCODING_MAP(kMipsJr, 0x00000008,
kFmtBitBlt, 25, 21, kFmtUnused, -1, -1, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_UNARY_OP | IS_BRANCH | REG_USE0,
- "jr", "!0r", 4),
+ "jr", "!0r!0N", 8),
ENCODING_MAP(kMipsLahi, 0x3C000000,
kFmtBitBlt, 20, 16, kFmtBitBlt, 15, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0,
@@ -520,10 +527,17 @@
<< (int)encoder->fieldLoc[i].kind;
}
}
- DCHECK_EQ(encoder->size, 2);
+ DCHECK_EQ(encoder->size, 4);
// FIXME: need multi-endian handling here
cUnit->codeBuffer.push_back((bits >> 16) & 0xffff);
cUnit->codeBuffer.push_back(bits & 0xffff);
+ // TUNING: replace with proper delay slot handling
+ if (encoder->size == 8) {
+ const MipsEncodingMap *encoder = &EncodingMap[kMipsNop];
+ u4 bits = encoder->skeleton;
+ cUnit->codeBuffer.push_back((bits >> 16) & 0xffff);
+ cUnit->codeBuffer.push_back(bits & 0xffff);
+ }
}
return res;
}
diff --git a/src/compiler/codegen/mips/Codegen.h b/src/compiler/codegen/mips/Codegen.h
index 355693c..c6f1d98 100644
--- a/src/compiler/codegen/mips/Codegen.h
+++ b/src/compiler/codegen/mips/Codegen.h
@@ -29,6 +29,10 @@
#if defined(_CODEGEN_C)
LIR *opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int value);
LIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int rSrc2);
+LIR* opCmpBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
+ int src2, LIR* target);
+LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
+ int checkValue, LIR* target);
/* Forward declaraton the portable versions due to circular dependency */
bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
@@ -41,17 +45,13 @@
bool genConversionPortable(CompilationUnit* cUnit, MIR* mir);
-MipsConditionCode oatMipsConditionEncoding(ConditionCode code);
-
int loadHelper(CompilationUnit* cUnit, int offset);
LIR* callRuntimeHelper(CompilationUnit* cUnit, int reg);
RegLocation getRetLoc(CompilationUnit* cUnit);
LIR* loadConstant(CompilationUnit* cUnit, int reg, int immVal);
-void genRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
- int srcLo, int srcHi);
-LIR* genRegCopy(CompilationUnit* cUnit, int rDest, int rSrc);
-LIR* genCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
- int checkValue);
+void opRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
+ int srcLo, int srcHi);
+LIR* opRegCopy(CompilationUnit* cUnit, int rDest, int rSrc);
void freeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
RegLocation rlFree);
diff --git a/src/compiler/codegen/mips/FP/MipsFP.cc b/src/compiler/codegen/mips/FP/MipsFP.cc
index acbac7f..4501210 100644
--- a/src/compiler/codegen/mips/FP/MipsFP.cc
+++ b/src/compiler/codegen/mips/FP/MipsFP.cc
@@ -217,7 +217,7 @@
loadValueAddress(cUnit, rlSrc1, r_A0);
oatClobber(cUnit, r_A0);
loadValueAddress(cUnit, rlSrc2, r_A1);
- UNIMP(FATAL) << "Need callout to handler";
+ UNIMPLEMENTED(FATAL) << "Need callout to handler";
#if 0
genDispatchToHandler(cUnit, templateOpcode);
#endif
diff --git a/src/compiler/codegen/mips/Mips32/Factory.cc b/src/compiler/codegen/mips/Mips32/Factory.cc
index 2613f2c..46987d3 100644
--- a/src/compiler/codegen/mips/Mips32/Factory.cc
+++ b/src/compiler/codegen/mips/Mips32/Factory.cc
@@ -39,8 +39,6 @@
#endif
void genBarrier(CompilationUnit *cUnit);
-LIR* genCompareBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
- int src2);
void storePair(CompilationUnit *cUnit, int base, int lowReg,
int highReg);
void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
@@ -145,39 +143,6 @@
return res;
}
-
-LIR *opCmpBranchCC(CompilationUnit *cUnit, MipsConditionCode cc,
- int rs, int rt)
-{
- UNIMPLEMENTED(FATAL);
- return 0;
-}
-LIR *opCmpImmBranchCC(CompilationUnit *cUnit, MipsConditionCode cc,
- int rs, int immVal)
-{
- UNIMPLEMENTED(FATAL);
- return 0;
-}
-LIR *opCmpImmBranch(CompilationUnit *cUnit, MipsOpCode cc,
- int rs, int immVal)
-{
- UNIMPLEMENTED(FATAL);
- return 0;
-}
-
-LIR *opCmpBranch(CompilationUnit *cUnit, MipsOpCode opc, int rs, int rt)
-{
- LIR *res;
- if (rt < 0) {
- DCHECK(opc >= kMipsBeqz && opc <= kMipsBnez);
- res = newLIR1(cUnit, opc, rs);
- } else {
- DCHECK(opc == kMipsBeq || opc == kMipsBne);
- res = newLIR2(cUnit, opc, rs, rt);
- }
- return res;
-}
-
LIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask);
LIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
@@ -187,6 +152,9 @@
case kOpBlx:
opcode = kMipsJalr;
break;
+ case kOpBx:
+ return newLIR1(cUnit, kMipsJr, rDestSrc);
+ break;
default:
LOG(FATAL) << "Bad case in opReg";
}
@@ -656,9 +624,7 @@
}
}
- UNIMPLEMENTED(FATAL) << "Needs art conversion";
-#if 0
- if (rBase == rFP) {
+ if (rBase == rSP) {
if (load != NULL)
annotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
true /* isLoad */);
@@ -666,7 +632,6 @@
annotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2,
true /* isLoad */);
}
-#endif
return load;
}
@@ -760,9 +725,7 @@
oatFreeTemp(cUnit, rScratch);
}
- UNIMPLEMENTED(FATAL) << "Needs art conversion";
-#if 0
- if (rBase == rFP) {
+ if (rBase == rSP) {
if (store != NULL)
annotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
false /* isLoad */);
@@ -770,7 +733,6 @@
annotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2,
false /* isLoad */);
}
-#endif
return res;
}
diff --git a/src/compiler/codegen/mips/Mips32/Gen.cc b/src/compiler/codegen/mips/Mips32/Gen.cc
index 942dbc5..db34ce3 100644
--- a/src/compiler/codegen/mips/Mips32/Gen.cc
+++ b/src/compiler/codegen/mips/Mips32/Gen.cc
@@ -85,13 +85,12 @@
newLIR2(cUnit, kThumb2LdmiaWB, rBase, (1 << rKey) | (1 << rDisp));
opRegReg(cUnit, kOpCmp, rKey, rlSrc.lowReg);
// Go if match. NOTE: No instruction set switch here - must stay Thumb2
- genIT(cUnit, kArmCondEq, "");
+ opIT(cUnit, kArmCondEq, "");
LIR* switchBranch = newLIR1(cUnit, kThumb2AddPCR, rDisp);
tabRec->bxInst = switchBranch;
// Needs to use setflags encoding here
newLIR3(cUnit, kThumb2SubsRRI12, rIdx, rIdx, 1);
- LIR* branch = opCondBranch(cUnit, kCondNe);
- branch->target = (LIR*)target;
+ LIR* branch = opCondBranch(cUnit, kCondNe, target);
#endif
}
@@ -130,7 +129,7 @@
}
// Bounds check - if < 0 or >= size continue following switch
opRegImm(cUnit, kOpCmp, keyReg, size-1);
- LIR* branchOver = opCondBranch(cUnit, kCondHi);
+ LIR* branchOver = opCondBranch(cUnit, kCondHi, NULL);
// Load the displacement from the switch table
int dispReg = oatAllocTemp(cUnit);
@@ -201,7 +200,7 @@
rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegImm(cUnit, kOpAdd, rlResult.highReg, rlSrc.highReg,
0x80000000);
- genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
+ opRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
storeValueWide(cUnit, rlDest, rlResult);
}
@@ -260,7 +259,7 @@
newLIR3(cUnit, kMipsSlt, t0, rlSrc1.highReg, rlSrc2.highReg);
newLIR3(cUnit, kMipsSlt, t1, rlSrc2.highReg, rlSrc1.highReg);
newLIR3(cUnit, kMipsSubu, rlResult.lowReg, t1, t0);
- LIR* branch = genCmpImmBranch(cUnit, kCondNe, rlResult.lowReg, 0);
+ LIR* branch = opCmpImmBranch(cUnit, kCondNe, rlResult.lowReg, 0, NULL);
newLIR3(cUnit, kMipsSltu, t0, rlSrc1.lowReg, rlSrc2.lowReg);
newLIR3(cUnit, kMipsSltu, t1, rlSrc2.lowReg, rlSrc1.lowReg);
newLIR3(cUnit, kMipsSubu, rlResult.lowReg, t1, t0);
@@ -272,32 +271,71 @@
storeValue(cUnit, rlDest, rlResult);
}
-LIR* genCompareBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
- int src2)
+LIR* opCmpBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
+ int src2, LIR* target)
{
+ LIR* branch;
if (cond == kCondEq) {
- return newLIR2(cUnit, kMipsBeq, src1, src2);
+ branch = newLIR2(cUnit, kMipsBeq, src1, src2);
} else if (cond == kCondNe) {
- return newLIR2(cUnit, kMipsBne, src1, src2);
+ branch = newLIR2(cUnit, kMipsBne, src1, src2);
+ } else {
+ MipsOpCode sltOp;
+ MipsOpCode brOp;
+ bool swapped = false;
+ switch(cond) {
+ case kCondEq: return newLIR2(cUnit, kMipsBeq, src1, src2);
+ case kCondNe: return newLIR2(cUnit, kMipsBne, src1, src2);
+ case kCondCc:
+ sltOp = kMipsSltu;
+ brOp = kMipsBnez;
+ break;
+ case kCondGe:
+ sltOp = kMipsSlt;
+ brOp = kMipsBeqz;
+ break;
+ case kCondGt:
+ sltOp = kMipsSlt;
+ brOp = kMipsBnez;
+ swapped = true;
+ break;
+ case kCondLe:
+ sltOp = kMipsSlt;
+ brOp = kMipsBeqz;
+ swapped = true;
+ break;
+ case kCondLt:
+ sltOp = kMipsSlt;
+ brOp = kMipsBnez;
+ break;
+ default:
+ UNIMPLEMENTED(FATAL) << "No support for ConditionCode: "
+ << (int) cond;
+ return NULL;
+ }
+ int tReg = oatAllocTemp(cUnit);
+ if (swapped) {
+ newLIR3(cUnit, sltOp, tReg, src2, src1);
+ } else {
+ newLIR3(cUnit, sltOp, tReg, src1, src2);
+ }
+ branch = newLIR1(cUnit, brOp, tReg);
+ branch->target = target;
}
- //int rRes = oatAllocTemp(cUnit);
- switch(cond) {
- case kCondEq: return newLIR2(cUnit, kMipsBeq, src1, src2);
- case kCondNe: return newLIR2(cUnit, kMipsBne, src1, src2);
- default:
- UNIMPLEMENTED(FATAL) << "Need to flesh out genCompareBranch";
- return NULL;
- }
+ return branch;
}
-LIR* genCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
- int checkValue)
+LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
+ int checkValue, LIR* target)
{
+ LIR* branch;
if (checkValue != 0) {
// TUNING: handle s16 & kCondLt/Mi case using slti
int tReg = oatAllocTemp(cUnit);
loadConstant(cUnit, tReg, checkValue);
- return genCompareBranch(cUnit, cond, reg, tReg);
+ branch = opCmpBranch(cUnit, cond, reg, tReg, target);
+ oatFreeTemp(cUnit, tReg);
+ return branch;
}
MipsOpCode opc;
switch(cond) {
@@ -309,14 +347,19 @@
case kCondLt: opc = kMipsBltz; break;
case kCondNe: opc = kMipsBnez; break;
default:
+ // Tuning: use slti when applicable
int tReg = oatAllocTemp(cUnit);
loadConstant(cUnit, tReg, checkValue);
- return genCompareBranch(cUnit, cond, reg, tReg);
+ branch = opCmpBranch(cUnit, cond, reg, tReg, target);
+ oatFreeTemp(cUnit, tReg);
+ return branch;
}
- return newLIR1(cUnit, opc, reg);
+ branch = newLIR1(cUnit, opc, reg);
+ branch->target = target;
+ return branch;
}
-LIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
+LIR* opRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
{
LIR* res;
MipsOpCode opcode;
@@ -337,14 +380,14 @@
return res;
}
-LIR* genRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
+LIR* opRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
{
- LIR *res = genRegCopyNoInsert(cUnit, rDest, rSrc);
+ LIR *res = opRegCopyNoInsert(cUnit, rDest, rSrc);
oatAppendLIR(cUnit, (LIR*)res);
return res;
}
-void genRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
+void opRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
#ifdef __mips_hard_float
@@ -354,7 +397,7 @@
assert(FPREG(destLo) == FPREG(destHi));
if (destFP) {
if (srcFP) {
- genRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
+ opRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
} else {
/* note the operands are swapped for the mtc1 instr */
newLIR2(cUnit, kMipsMtc1, srcLo, destLo);
@@ -367,22 +410,22 @@
} else {
// Handle overlap
if (srcHi == destLo) {
- genRegCopy(cUnit, destHi, srcHi);
- genRegCopy(cUnit, destLo, srcLo);
+ opRegCopy(cUnit, destHi, srcHi);
+ opRegCopy(cUnit, destLo, srcLo);
} else {
- genRegCopy(cUnit, destLo, srcLo);
- genRegCopy(cUnit, destHi, srcHi);
+ opRegCopy(cUnit, destLo, srcLo);
+ opRegCopy(cUnit, destHi, srcHi);
}
}
}
#else
// Handle overlap
if (srcHi == destLo) {
- genRegCopy(cUnit, destHi, srcHi);
- genRegCopy(cUnit, destLo, srcLo);
+ opRegCopy(cUnit, destHi, srcHi);
+ opRegCopy(cUnit, destLo, srcLo);
} else {
- genRegCopy(cUnit, destLo, srcLo);
- genRegCopy(cUnit, destHi, srcHi);
+ opRegCopy(cUnit, destLo, srcLo);
+ opRegCopy(cUnit, destHi, srcHi);
}
#endif
}
diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h
index 9baa3c0..67f3131 100644
--- a/src/compiler/codegen/mips/MipsLIR.h
+++ b/src/compiler/codegen/mips/MipsLIR.h
@@ -311,26 +311,6 @@
kMipsRor = 0x3
} MipsShiftEncodings;
-/* condition encodings */
-typedef enum MipsConditionCode {
- kMipsCondEq = 0x0, /* 0000 */
- kMipsCondNe = 0x1, /* 0001 */
- kMipsCondCs = 0x2, /* 0010 */
- kMipsCondCc = 0x3, /* 0011 */
- kMipsCondMi = 0x4, /* 0100 */
- kMipsCondPl = 0x5, /* 0101 */
- kMipsCondVs = 0x6, /* 0110 */
- kMipsCondVc = 0x7, /* 0111 */
- kMipsCondHi = 0x8, /* 1000 */
- kMipsCondLs = 0x9, /* 1001 */
- kMipsCondGe = 0xa, /* 1010 */
- kMipsCondLt = 0xb, /* 1011 */
- kMipsCondGt = 0xc, /* 1100 */
- kMipsCondLe = 0xd, /* 1101 */
- kMipsCondAl = 0xe, /* 1110 */
- kMipsCondNv = 0xf, /* 1111 */
-} MipsConditionCode;
-
// FIXME: Need support for barriers. Adding these defines to allow compile
#define kST 0
#define kSY 1
diff --git a/src/compiler/codegen/mips/MipsRallocUtil.cc b/src/compiler/codegen/mips/MipsRallocUtil.cc
index 504375b..774dffc 100644
--- a/src/compiler/codegen/mips/MipsRallocUtil.cc
+++ b/src/compiler/codegen/mips/MipsRallocUtil.cc
@@ -122,8 +122,6 @@
oatClobber(cUnit, r_GP);
oatClobber(cUnit, r_FP);
oatClobber(cUnit, r_RA);
- oatClobber(cUnit, r_HI);
- oatClobber(cUnit, r_LO);
oatClobber(cUnit, r_F0);
oatClobber(cUnit, r_F1);
oatClobber(cUnit, r_F2);