Update load/store utilities for 64-bit backends
This CL replaces the typical use of LoadWord/StoreWord
utilities (which, in practice, were 32-bit load/store) in
favor of a new set that make the size explicit. We now have:
LoadWordDisp/StoreWordDisp:
32 or 64 depending on target. Load or store the natural
word size. Expect this to be used infrequently - generally
when we know we're dealing with a native pointer or flushed
register not holding a Dalvik value (Dalvik values will flush
to home location sizes based on Dalvik, rather than the target).
Load32Disp/Store32Disp:
Load or store 32 bits, regardless of target.
Load64Disp/Store64Disp:
Load or store 64 bits, regardless of target.
LoadRefDisp:
Load a 32-bit compressed reference, and expand it to the
natural word size in the target register.
StoreRefDisp:
Compress a reference held in a register of the natural word
size and store it as a 32-bit compressed reference.
Change-Id: I50fcbc8684476abd9527777ee7c152c61ba41c6f
diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc
index c959510..12775e1 100644
--- a/compiler/dex/quick/mips/utility_mips.cc
+++ b/compiler/dex/quick/mips/utility_mips.cc
@@ -357,11 +357,11 @@
if (MIPS_FPREG(r_dest.GetReg())) {
DCHECK(MIPS_SINGLEREG(r_dest.GetReg()));
- DCHECK((size == kWord) || (size == kSingle));
+ DCHECK((size == k32) || (size == kSingle));
size = kSingle;
} else {
if (size == kSingle)
- size = kWord;
+ size = k32;
}
if (!scale) {
@@ -375,7 +375,8 @@
case kSingle:
opcode = kMipsFlwc1;
break;
- case kWord:
+ case k32:
+ case kReference:
opcode = kMipsLw;
break;
case kUnsignedHalf:
@@ -408,11 +409,11 @@
if (MIPS_FPREG(r_src.GetReg())) {
DCHECK(MIPS_SINGLEREG(r_src.GetReg()));
- DCHECK((size == kWord) || (size == kSingle));
+ DCHECK((size == k32) || (size == kSingle));
size = kSingle;
} else {
if (size == kSingle)
- size = kWord;
+ size = k32;
}
if (!scale) {
@@ -426,7 +427,8 @@
case kSingle:
opcode = kMipsFswc1;
break;
- case kWord:
+ case k32:
+ case kReference:
opcode = kMipsSw;
break;
case kUnsignedHalf:
@@ -463,7 +465,7 @@
bool pair = false;
switch (size) {
- case kLong:
+ case k64:
case kDouble:
pair = true;
opcode = kMipsLw;
@@ -481,8 +483,9 @@
short_form = IS_SIMM16_2WORD(displacement);
DCHECK_EQ((displacement & 0x3), 0);
break;
- case kWord:
+ case k32:
case kSingle:
+ case kReference:
opcode = kMipsLw;
if (MIPS_FPREG(r_dest.GetReg())) {
opcode = kMipsFlwc1;
@@ -544,13 +547,17 @@
LIR* MipsMir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
OpSize size, int s_reg) {
+ // TODO: base this on target.
+ if (size == kWord) {
+ size = k32;
+ }
return LoadBaseDispBody(r_base, displacement, r_dest, RegStorage::InvalidReg(), size,
s_reg);
}
LIR* MipsMir2Lir::LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest,
int s_reg) {
- return LoadBaseDispBody(r_base, displacement, r_dest.GetLow(), r_dest.GetHigh(), kLong, s_reg);
+ return LoadBaseDispBody(r_base, displacement, r_dest.GetLow(), r_dest.GetHigh(), k64, s_reg);
}
LIR* MipsMir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement,
@@ -563,7 +570,7 @@
bool pair = false;
switch (size) {
- case kLong:
+ case k64:
case kDouble:
pair = true;
opcode = kMipsSw;
@@ -580,8 +587,9 @@
short_form = IS_SIMM16_2WORD(displacement);
DCHECK_EQ((displacement & 0x3), 0);
break;
- case kWord:
+ case k32:
case kSingle:
+ case kReference:
opcode = kMipsSw;
if (MIPS_FPREG(r_src.GetReg())) {
opcode = kMipsFswc1;
@@ -635,11 +643,15 @@
LIR* MipsMir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
OpSize size) {
+ // TODO: base this on target.
+ if (size == kWord) {
+ size = k32;
+ }
return StoreBaseDispBody(r_base, displacement, r_src, RegStorage::InvalidReg(), size);
}
LIR* MipsMir2Lir::StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src) {
- return StoreBaseDispBody(r_base, displacement, r_src.GetLow(), r_src.GetHigh(), kLong);
+ return StoreBaseDispBody(r_base, displacement, r_src.GetLow(), r_src.GetHigh(), k64);
}
LIR* MipsMir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) {