Update load/store utilities for 64-bit backends
This CL replaces the typical use of LoadWord/StoreWord
utilities (which, in practice, were 32-bit load/store) in
favor of a new set that make the size explicit. We now have:
LoadWordDisp/StoreWordDisp:
32 or 64 depending on target. Load or store the natural
word size. Expect this to be used infrequently - generally
when we know we're dealing with a native pointer or flushed
register not holding a Dalvik value (Dalvik values will flush
to home location sizes based on Dalvik, rather than the target).
Load32Disp/Store32Disp:
Load or store 32 bits, regardless of target.
Load64Disp/Store64Disp:
Load or store 64 bits, regardless of target.
LoadRefDisp:
Load a 32-bit compressed reference, and expand it to the
natural word size in the target register.
StoreRefDisp:
Compress a reference held in a register of the natural word
size and store it as a 32-bit compressed reference.
Change-Id: I50fcbc8684476abd9527777ee7c152c61ba41c6f
diff --git a/compiler/dex/quick/mips/call_mips.cc b/compiler/dex/quick/mips/call_mips.cc
index a938478..a237ac7 100644
--- a/compiler/dex/quick/mips/call_mips.cc
+++ b/compiler/dex/quick/mips/call_mips.cc
@@ -112,11 +112,11 @@
RegStorage r_key = AllocTemp();
LIR* loop_label = NewLIR0(kPseudoTargetLabel);
LIR* exit_branch = OpCmpBranch(kCondEq, r_base, r_end, NULL);
- LoadWordDisp(r_base, 0, r_key);
+ Load32Disp(r_base, 0, r_key);
OpRegImm(kOpAdd, r_base, 8);
OpCmpBranch(kCondNe, rl_src.reg, r_key, loop_label);
RegStorage r_disp = AllocTemp();
- LoadWordDisp(r_base, -4, r_disp);
+ Load32Disp(r_base, -4, r_disp);
OpRegRegReg(kOpAdd, rs_rRA, rs_rRA, r_disp);
OpReg(kOpBx, rs_rRA);
@@ -200,7 +200,7 @@
// Load the displacement from the switch table
RegStorage r_disp = AllocTemp();
- LoadBaseIndexed(r_base, r_key, r_disp, 2, kWord);
+ LoadBaseIndexed(r_base, r_key, r_disp, 2, k32);
// Add to rAP and go
OpRegRegReg(kOpAdd, rs_rRA, rs_rRA, r_disp);
@@ -263,9 +263,9 @@
int ex_offset = Thread::ExceptionOffset<4>().Int32Value();
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
RegStorage reset_reg = AllocTemp();
- LoadWordDisp(rs_rMIPS_SELF, ex_offset, rl_result.reg);
+ Load32Disp(rs_rMIPS_SELF, ex_offset, rl_result.reg);
LoadConstant(reset_reg, 0);
- StoreWordDisp(rs_rMIPS_SELF, ex_offset, reset_reg);
+ Store32Disp(rs_rMIPS_SELF, ex_offset, reset_reg);
FreeTemp(reset_reg);
StoreValue(rl_dest, rl_result);
}
@@ -277,6 +277,7 @@
RegStorage reg_card_base = AllocTemp();
RegStorage reg_card_no = AllocTemp();
LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
+ // NOTE: native pointer.
LoadWordDisp(rs_rMIPS_SELF, Thread::CardTableOffset<4>().Int32Value(), reg_card_base);
OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift);
StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, kUnsignedByte);
@@ -310,7 +311,7 @@
RegStorage new_sp = AllocTemp();
if (!skip_overflow_check) {
/* Load stack limit */
- LoadWordDisp(rs_rMIPS_SELF, Thread::StackEndOffset<4>().Int32Value(), check_reg);
+ Load32Disp(rs_rMIPS_SELF, Thread::StackEndOffset<4>().Int32Value(), check_reg);
}
/* Spill core callee saves */
SpillCoreRegs();
@@ -328,7 +329,7 @@
m2l_->ResetDefTracking();
GenerateTargetLabel();
// LR is offset 0 since we push in reverse order.
- m2l_->LoadWordDisp(rs_rMIPS_SP, 0, rs_rRA);
+ m2l_->Load32Disp(rs_rMIPS_SP, 0, rs_rRA);
m2l_->OpRegImm(kOpAdd, rs_rMIPS_SP, sp_displace_);
m2l_->ClobberCallerSave();
ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pThrowStackOverflow);
diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc
index 60358b4..3644738 100644
--- a/compiler/dex/quick/mips/int_mips.cc
+++ b/compiler/dex/quick/mips/int_mips.cc
@@ -480,7 +480,7 @@
rl_array = LoadValue(rl_array, kCoreReg);
rl_index = LoadValue(rl_index, kCoreReg);
- if (size == kLong || size == kDouble) {
+ if (size == k64 || size == kDouble) {
data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value();
} else {
data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value();
@@ -495,12 +495,12 @@
if (needs_range_check) {
reg_len = AllocTemp();
/* Get len */
- LoadWordDisp(rl_array.reg, len_offset, reg_len);
+ Load32Disp(rl_array.reg, len_offset, reg_len);
}
/* reg_ptr -> array data */
OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset);
FreeTemp(rl_array.reg.GetReg());
- if ((size == kLong) || (size == kDouble)) {
+ if ((size == k64) || (size == kDouble)) {
if (scale) {
RegStorage r_new_index = AllocTemp();
OpRegRegImm(kOpLsl, r_new_index, rl_index.reg, scale);
@@ -544,7 +544,7 @@
int len_offset = mirror::Array::LengthOffset().Int32Value();
int data_offset;
- if (size == kLong || size == kDouble) {
+ if (size == k64 || size == kDouble) {
data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value();
} else {
data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value();
@@ -572,12 +572,12 @@
reg_len = AllocTemp();
// NOTE: max live temps(4) here.
/* Get len */
- LoadWordDisp(rl_array.reg, len_offset, reg_len);
+ Load32Disp(rl_array.reg, len_offset, reg_len);
}
/* reg_ptr -> array data */
OpRegImm(kOpAdd, reg_ptr, data_offset);
/* at this point, reg_ptr points to array, 2 live temps */
- if ((size == kLong) || (size == kDouble)) {
+ if ((size == k64) || (size == kDouble)) {
// TUNING: specific wide routine that can handle fp regs
if (scale) {
RegStorage r_new_index = AllocTemp();
diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc
index 3e02fae..7f4cd5e 100644
--- a/compiler/dex/quick/mips/target_mips.cc
+++ b/compiler/dex/quick/mips/target_mips.cc
@@ -369,7 +369,7 @@
if (info->live && info->dirty) {
info->dirty = false;
int v_reg = mir_graph_->SRegToVReg(info->s_reg);
- StoreBaseDisp(rs_rMIPS_SP, VRegOffset(v_reg), reg, kWord);
+ Store32Disp(rs_rMIPS_SP, VRegOffset(v_reg), reg);
}
}
@@ -531,12 +531,14 @@
* there is a trap in the shadow. Allocate a temp register.
*/
RegStorage MipsMir2Lir::LoadHelper(ThreadOffset<4> offset) {
+ // NOTE: native pointer.
LoadWordDisp(rs_rMIPS_SELF, offset.Int32Value(), rs_rT9);
return rs_rT9;
}
LIR* MipsMir2Lir::CheckSuspendUsingLoad() {
RegStorage tmp = AllocTemp();
+ // NOTE: native pointer.
LoadWordDisp(rs_rMIPS_SELF, Thread::ThreadSuspendTriggerOffset<4>().Int32Value(), tmp);
LIR *inst = LoadWordDisp(tmp, 0, tmp);
FreeTemp(tmp);
@@ -553,7 +555,7 @@
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
offset -= 4;
- StoreWordDisp(rs_rMIPS_SP, offset, RegStorage::Solo32(reg));
+ Store32Disp(rs_rMIPS_SP, offset, RegStorage::Solo32(reg));
}
}
}
@@ -567,7 +569,7 @@
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
offset -= 4;
- LoadWordDisp(rs_rMIPS_SP, offset, RegStorage::Solo32(reg));
+ Load32Disp(rs_rMIPS_SP, offset, RegStorage::Solo32(reg));
}
}
OpRegImm(kOpAdd, rs_rSP, frame_size_);
diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc
index c959510..12775e1 100644
--- a/compiler/dex/quick/mips/utility_mips.cc
+++ b/compiler/dex/quick/mips/utility_mips.cc
@@ -357,11 +357,11 @@
if (MIPS_FPREG(r_dest.GetReg())) {
DCHECK(MIPS_SINGLEREG(r_dest.GetReg()));
- DCHECK((size == kWord) || (size == kSingle));
+ DCHECK((size == k32) || (size == kSingle));
size = kSingle;
} else {
if (size == kSingle)
- size = kWord;
+ size = k32;
}
if (!scale) {
@@ -375,7 +375,8 @@
case kSingle:
opcode = kMipsFlwc1;
break;
- case kWord:
+ case k32:
+ case kReference:
opcode = kMipsLw;
break;
case kUnsignedHalf:
@@ -408,11 +409,11 @@
if (MIPS_FPREG(r_src.GetReg())) {
DCHECK(MIPS_SINGLEREG(r_src.GetReg()));
- DCHECK((size == kWord) || (size == kSingle));
+ DCHECK((size == k32) || (size == kSingle));
size = kSingle;
} else {
if (size == kSingle)
- size = kWord;
+ size = k32;
}
if (!scale) {
@@ -426,7 +427,8 @@
case kSingle:
opcode = kMipsFswc1;
break;
- case kWord:
+ case k32:
+ case kReference:
opcode = kMipsSw;
break;
case kUnsignedHalf:
@@ -463,7 +465,7 @@
bool pair = false;
switch (size) {
- case kLong:
+ case k64:
case kDouble:
pair = true;
opcode = kMipsLw;
@@ -481,8 +483,9 @@
short_form = IS_SIMM16_2WORD(displacement);
DCHECK_EQ((displacement & 0x3), 0);
break;
- case kWord:
+ case k32:
case kSingle:
+ case kReference:
opcode = kMipsLw;
if (MIPS_FPREG(r_dest.GetReg())) {
opcode = kMipsFlwc1;
@@ -544,13 +547,17 @@
LIR* MipsMir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
OpSize size, int s_reg) {
+ // TODO: base this on target.
+ if (size == kWord) {
+ size = k32;
+ }
return LoadBaseDispBody(r_base, displacement, r_dest, RegStorage::InvalidReg(), size,
s_reg);
}
LIR* MipsMir2Lir::LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest,
int s_reg) {
- return LoadBaseDispBody(r_base, displacement, r_dest.GetLow(), r_dest.GetHigh(), kLong, s_reg);
+ return LoadBaseDispBody(r_base, displacement, r_dest.GetLow(), r_dest.GetHigh(), k64, s_reg);
}
LIR* MipsMir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement,
@@ -563,7 +570,7 @@
bool pair = false;
switch (size) {
- case kLong:
+ case k64:
case kDouble:
pair = true;
opcode = kMipsSw;
@@ -580,8 +587,9 @@
short_form = IS_SIMM16_2WORD(displacement);
DCHECK_EQ((displacement & 0x3), 0);
break;
- case kWord:
+ case k32:
case kSingle:
+ case kReference:
opcode = kMipsSw;
if (MIPS_FPREG(r_src.GetReg())) {
opcode = kMipsFswc1;
@@ -635,11 +643,15 @@
LIR* MipsMir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
OpSize size) {
+ // TODO: base this on target.
+ if (size == kWord) {
+ size = k32;
+ }
return StoreBaseDispBody(r_base, displacement, r_src, RegStorage::InvalidReg(), size);
}
LIR* MipsMir2Lir::StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src) {
- return StoreBaseDispBody(r_base, displacement, r_src.GetLow(), r_src.GetHigh(), kLong);
+ return StoreBaseDispBody(r_base, displacement, r_src.GetLow(), r_src.GetHigh(), k64);
}
LIR* MipsMir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) {