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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Header for MultiMediaCard (MMC)
3 *
4 * Copyright 2002 Hewlett-Packard Company
5 *
6 * Use consistent with the GNU GPL is permitted,
7 * provided that this copyright notice is
8 * preserved in its entirety in all copies and derived works.
9 *
10 * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
11 * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
12 * FITNESS FOR ANY PARTICULAR PURPOSE.
13 *
14 * Many thanks to Alessandro Rubini and Jonathan Corbet!
15 *
16 * Based strongly on code by:
17 *
18 * Author: Yong-iL Joh <tolkien@mizi.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019 *
20 * Author: Andrew Christian
21 * 15 May 2002
22 */
23
Robert P. J. Day100e9182011-05-27 16:04:03 -040024#ifndef LINUX_MMC_MMC_H
25#define LINUX_MMC_MMC_H
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Philip Langdalebce40a32006-10-21 12:35:02 +020027/* Standard MMC commands (4.1) type argument response */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028 /* class 1 */
David Brownell97018582007-08-08 09:09:01 -070029#define MMC_GO_IDLE_STATE 0 /* bc */
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
31#define MMC_ALL_SEND_CID 2 /* bcr R2 */
32#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
33#define MMC_SET_DSR 4 /* bc [31:16] RCA */
Jarkko Lavinenb1ebe382009-09-22 16:44:34 -070034#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
Philip Langdalebce40a32006-10-21 12:35:02 +020035#define MMC_SWITCH 6 /* ac [31:0] See below R1b */
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
Philip Langdalebce40a32006-10-21 12:35:02 +020037#define MMC_SEND_EXT_CSD 8 /* adtc R1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
39#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
40#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
41#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
David Brownell97018582007-08-08 09:09:01 -070042#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
Aries Lee22113ef2010-12-15 08:14:24 +010043#define MMC_BUS_TEST_R 14 /* adtc R1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
Aries Lee22113ef2010-12-15 08:14:24 +010045#define MMC_BUS_TEST_W 19 /* adtc R1 */
David Brownell97018582007-08-08 09:09:01 -070046#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
47#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49 /* class 2 */
50#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
51#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
52#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
Arindam Nathb513ea22011-05-05 12:19:04 +053053#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
Girish K Sa4924c72012-01-11 14:04:52 -050054#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
SamarV-121b5757112020-09-21 05:47:44 +000056#define MMC_TUNING_BLK_PATTERN_4BIT_SIZE 64
57#define MMC_TUNING_BLK_PATTERN_8BIT_SIZE 128
58extern const u8 tuning_blk_pattern_4bit[MMC_TUNING_BLK_PATTERN_4BIT_SIZE];
59extern const u8 tuning_blk_pattern_8bit[MMC_TUNING_BLK_PATTERN_8BIT_SIZE];
60
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 /* class 3 */
62#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
63
64 /* class 4 */
65#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
66#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
67#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
68#define MMC_PROGRAM_CID 26 /* adtc R1 */
69#define MMC_PROGRAM_CSD 27 /* adtc R1 */
70
71 /* class 6 */
72#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
73#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
74#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
75
76 /* class 5 */
77#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
78#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
Pierre Ossman24117de2005-11-28 21:00:29 +000079#define MMC_ERASE 38 /* ac R1b */
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
81 /* class 9 */
82#define MMC_FAST_IO 39 /* ac <Complex> R4 */
83#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
84
85 /* class 7 */
86#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
87
88 /* class 8 */
89#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
Pierre Ossman24117de2005-11-28 21:00:29 +000090#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070091
SamarV-121b5757112020-09-21 05:47:44 +000092/* class 11 */
93#define MMC_CMDQ_TASK_MGMT 48 /* ac [31:0] task ID R1b */
94#define DISCARD_QUEUE 0x1
95#define DISCARD_TASK 0x2
96
Andrei Warkentind0c97cf2011-05-23 15:06:36 -050097static inline bool mmc_op_multi(u32 opcode)
98{
99 return opcode == MMC_WRITE_MULTIPLE_BLOCK ||
100 opcode == MMC_READ_MULTIPLE_BLOCK;
101}
102
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103/*
Philip Langdalebce40a32006-10-21 12:35:02 +0200104 * MMC_SWITCH argument format:
105 *
106 * [31:26] Always 0
107 * [25:24] Access Mode
108 * [23:16] Location of target Byte in EXT_CSD
109 * [15:08] Value Byte
110 * [07:03] Always 0
111 * [02:00] Command Set
112 */
113
114/*
David Brownell97018582007-08-08 09:09:01 -0700115 MMC status in R1, for native mode (SPI bits are different)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116 Type
David Brownell97018582007-08-08 09:09:01 -0700117 e : error bit
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 s : status bit
119 r : detected and set for the actual command response
120 x : detected and set during command execution. the host must poll
121 the card by sending status command in order to read these bits.
122 Clear condition
David Brownell97018582007-08-08 09:09:01 -0700123 a : according to the card state
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124 b : always related to the previous command. Reception of
125 a valid command will clear it (with a delay of one command)
126 c : clear by read
127 */
128
129#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
130#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
131#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
132#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
133#define R1_ERASE_PARAM (1 << 27) /* ex, c */
134#define R1_WP_VIOLATION (1 << 26) /* erx, c */
135#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
136#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
137#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
138#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
139#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
140#define R1_CC_ERROR (1 << 20) /* erx, c */
141#define R1_ERROR (1 << 19) /* erx, c */
142#define R1_UNDERRUN (1 << 18) /* ex, c */
143#define R1_OVERRUN (1 << 17) /* ex, c */
144#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
145#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
146#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
147#define R1_ERASE_RESET (1 << 13) /* sr, c */
148#define R1_STATUS(x) (x & 0xFFFFE000)
David Brownell97018582007-08-08 09:09:01 -0700149#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
Adrian Hunteref0b27d2009-09-22 16:44:37 -0700151#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
Seungwon Jeonabd9ac12013-02-06 17:01:43 +0900152#define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153#define R1_APP_CMD (1 << 5) /* sr, c */
154
Russell King - ARM Linux0a2d4042011-06-20 20:10:08 +0100155#define R1_STATE_IDLE 0
156#define R1_STATE_READY 1
157#define R1_STATE_IDENT 2
158#define R1_STATE_STBY 3
159#define R1_STATE_TRAN 4
160#define R1_STATE_DATA 5
161#define R1_STATE_RCV 6
162#define R1_STATE_PRG 7
163#define R1_STATE_DIS 8
164
David Brownell97018582007-08-08 09:09:01 -0700165/*
166 * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
167 * R1 is the low order byte; R2 is the next highest byte, when present.
168 */
169#define R1_SPI_IDLE (1 << 0)
170#define R1_SPI_ERASE_RESET (1 << 1)
171#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
172#define R1_SPI_COM_CRC (1 << 3)
173#define R1_SPI_ERASE_SEQ (1 << 4)
174#define R1_SPI_ADDRESS (1 << 5)
175#define R1_SPI_PARAMETER (1 << 6)
176/* R1 bit 7 is always zero */
177#define R2_SPI_CARD_LOCKED (1 << 8)
178#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
179#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
180#define R2_SPI_ERROR (1 << 10)
181#define R2_SPI_CC_ERROR (1 << 11)
182#define R2_SPI_CARD_ECC_ERROR (1 << 12)
183#define R2_SPI_WP_VIOLATION (1 << 13)
184#define R2_SPI_ERASE_PARAM (1 << 14)
185#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
186#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
187
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188/* These are unpacked versions of the actual responses */
189
190struct _mmc_csd {
191 u8 csd_structure;
192 u8 spec_vers;
193 u8 taac;
194 u8 nsac;
195 u8 tran_speed;
196 u16 ccc;
197 u8 read_bl_len;
198 u8 read_bl_partial;
199 u8 write_blk_misalign;
200 u8 read_blk_misalign;
201 u8 dsr_imp;
202 u16 c_size;
203 u8 vdd_r_curr_min;
204 u8 vdd_r_curr_max;
205 u8 vdd_w_curr_min;
206 u8 vdd_w_curr_max;
207 u8 c_size_mult;
208 union {
209 struct { /* MMC system specification version 3.1 */
210 u8 erase_grp_size;
211 u8 erase_grp_mult;
212 } v31;
213 struct { /* MMC system specification version 2.2 */
214 u8 sector_size;
215 u8 erase_grp_size;
216 } v22;
217 } erase;
218 u8 wp_grp_size;
219 u8 wp_grp_enable;
220 u8 default_ecc;
221 u8 r2w_factor;
222 u8 write_bl_len;
223 u8 write_bl_partial;
224 u8 file_format_grp;
225 u8 copy;
226 u8 perm_write_protect;
227 u8 tmp_write_protect;
228 u8 file_format;
229 u8 ecc;
230};
231
Pierre Ossmanf74d1322007-02-09 22:49:31 +0100232/*
233 * OCR bits are mostly in host.h
234 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
236
Pierre Ossman912490d2005-05-21 10:27:02 +0100237/*
238 * Card Command Classes (CCC)
239 */
240#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
241 /* (CMD0,1,2,3,4,7,9,10,12,13,15) */
David Brownell97018582007-08-08 09:09:01 -0700242 /* (and for SPI, CMD58,59) */
Pierre Ossman912490d2005-05-21 10:27:02 +0100243#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
244 /* (CMD11) */
245#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
246 /* (CMD16,17,18) */
247#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
248 /* (CMD20) */
249#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
250 /* (CMD16,24,25,26,27) */
251#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
252 /* (CMD32,33,34,35,36,37,38,39) */
253#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
254 /* (CMD28,29,30) */
255#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
256 /* (CMD16,CMD42) */
257#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
258 /* (CMD55,56,57,ACMD*) */
259#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
260 /* (CMD5,39,40,52,53) */
261#define CCC_SWITCH (1<<10) /* (10) High speed switch */
262 /* (CMD6,34,35,36,37,50) */
263 /* (11) Reserved */
264 /* (CMD?) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265
266/*
267 * CSD field definitions
268 */
269
270#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
271#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
Philip Langdalebce40a32006-10-21 12:35:02 +0200272#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
273#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274
275#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
276#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
277#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
Philip Langdalebce40a32006-10-21 12:35:02 +0200278#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
279#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280
Philip Langdalebce40a32006-10-21 12:35:02 +0200281/*
282 * EXT_CSD fields
283 */
284
SamarV-121b5757112020-09-21 05:47:44 +0000285#define EXT_CSD_CMDQ 15 /* R/W */
286#define EXT_CSD_BARRIER_CTRL 31 /* R/W */
Seungwon Jeon881d1c22011-10-14 14:03:21 +0900287#define EXT_CSD_FLUSH_CACHE 32 /* W */
288#define EXT_CSD_CACHE_CTRL 33 /* R/W */
Girish K Sbec87262011-10-13 12:04:16 +0530289#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
Seungwon Jeonabd9ac12013-02-06 17:01:43 +0900290#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
291#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
292#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
293#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
Saugata Das42659002011-12-21 13:09:17 +0530294#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
Namjae Jeone0c368d2011-10-06 23:41:38 +0900295#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
Grégory Soutadé69803d42014-09-15 17:47:09 +0200296#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
Chuanxiao Dong709de992011-01-22 04:09:41 +0800297#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
298#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
Jaehoon Chungeb0d8f12011-10-18 01:26:42 -0400299#define EXT_CSD_HPI_MGMT 161 /* R/W */
Adrian Hunterb2499512011-08-29 16:42:11 +0300300#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
Jaehoon Chung950d56a2012-09-17 08:42:02 +0000301#define EXT_CSD_BKOPS_EN 163 /* R/W */
302#define EXT_CSD_BKOPS_START 164 /* W */
Kyungmin Parkd9ddd622011-10-14 14:15:48 +0900303#define EXT_CSD_SANITIZE_START 165 /* W */
Andrei Warkentinf4c55222011-03-31 18:40:00 -0500304#define EXT_CSD_WR_REL_PARAM 166 /* RO */
Loic Pallardy090d25f2012-11-17 18:08:24 -0500305#define EXT_CSD_RPMB_MULT 168 /* RO */
Gwendal Grignou0f762422014-10-16 11:27:16 -0700306#define EXT_CSD_FW_CONFIG 169 /* R/W */
Johan Rudholmadd710e2011-12-02 08:51:06 +0100307#define EXT_CSD_BOOT_WP 173 /* R/W */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700308#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
Andrei Warkentin371a6892011-04-11 18:10:25 -0500309#define EXT_CSD_PART_CONFIG 179 /* R/W */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700310#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
311#define EXT_CSD_BUS_WIDTH 183 /* R/W */
SamarV-121b5757112020-09-21 05:47:44 +0000312#define EXT_CSD_STORBE_SUPPORT 184 /* R/W */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700313#define EXT_CSD_HS_TIMING 185 /* R/W */
Girish K Sb87d8db2011-09-23 20:41:47 +0530314#define EXT_CSD_POWER_CLASS 187 /* R/W */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700315#define EXT_CSD_REV 192 /* RO */
316#define EXT_CSD_STRUCTURE 194 /* RO */
317#define EXT_CSD_CARD_TYPE 196 /* RO */
Adrian Hunterb097e072015-02-06 14:12:57 +0200318#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
Jaehoon Chungeb0d8f12011-10-18 01:26:42 -0400319#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
Andrei Warkentin371a6892011-04-11 18:10:25 -0500320#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
Girish K Sb87d8db2011-09-23 20:41:47 +0530321#define EXT_CSD_PWR_CL_52_195 200 /* RO */
322#define EXT_CSD_PWR_CL_26_195 201 /* RO */
323#define EXT_CSD_PWR_CL_52_360 202 /* RO */
324#define EXT_CSD_PWR_CL_26_360 203 /* RO */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700325#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
326#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
Andrei Warkentinf4c55222011-03-31 18:40:00 -0500327#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
Chuanxiao Dong709de992011-01-22 04:09:41 +0800328#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700329#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
330#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Andrei Warkentin371a6892011-04-11 18:10:25 -0500331#define EXT_CSD_BOOT_MULT 226 /* RO */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700332#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
333#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
334#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
335#define EXT_CSD_TRIM_MULT 232 /* RO */
Girish K Sb87d8db2011-09-23 20:41:47 +0530336#define EXT_CSD_PWR_CL_200_195 236 /* RO */
337#define EXT_CSD_PWR_CL_200_360 237 /* RO */
338#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
339#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
SamarV-121b5757112020-09-21 05:47:44 +0000340#define EXT_CSD_CACHE_FLUSH_POLICY 240 /* RO */
Jaehoon Chung950d56a2012-09-17 08:42:02 +0000341#define EXT_CSD_BKOPS_STATUS 246 /* RO */
Girish K Sb87d8db2011-09-23 20:41:47 +0530342#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
Seungwon Jeonb23cf0b2011-09-23 14:15:29 +0900343#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
Seungwon Jeon881d1c22011-10-14 14:03:21 +0900344#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
Seungwon Jeon0a5b6432014-04-23 17:14:58 +0900345#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
Gwendal Grignou0f762422014-10-16 11:27:16 -0700346#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */
SamarV-121b5757112020-09-21 05:47:44 +0000347#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYPE_A 268 /* RO, 8 bytes */
348#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYPE_B 269 /* RO, 8 bytes */
349#define EXT_CSD_CMDQ_DEPTH 307 /* RO */
350#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */
351#define EXT_CSD_BARRIER_SUPPORT 486 /* RO */
352#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
353#define EXT_CSD_PRE_EOL_INFO 267 /* RO */
354#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */
355#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */
Gwendal Grignou0f762422014-10-16 11:27:16 -0700356#define EXT_CSD_SUPPORTED_MODE 493 /* RO */
Saugata Das42659002011-12-21 13:09:17 +0530357#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
358#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
Seungwon Jeonabd9ac12013-02-06 17:01:43 +0900359#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
360#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
Jaehoon Chung950d56a2012-09-17 08:42:02 +0000361#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
Jaehoon Chungeb0d8f12011-10-18 01:26:42 -0400362#define EXT_CSD_HPI_FEATURES 503 /* RO */
Philip Langdalebce40a32006-10-21 12:35:02 +0200363
364/*
365 * EXT_CSD field definitions
366 */
367
SamarV-121b5757112020-09-21 05:47:44 +0000368#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
369#define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1<<4)
Andrei Warkentinf4c55222011-03-31 18:40:00 -0500370
Johan Rudholmadd710e2011-12-02 08:51:06 +0100371#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
372#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
373#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
374#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
375
Andrei Warkentin371a6892011-04-11 18:10:25 -0500376#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
377#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
Loic Pallardy090d25f2012-11-17 18:08:24 -0500378#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
Namjae Jeone0c368d2011-10-06 23:41:38 +0900379#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
380
Grégory Soutadé69803d42014-09-15 17:47:09 +0200381#define EXT_CSD_PART_SETTING_COMPLETED (0x1)
Namjae Jeone0c368d2011-10-06 23:41:38 +0900382#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
Andrei Warkentin371a6892011-04-11 18:10:25 -0500383
Philip Langdalebce40a32006-10-21 12:35:02 +0200384#define EXT_CSD_CMD_SET_NORMAL (1<<0)
385#define EXT_CSD_CMD_SET_SECURE (1<<1)
386#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
387
Seungwon Jeon2415c0e2014-04-23 17:07:58 +0900388#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
389#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
390#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \
391 EXT_CSD_CARD_TYPE_HS_52)
Hanumath Prasaddfc13e82010-09-30 17:37:23 -0400392#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
393 /* DDR mode @1.8V or 3V I/O */
394#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
395 /* DDR mode @1.2V I/O */
396#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
397 | EXT_CSD_CARD_TYPE_DDR_1_2V)
Seungwon Jeon2415c0e2014-04-23 17:07:58 +0900398#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
399#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
Girish K Sa4924c72012-01-11 14:04:52 -0500400 /* SDR mode @1.2V I/O */
Seungwon Jeon2415c0e2014-04-23 17:07:58 +0900401#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
402 EXT_CSD_CARD_TYPE_HS200_1_2V)
Seungwon Jeon0a5b6432014-04-23 17:14:58 +0900403#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
404#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
405#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
406 EXT_CSD_CARD_TYPE_HS400_1_2V)
Girish K Sa4924c72012-01-11 14:04:52 -0500407
Philip Langdalee45a1bd2006-10-29 10:14:19 +0100408#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
409#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
410#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Hanumath Prasaddfc13e82010-09-30 17:37:23 -0400411#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
412#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
SamarV-121b5757112020-09-21 05:47:44 +0000413#define EXT_CSD_STROBE_ENHANCED_EN (1 << 7) /* Card in enhanced strobe mode */
Philip Langdalee45a1bd2006-10-29 10:14:19 +0100414
Seungwon Jeon577fb132014-04-23 17:08:44 +0900415#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
416#define EXT_CSD_TIMING_HS 1 /* High speed */
417#define EXT_CSD_TIMING_HS200 2 /* HS200 */
Seungwon Jeon0a5b6432014-04-23 17:14:58 +0900418#define EXT_CSD_TIMING_HS400 3 /* HS400 */
Adrian Huntercc4f4142015-02-06 14:12:58 +0200419#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
Seungwon Jeon577fb132014-04-23 17:08:44 +0900420
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700421#define EXT_CSD_SEC_ER_EN BIT(0)
422#define EXT_CSD_SEC_BD_BLK_EN BIT(2)
423#define EXT_CSD_SEC_GB_CL_EN BIT(4)
Kyungmin Parkd9ddd622011-10-14 14:15:48 +0900424#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
Adrian Hunterdfe86cb2010-08-11 14:17:46 -0700425
Adrian Hunterb2499512011-08-29 16:42:11 +0300426#define EXT_CSD_RST_N_EN_MASK 0x3
427#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
428
Girish K Sbec87262011-10-13 12:04:16 +0530429#define EXT_CSD_NO_POWER_NOTIFICATION 0
430#define EXT_CSD_POWER_ON 1
431#define EXT_CSD_POWER_OFF_SHORT 2
432#define EXT_CSD_POWER_OFF_LONG 3
433
Girish K Sb87d8db2011-09-23 20:41:47 +0530434#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
435#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
436#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
437#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
Seungwon Jeonabd9ac12013-02-06 17:01:43 +0900438
439#define EXT_CSD_PACKED_EVENT_EN BIT(3)
440
Philip Langdalebce40a32006-10-21 12:35:02 +0200441/*
Jaehoon Chung950d56a2012-09-17 08:42:02 +0000442 * EXCEPTION_EVENT_STATUS field
443 */
444#define EXT_CSD_URGENT_BKOPS BIT(0)
445#define EXT_CSD_DYNCAP_NEEDED BIT(1)
446#define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2)
447#define EXT_CSD_PACKED_FAILURE BIT(3)
448
Seungwon Jeonabd9ac12013-02-06 17:01:43 +0900449#define EXT_CSD_PACKED_GENERIC_ERROR BIT(0)
450#define EXT_CSD_PACKED_INDEXED_ERROR BIT(1)
451
Jaehoon Chung950d56a2012-09-17 08:42:02 +0000452/*
453 * BKOPS status level
454 */
455#define EXT_CSD_BKOPS_LEVEL_2 0x2
456
457/*
Alexey Skidanov0501be62015-01-29 10:49:43 +0200458 * BKOPS modes
459 */
460#define EXT_CSD_MANUAL_BKOPS_MASK 0x01
461
462/*
Philip Langdalebce40a32006-10-21 12:35:02 +0200463 * MMC_SWITCH access modes
464 */
465
466#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
467#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
468#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
469#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
Pierre Ossmanf2182782005-09-06 15:18:55 -0700470
Adrian Huntercc4f4142015-02-06 14:12:58 +0200471#define mmc_driver_type_mask(n) (1 << (n))
472
Robert P. J. Day100e9182011-05-27 16:04:03 -0400473#endif /* LINUX_MMC_MMC_H */