Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Header for MultiMediaCard (MMC) |
| 3 | * |
| 4 | * Copyright 2002 Hewlett-Packard Company |
| 5 | * |
| 6 | * Use consistent with the GNU GPL is permitted, |
| 7 | * provided that this copyright notice is |
| 8 | * preserved in its entirety in all copies and derived works. |
| 9 | * |
| 10 | * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, |
| 11 | * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS |
| 12 | * FITNESS FOR ANY PARTICULAR PURPOSE. |
| 13 | * |
| 14 | * Many thanks to Alessandro Rubini and Jonathan Corbet! |
| 15 | * |
| 16 | * Based strongly on code by: |
| 17 | * |
| 18 | * Author: Yong-iL Joh <tolkien@mizi.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | * |
| 20 | * Author: Andrew Christian |
| 21 | * 15 May 2002 |
| 22 | */ |
| 23 | |
Robert P. J. Day | 100e918 | 2011-05-27 16:04:03 -0400 | [diff] [blame] | 24 | #ifndef LINUX_MMC_MMC_H |
| 25 | #define LINUX_MMC_MMC_H |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 27 | /* Standard MMC commands (4.1) type argument response */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | /* class 1 */ |
David Brownell | 9701858 | 2007-08-08 09:09:01 -0700 | [diff] [blame] | 29 | #define MMC_GO_IDLE_STATE 0 /* bc */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ |
| 31 | #define MMC_ALL_SEND_CID 2 /* bcr R2 */ |
| 32 | #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ |
| 33 | #define MMC_SET_DSR 4 /* bc [31:16] RCA */ |
Jarkko Lavinen | b1ebe38 | 2009-09-22 16:44:34 -0700 | [diff] [blame] | 34 | #define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 35 | #define MMC_SWITCH 6 /* ac [31:0] See below R1b */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 37 | #define MMC_SEND_EXT_CSD 8 /* adtc R1 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ |
| 39 | #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ |
| 40 | #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ |
| 41 | #define MMC_STOP_TRANSMISSION 12 /* ac R1b */ |
David Brownell | 9701858 | 2007-08-08 09:09:01 -0700 | [diff] [blame] | 42 | #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 43 | #define MMC_BUS_TEST_R 14 /* adtc R1 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 45 | #define MMC_BUS_TEST_W 19 /* adtc R1 */ |
David Brownell | 9701858 | 2007-08-08 09:09:01 -0700 | [diff] [blame] | 46 | #define MMC_SPI_READ_OCR 58 /* spi spi_R3 */ |
| 47 | #define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | |
| 49 | /* class 2 */ |
| 50 | #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ |
| 51 | #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ |
| 52 | #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 53 | #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */ |
Girish K S | a4924c7 | 2012-01-11 14:04:52 -0500 | [diff] [blame] | 54 | #define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | |
SamarV-121 | b575711 | 2020-09-21 05:47:44 +0000 | [diff] [blame] | 56 | #define MMC_TUNING_BLK_PATTERN_4BIT_SIZE 64 |
| 57 | #define MMC_TUNING_BLK_PATTERN_8BIT_SIZE 128 |
| 58 | extern const u8 tuning_blk_pattern_4bit[MMC_TUNING_BLK_PATTERN_4BIT_SIZE]; |
| 59 | extern const u8 tuning_blk_pattern_8bit[MMC_TUNING_BLK_PATTERN_8BIT_SIZE]; |
| 60 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | /* class 3 */ |
| 62 | #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ |
| 63 | |
| 64 | /* class 4 */ |
| 65 | #define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ |
| 66 | #define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ |
| 67 | #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ |
| 68 | #define MMC_PROGRAM_CID 26 /* adtc R1 */ |
| 69 | #define MMC_PROGRAM_CSD 27 /* adtc R1 */ |
| 70 | |
| 71 | /* class 6 */ |
| 72 | #define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ |
| 73 | #define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ |
| 74 | #define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ |
| 75 | |
| 76 | /* class 5 */ |
| 77 | #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ |
| 78 | #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ |
Pierre Ossman | 24117de | 2005-11-28 21:00:29 +0000 | [diff] [blame] | 79 | #define MMC_ERASE 38 /* ac R1b */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | |
| 81 | /* class 9 */ |
| 82 | #define MMC_FAST_IO 39 /* ac <Complex> R4 */ |
| 83 | #define MMC_GO_IRQ_STATE 40 /* bcr R5 */ |
| 84 | |
| 85 | /* class 7 */ |
| 86 | #define MMC_LOCK_UNLOCK 42 /* adtc R1b */ |
| 87 | |
| 88 | /* class 8 */ |
| 89 | #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ |
Pierre Ossman | 24117de | 2005-11-28 21:00:29 +0000 | [diff] [blame] | 90 | #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | |
SamarV-121 | b575711 | 2020-09-21 05:47:44 +0000 | [diff] [blame] | 92 | /* class 11 */ |
| 93 | #define MMC_CMDQ_TASK_MGMT 48 /* ac [31:0] task ID R1b */ |
| 94 | #define DISCARD_QUEUE 0x1 |
| 95 | #define DISCARD_TASK 0x2 |
| 96 | |
Andrei Warkentin | d0c97cf | 2011-05-23 15:06:36 -0500 | [diff] [blame] | 97 | static inline bool mmc_op_multi(u32 opcode) |
| 98 | { |
| 99 | return opcode == MMC_WRITE_MULTIPLE_BLOCK || |
| 100 | opcode == MMC_READ_MULTIPLE_BLOCK; |
| 101 | } |
| 102 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | /* |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 104 | * MMC_SWITCH argument format: |
| 105 | * |
| 106 | * [31:26] Always 0 |
| 107 | * [25:24] Access Mode |
| 108 | * [23:16] Location of target Byte in EXT_CSD |
| 109 | * [15:08] Value Byte |
| 110 | * [07:03] Always 0 |
| 111 | * [02:00] Command Set |
| 112 | */ |
| 113 | |
| 114 | /* |
David Brownell | 9701858 | 2007-08-08 09:09:01 -0700 | [diff] [blame] | 115 | MMC status in R1, for native mode (SPI bits are different) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | Type |
David Brownell | 9701858 | 2007-08-08 09:09:01 -0700 | [diff] [blame] | 117 | e : error bit |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | s : status bit |
| 119 | r : detected and set for the actual command response |
| 120 | x : detected and set during command execution. the host must poll |
| 121 | the card by sending status command in order to read these bits. |
| 122 | Clear condition |
David Brownell | 9701858 | 2007-08-08 09:09:01 -0700 | [diff] [blame] | 123 | a : according to the card state |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | b : always related to the previous command. Reception of |
| 125 | a valid command will clear it (with a delay of one command) |
| 126 | c : clear by read |
| 127 | */ |
| 128 | |
| 129 | #define R1_OUT_OF_RANGE (1 << 31) /* er, c */ |
| 130 | #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ |
| 131 | #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ |
| 132 | #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ |
| 133 | #define R1_ERASE_PARAM (1 << 27) /* ex, c */ |
| 134 | #define R1_WP_VIOLATION (1 << 26) /* erx, c */ |
| 135 | #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ |
| 136 | #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ |
| 137 | #define R1_COM_CRC_ERROR (1 << 23) /* er, b */ |
| 138 | #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ |
| 139 | #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ |
| 140 | #define R1_CC_ERROR (1 << 20) /* erx, c */ |
| 141 | #define R1_ERROR (1 << 19) /* erx, c */ |
| 142 | #define R1_UNDERRUN (1 << 18) /* ex, c */ |
| 143 | #define R1_OVERRUN (1 << 17) /* ex, c */ |
| 144 | #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ |
| 145 | #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ |
| 146 | #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ |
| 147 | #define R1_ERASE_RESET (1 << 13) /* sr, c */ |
| 148 | #define R1_STATUS(x) (x & 0xFFFFE000) |
David Brownell | 9701858 | 2007-08-08 09:09:01 -0700 | [diff] [blame] | 149 | #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | #define R1_READY_FOR_DATA (1 << 8) /* sx, a */ |
Adrian Hunter | ef0b27d | 2009-09-22 16:44:37 -0700 | [diff] [blame] | 151 | #define R1_SWITCH_ERROR (1 << 7) /* sx, c */ |
Seungwon Jeon | abd9ac1 | 2013-02-06 17:01:43 +0900 | [diff] [blame] | 152 | #define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | #define R1_APP_CMD (1 << 5) /* sr, c */ |
| 154 | |
Russell King - ARM Linux | 0a2d404 | 2011-06-20 20:10:08 +0100 | [diff] [blame] | 155 | #define R1_STATE_IDLE 0 |
| 156 | #define R1_STATE_READY 1 |
| 157 | #define R1_STATE_IDENT 2 |
| 158 | #define R1_STATE_STBY 3 |
| 159 | #define R1_STATE_TRAN 4 |
| 160 | #define R1_STATE_DATA 5 |
| 161 | #define R1_STATE_RCV 6 |
| 162 | #define R1_STATE_PRG 7 |
| 163 | #define R1_STATE_DIS 8 |
| 164 | |
David Brownell | 9701858 | 2007-08-08 09:09:01 -0700 | [diff] [blame] | 165 | /* |
| 166 | * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS |
| 167 | * R1 is the low order byte; R2 is the next highest byte, when present. |
| 168 | */ |
| 169 | #define R1_SPI_IDLE (1 << 0) |
| 170 | #define R1_SPI_ERASE_RESET (1 << 1) |
| 171 | #define R1_SPI_ILLEGAL_COMMAND (1 << 2) |
| 172 | #define R1_SPI_COM_CRC (1 << 3) |
| 173 | #define R1_SPI_ERASE_SEQ (1 << 4) |
| 174 | #define R1_SPI_ADDRESS (1 << 5) |
| 175 | #define R1_SPI_PARAMETER (1 << 6) |
| 176 | /* R1 bit 7 is always zero */ |
| 177 | #define R2_SPI_CARD_LOCKED (1 << 8) |
| 178 | #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ |
| 179 | #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP |
| 180 | #define R2_SPI_ERROR (1 << 10) |
| 181 | #define R2_SPI_CC_ERROR (1 << 11) |
| 182 | #define R2_SPI_CARD_ECC_ERROR (1 << 12) |
| 183 | #define R2_SPI_WP_VIOLATION (1 << 13) |
| 184 | #define R2_SPI_ERASE_PARAM (1 << 14) |
| 185 | #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ |
| 186 | #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE |
| 187 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | /* These are unpacked versions of the actual responses */ |
| 189 | |
| 190 | struct _mmc_csd { |
| 191 | u8 csd_structure; |
| 192 | u8 spec_vers; |
| 193 | u8 taac; |
| 194 | u8 nsac; |
| 195 | u8 tran_speed; |
| 196 | u16 ccc; |
| 197 | u8 read_bl_len; |
| 198 | u8 read_bl_partial; |
| 199 | u8 write_blk_misalign; |
| 200 | u8 read_blk_misalign; |
| 201 | u8 dsr_imp; |
| 202 | u16 c_size; |
| 203 | u8 vdd_r_curr_min; |
| 204 | u8 vdd_r_curr_max; |
| 205 | u8 vdd_w_curr_min; |
| 206 | u8 vdd_w_curr_max; |
| 207 | u8 c_size_mult; |
| 208 | union { |
| 209 | struct { /* MMC system specification version 3.1 */ |
| 210 | u8 erase_grp_size; |
| 211 | u8 erase_grp_mult; |
| 212 | } v31; |
| 213 | struct { /* MMC system specification version 2.2 */ |
| 214 | u8 sector_size; |
| 215 | u8 erase_grp_size; |
| 216 | } v22; |
| 217 | } erase; |
| 218 | u8 wp_grp_size; |
| 219 | u8 wp_grp_enable; |
| 220 | u8 default_ecc; |
| 221 | u8 r2w_factor; |
| 222 | u8 write_bl_len; |
| 223 | u8 write_bl_partial; |
| 224 | u8 file_format_grp; |
| 225 | u8 copy; |
| 226 | u8 perm_write_protect; |
| 227 | u8 tmp_write_protect; |
| 228 | u8 file_format; |
| 229 | u8 ecc; |
| 230 | }; |
| 231 | |
Pierre Ossman | f74d132 | 2007-02-09 22:49:31 +0100 | [diff] [blame] | 232 | /* |
| 233 | * OCR bits are mostly in host.h |
| 234 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | #define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ |
| 236 | |
Pierre Ossman | 912490d | 2005-05-21 10:27:02 +0100 | [diff] [blame] | 237 | /* |
| 238 | * Card Command Classes (CCC) |
| 239 | */ |
| 240 | #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ |
| 241 | /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ |
David Brownell | 9701858 | 2007-08-08 09:09:01 -0700 | [diff] [blame] | 242 | /* (and for SPI, CMD58,59) */ |
Pierre Ossman | 912490d | 2005-05-21 10:27:02 +0100 | [diff] [blame] | 243 | #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ |
| 244 | /* (CMD11) */ |
| 245 | #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ |
| 246 | /* (CMD16,17,18) */ |
| 247 | #define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ |
| 248 | /* (CMD20) */ |
| 249 | #define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ |
| 250 | /* (CMD16,24,25,26,27) */ |
| 251 | #define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ |
| 252 | /* (CMD32,33,34,35,36,37,38,39) */ |
| 253 | #define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ |
| 254 | /* (CMD28,29,30) */ |
| 255 | #define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ |
| 256 | /* (CMD16,CMD42) */ |
| 257 | #define CCC_APP_SPEC (1<<8) /* (8) Application specific */ |
| 258 | /* (CMD55,56,57,ACMD*) */ |
| 259 | #define CCC_IO_MODE (1<<9) /* (9) I/O mode */ |
| 260 | /* (CMD5,39,40,52,53) */ |
| 261 | #define CCC_SWITCH (1<<10) /* (10) High speed switch */ |
| 262 | /* (CMD6,34,35,36,37,50) */ |
| 263 | /* (11) Reserved */ |
| 264 | /* (CMD?) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 265 | |
| 266 | /* |
| 267 | * CSD field definitions |
| 268 | */ |
| 269 | |
| 270 | #define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ |
| 271 | #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 272 | #define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */ |
| 273 | #define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | |
| 275 | #define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ |
| 276 | #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ |
| 277 | #define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 278 | #define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */ |
| 279 | #define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 280 | |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 281 | /* |
| 282 | * EXT_CSD fields |
| 283 | */ |
| 284 | |
SamarV-121 | b575711 | 2020-09-21 05:47:44 +0000 | [diff] [blame] | 285 | #define EXT_CSD_CMDQ 15 /* R/W */ |
| 286 | #define EXT_CSD_BARRIER_CTRL 31 /* R/W */ |
Seungwon Jeon | 881d1c2 | 2011-10-14 14:03:21 +0900 | [diff] [blame] | 287 | #define EXT_CSD_FLUSH_CACHE 32 /* W */ |
| 288 | #define EXT_CSD_CACHE_CTRL 33 /* R/W */ |
Girish K S | bec8726 | 2011-10-13 12:04:16 +0530 | [diff] [blame] | 289 | #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ |
Seungwon Jeon | abd9ac1 | 2013-02-06 17:01:43 +0900 | [diff] [blame] | 290 | #define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */ |
| 291 | #define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */ |
| 292 | #define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */ |
| 293 | #define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */ |
Saugata Das | 4265900 | 2011-12-21 13:09:17 +0530 | [diff] [blame] | 294 | #define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */ |
Namjae Jeon | e0c368d | 2011-10-06 23:41:38 +0900 | [diff] [blame] | 295 | #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ |
Grégory Soutadé | 69803d4 | 2014-09-15 17:47:09 +0200 | [diff] [blame] | 296 | #define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */ |
Chuanxiao Dong | 709de99 | 2011-01-22 04:09:41 +0800 | [diff] [blame] | 297 | #define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */ |
| 298 | #define EXT_CSD_PARTITION_SUPPORT 160 /* RO */ |
Jaehoon Chung | eb0d8f1 | 2011-10-18 01:26:42 -0400 | [diff] [blame] | 299 | #define EXT_CSD_HPI_MGMT 161 /* R/W */ |
Adrian Hunter | b249951 | 2011-08-29 16:42:11 +0300 | [diff] [blame] | 300 | #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ |
Jaehoon Chung | 950d56a | 2012-09-17 08:42:02 +0000 | [diff] [blame] | 301 | #define EXT_CSD_BKOPS_EN 163 /* R/W */ |
| 302 | #define EXT_CSD_BKOPS_START 164 /* W */ |
Kyungmin Park | d9ddd62 | 2011-10-14 14:15:48 +0900 | [diff] [blame] | 303 | #define EXT_CSD_SANITIZE_START 165 /* W */ |
Andrei Warkentin | f4c5522 | 2011-03-31 18:40:00 -0500 | [diff] [blame] | 304 | #define EXT_CSD_WR_REL_PARAM 166 /* RO */ |
Loic Pallardy | 090d25f | 2012-11-17 18:08:24 -0500 | [diff] [blame] | 305 | #define EXT_CSD_RPMB_MULT 168 /* RO */ |
Gwendal Grignou | 0f76242 | 2014-10-16 11:27:16 -0700 | [diff] [blame] | 306 | #define EXT_CSD_FW_CONFIG 169 /* R/W */ |
Johan Rudholm | add710e | 2011-12-02 08:51:06 +0100 | [diff] [blame] | 307 | #define EXT_CSD_BOOT_WP 173 /* R/W */ |
Adrian Hunter | dfe86cb | 2010-08-11 14:17:46 -0700 | [diff] [blame] | 308 | #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ |
Andrei Warkentin | 371a689 | 2011-04-11 18:10:25 -0500 | [diff] [blame] | 309 | #define EXT_CSD_PART_CONFIG 179 /* R/W */ |
Adrian Hunter | dfe86cb | 2010-08-11 14:17:46 -0700 | [diff] [blame] | 310 | #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ |
| 311 | #define EXT_CSD_BUS_WIDTH 183 /* R/W */ |
SamarV-121 | b575711 | 2020-09-21 05:47:44 +0000 | [diff] [blame] | 312 | #define EXT_CSD_STORBE_SUPPORT 184 /* R/W */ |
Adrian Hunter | dfe86cb | 2010-08-11 14:17:46 -0700 | [diff] [blame] | 313 | #define EXT_CSD_HS_TIMING 185 /* R/W */ |
Girish K S | b87d8db | 2011-09-23 20:41:47 +0530 | [diff] [blame] | 314 | #define EXT_CSD_POWER_CLASS 187 /* R/W */ |
Adrian Hunter | dfe86cb | 2010-08-11 14:17:46 -0700 | [diff] [blame] | 315 | #define EXT_CSD_REV 192 /* RO */ |
| 316 | #define EXT_CSD_STRUCTURE 194 /* RO */ |
| 317 | #define EXT_CSD_CARD_TYPE 196 /* RO */ |
Adrian Hunter | b097e07 | 2015-02-06 14:12:57 +0200 | [diff] [blame] | 318 | #define EXT_CSD_DRIVER_STRENGTH 197 /* RO */ |
Jaehoon Chung | eb0d8f1 | 2011-10-18 01:26:42 -0400 | [diff] [blame] | 319 | #define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */ |
Andrei Warkentin | 371a689 | 2011-04-11 18:10:25 -0500 | [diff] [blame] | 320 | #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */ |
Girish K S | b87d8db | 2011-09-23 20:41:47 +0530 | [diff] [blame] | 321 | #define EXT_CSD_PWR_CL_52_195 200 /* RO */ |
| 322 | #define EXT_CSD_PWR_CL_26_195 201 /* RO */ |
| 323 | #define EXT_CSD_PWR_CL_52_360 202 /* RO */ |
| 324 | #define EXT_CSD_PWR_CL_26_360 203 /* RO */ |
Adrian Hunter | dfe86cb | 2010-08-11 14:17:46 -0700 | [diff] [blame] | 325 | #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ |
| 326 | #define EXT_CSD_S_A_TIMEOUT 217 /* RO */ |
Andrei Warkentin | f4c5522 | 2011-03-31 18:40:00 -0500 | [diff] [blame] | 327 | #define EXT_CSD_REL_WR_SEC_C 222 /* RO */ |
Chuanxiao Dong | 709de99 | 2011-01-22 04:09:41 +0800 | [diff] [blame] | 328 | #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ |
Adrian Hunter | dfe86cb | 2010-08-11 14:17:46 -0700 | [diff] [blame] | 329 | #define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ |
| 330 | #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ |
Andrei Warkentin | 371a689 | 2011-04-11 18:10:25 -0500 | [diff] [blame] | 331 | #define EXT_CSD_BOOT_MULT 226 /* RO */ |
Adrian Hunter | dfe86cb | 2010-08-11 14:17:46 -0700 | [diff] [blame] | 332 | #define EXT_CSD_SEC_TRIM_MULT 229 /* RO */ |
| 333 | #define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ |
| 334 | #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ |
| 335 | #define EXT_CSD_TRIM_MULT 232 /* RO */ |
Girish K S | b87d8db | 2011-09-23 20:41:47 +0530 | [diff] [blame] | 336 | #define EXT_CSD_PWR_CL_200_195 236 /* RO */ |
| 337 | #define EXT_CSD_PWR_CL_200_360 237 /* RO */ |
| 338 | #define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */ |
| 339 | #define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */ |
SamarV-121 | b575711 | 2020-09-21 05:47:44 +0000 | [diff] [blame] | 340 | #define EXT_CSD_CACHE_FLUSH_POLICY 240 /* RO */ |
Jaehoon Chung | 950d56a | 2012-09-17 08:42:02 +0000 | [diff] [blame] | 341 | #define EXT_CSD_BKOPS_STATUS 246 /* RO */ |
Girish K S | b87d8db | 2011-09-23 20:41:47 +0530 | [diff] [blame] | 342 | #define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ |
Seungwon Jeon | b23cf0b | 2011-09-23 14:15:29 +0900 | [diff] [blame] | 343 | #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ |
Seungwon Jeon | 881d1c2 | 2011-10-14 14:03:21 +0900 | [diff] [blame] | 344 | #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ |
Seungwon Jeon | 0a5b643 | 2014-04-23 17:14:58 +0900 | [diff] [blame] | 345 | #define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ |
Gwendal Grignou | 0f76242 | 2014-10-16 11:27:16 -0700 | [diff] [blame] | 346 | #define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */ |
SamarV-121 | b575711 | 2020-09-21 05:47:44 +0000 | [diff] [blame] | 347 | #define EXT_CSD_DEVICE_LIFE_TIME_EST_TYPE_A 268 /* RO, 8 bytes */ |
| 348 | #define EXT_CSD_DEVICE_LIFE_TIME_EST_TYPE_B 269 /* RO, 8 bytes */ |
| 349 | #define EXT_CSD_CMDQ_DEPTH 307 /* RO */ |
| 350 | #define EXT_CSD_CMDQ_SUPPORT 308 /* RO */ |
| 351 | #define EXT_CSD_BARRIER_SUPPORT 486 /* RO */ |
| 352 | #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ |
| 353 | #define EXT_CSD_PRE_EOL_INFO 267 /* RO */ |
| 354 | #define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */ |
| 355 | #define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */ |
Gwendal Grignou | 0f76242 | 2014-10-16 11:27:16 -0700 | [diff] [blame] | 356 | #define EXT_CSD_SUPPORTED_MODE 493 /* RO */ |
Saugata Das | 4265900 | 2011-12-21 13:09:17 +0530 | [diff] [blame] | 357 | #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ |
| 358 | #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ |
Seungwon Jeon | abd9ac1 | 2013-02-06 17:01:43 +0900 | [diff] [blame] | 359 | #define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */ |
| 360 | #define EXT_CSD_MAX_PACKED_READS 501 /* RO */ |
Jaehoon Chung | 950d56a | 2012-09-17 08:42:02 +0000 | [diff] [blame] | 361 | #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ |
Jaehoon Chung | eb0d8f1 | 2011-10-18 01:26:42 -0400 | [diff] [blame] | 362 | #define EXT_CSD_HPI_FEATURES 503 /* RO */ |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 363 | |
| 364 | /* |
| 365 | * EXT_CSD field definitions |
| 366 | */ |
| 367 | |
SamarV-121 | b575711 | 2020-09-21 05:47:44 +0000 | [diff] [blame] | 368 | #define EXT_CSD_WR_REL_PARAM_EN (1<<2) |
| 369 | #define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1<<4) |
Andrei Warkentin | f4c5522 | 2011-03-31 18:40:00 -0500 | [diff] [blame] | 370 | |
Johan Rudholm | add710e | 2011-12-02 08:51:06 +0100 | [diff] [blame] | 371 | #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40) |
| 372 | #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10) |
| 373 | #define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04) |
| 374 | #define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01) |
| 375 | |
Andrei Warkentin | 371a689 | 2011-04-11 18:10:25 -0500 | [diff] [blame] | 376 | #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7) |
| 377 | #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1) |
Loic Pallardy | 090d25f | 2012-11-17 18:08:24 -0500 | [diff] [blame] | 378 | #define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3) |
Namjae Jeon | e0c368d | 2011-10-06 23:41:38 +0900 | [diff] [blame] | 379 | #define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4) |
| 380 | |
Grégory Soutadé | 69803d4 | 2014-09-15 17:47:09 +0200 | [diff] [blame] | 381 | #define EXT_CSD_PART_SETTING_COMPLETED (0x1) |
Namjae Jeon | e0c368d | 2011-10-06 23:41:38 +0900 | [diff] [blame] | 382 | #define EXT_CSD_PART_SUPPORT_PART_EN (0x1) |
Andrei Warkentin | 371a689 | 2011-04-11 18:10:25 -0500 | [diff] [blame] | 383 | |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 384 | #define EXT_CSD_CMD_SET_NORMAL (1<<0) |
| 385 | #define EXT_CSD_CMD_SET_SECURE (1<<1) |
| 386 | #define EXT_CSD_CMD_SET_CPSECURE (1<<2) |
| 387 | |
Seungwon Jeon | 2415c0e | 2014-04-23 17:07:58 +0900 | [diff] [blame] | 388 | #define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */ |
| 389 | #define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */ |
| 390 | #define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \ |
| 391 | EXT_CSD_CARD_TYPE_HS_52) |
Hanumath Prasad | dfc13e8 | 2010-09-30 17:37:23 -0400 | [diff] [blame] | 392 | #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ |
| 393 | /* DDR mode @1.8V or 3V I/O */ |
| 394 | #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ |
| 395 | /* DDR mode @1.2V I/O */ |
| 396 | #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ |
| 397 | | EXT_CSD_CARD_TYPE_DDR_1_2V) |
Seungwon Jeon | 2415c0e | 2014-04-23 17:07:58 +0900 | [diff] [blame] | 398 | #define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */ |
| 399 | #define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */ |
Girish K S | a4924c7 | 2012-01-11 14:04:52 -0500 | [diff] [blame] | 400 | /* SDR mode @1.2V I/O */ |
Seungwon Jeon | 2415c0e | 2014-04-23 17:07:58 +0900 | [diff] [blame] | 401 | #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ |
| 402 | EXT_CSD_CARD_TYPE_HS200_1_2V) |
Seungwon Jeon | 0a5b643 | 2014-04-23 17:14:58 +0900 | [diff] [blame] | 403 | #define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */ |
| 404 | #define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */ |
| 405 | #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ |
| 406 | EXT_CSD_CARD_TYPE_HS400_1_2V) |
Girish K S | a4924c7 | 2012-01-11 14:04:52 -0500 | [diff] [blame] | 407 | |
Philip Langdale | e45a1bd | 2006-10-29 10:14:19 +0100 | [diff] [blame] | 408 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ |
| 409 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ |
| 410 | #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ |
Hanumath Prasad | dfc13e8 | 2010-09-30 17:37:23 -0400 | [diff] [blame] | 411 | #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ |
| 412 | #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ |
SamarV-121 | b575711 | 2020-09-21 05:47:44 +0000 | [diff] [blame] | 413 | #define EXT_CSD_STROBE_ENHANCED_EN (1 << 7) /* Card in enhanced strobe mode */ |
Philip Langdale | e45a1bd | 2006-10-29 10:14:19 +0100 | [diff] [blame] | 414 | |
Seungwon Jeon | 577fb13 | 2014-04-23 17:08:44 +0900 | [diff] [blame] | 415 | #define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ |
| 416 | #define EXT_CSD_TIMING_HS 1 /* High speed */ |
| 417 | #define EXT_CSD_TIMING_HS200 2 /* HS200 */ |
Seungwon Jeon | 0a5b643 | 2014-04-23 17:14:58 +0900 | [diff] [blame] | 418 | #define EXT_CSD_TIMING_HS400 3 /* HS400 */ |
Adrian Hunter | cc4f414 | 2015-02-06 14:12:58 +0200 | [diff] [blame] | 419 | #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */ |
Seungwon Jeon | 577fb13 | 2014-04-23 17:08:44 +0900 | [diff] [blame] | 420 | |
Adrian Hunter | dfe86cb | 2010-08-11 14:17:46 -0700 | [diff] [blame] | 421 | #define EXT_CSD_SEC_ER_EN BIT(0) |
| 422 | #define EXT_CSD_SEC_BD_BLK_EN BIT(2) |
| 423 | #define EXT_CSD_SEC_GB_CL_EN BIT(4) |
Kyungmin Park | d9ddd62 | 2011-10-14 14:15:48 +0900 | [diff] [blame] | 424 | #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */ |
Adrian Hunter | dfe86cb | 2010-08-11 14:17:46 -0700 | [diff] [blame] | 425 | |
Adrian Hunter | b249951 | 2011-08-29 16:42:11 +0300 | [diff] [blame] | 426 | #define EXT_CSD_RST_N_EN_MASK 0x3 |
| 427 | #define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */ |
| 428 | |
Girish K S | bec8726 | 2011-10-13 12:04:16 +0530 | [diff] [blame] | 429 | #define EXT_CSD_NO_POWER_NOTIFICATION 0 |
| 430 | #define EXT_CSD_POWER_ON 1 |
| 431 | #define EXT_CSD_POWER_OFF_SHORT 2 |
| 432 | #define EXT_CSD_POWER_OFF_LONG 3 |
| 433 | |
Girish K S | b87d8db | 2011-09-23 20:41:47 +0530 | [diff] [blame] | 434 | #define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */ |
| 435 | #define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */ |
| 436 | #define EXT_CSD_PWR_CL_8BIT_SHIFT 4 |
| 437 | #define EXT_CSD_PWR_CL_4BIT_SHIFT 0 |
Seungwon Jeon | abd9ac1 | 2013-02-06 17:01:43 +0900 | [diff] [blame] | 438 | |
| 439 | #define EXT_CSD_PACKED_EVENT_EN BIT(3) |
| 440 | |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 441 | /* |
Jaehoon Chung | 950d56a | 2012-09-17 08:42:02 +0000 | [diff] [blame] | 442 | * EXCEPTION_EVENT_STATUS field |
| 443 | */ |
| 444 | #define EXT_CSD_URGENT_BKOPS BIT(0) |
| 445 | #define EXT_CSD_DYNCAP_NEEDED BIT(1) |
| 446 | #define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2) |
| 447 | #define EXT_CSD_PACKED_FAILURE BIT(3) |
| 448 | |
Seungwon Jeon | abd9ac1 | 2013-02-06 17:01:43 +0900 | [diff] [blame] | 449 | #define EXT_CSD_PACKED_GENERIC_ERROR BIT(0) |
| 450 | #define EXT_CSD_PACKED_INDEXED_ERROR BIT(1) |
| 451 | |
Jaehoon Chung | 950d56a | 2012-09-17 08:42:02 +0000 | [diff] [blame] | 452 | /* |
| 453 | * BKOPS status level |
| 454 | */ |
| 455 | #define EXT_CSD_BKOPS_LEVEL_2 0x2 |
| 456 | |
| 457 | /* |
Alexey Skidanov | 0501be6 | 2015-01-29 10:49:43 +0200 | [diff] [blame] | 458 | * BKOPS modes |
| 459 | */ |
| 460 | #define EXT_CSD_MANUAL_BKOPS_MASK 0x01 |
| 461 | |
| 462 | /* |
Philip Langdale | bce40a3 | 2006-10-21 12:35:02 +0200 | [diff] [blame] | 463 | * MMC_SWITCH access modes |
| 464 | */ |
| 465 | |
| 466 | #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ |
| 467 | #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ |
| 468 | #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ |
| 469 | #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ |
Pierre Ossman | f218278 | 2005-09-06 15:18:55 -0700 | [diff] [blame] | 470 | |
Adrian Hunter | cc4f414 | 2015-02-06 14:12:58 +0200 | [diff] [blame] | 471 | #define mmc_driver_type_mask(n) (1 << (n)) |
| 472 | |
Robert P. J. Day | 100e918 | 2011-05-27 16:04:03 -0400 | [diff] [blame] | 473 | #endif /* LINUX_MMC_MMC_H */ |