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Zang Roy-r619119eb90a02007-03-09 13:27:28 +08001/*
2 * MPC85xx/86xx PCI Express structure define
3 *
4 * Copyright 2007 Freescale Semiconductor, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifdef __KERNEL__
Zang Roy-r619119ac4dd32007-07-10 18:46:35 +080014#ifndef __POWERPC_FSL_PCI_H
15#define __POWERPC_FSL_PCI_H
Zang Roy-r619119eb90a02007-03-09 13:27:28 +080016
Zang Roy-r619119ac4dd32007-07-10 18:46:35 +080017#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
18#define PCIE_LTSSM_L0 0x16 /* L0 state */
Kumar Gala54c18192009-05-08 15:05:23 -050019#define PIWAR_EN 0x80000000 /* Enable */
20#define PIWAR_PF 0x20000000 /* prefetch */
21#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
22#define PIWAR_READ_SNOOP 0x00050000
23#define PIWAR_WRITE_SNOOP 0x00005000
Zang Roy-r619119eb90a02007-03-09 13:27:28 +080024
Zang Roy-r619119ac4dd32007-07-10 18:46:35 +080025/* PCI/PCI Express outbound window reg */
26struct pci_outbound_window_regs {
27 __be32 potar; /* 0x.0 - Outbound translation address register */
28 __be32 potear; /* 0x.4 - Outbound translation extended address register */
29 __be32 powbar; /* 0x.8 - Outbound window base address register */
30 u8 res1[4];
31 __be32 powar; /* 0x.10 - Outbound window attributes register */
32 u8 res2[12];
Zang Roy-r619119eb90a02007-03-09 13:27:28 +080033};
34
Zang Roy-r619119ac4dd32007-07-10 18:46:35 +080035/* PCI/PCI Express inbound window reg */
36struct pci_inbound_window_regs {
37 __be32 pitar; /* 0x.0 - Inbound translation address register */
38 u8 res1[4];
39 __be32 piwbar; /* 0x.8 - Inbound window base address register */
40 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
41 __be32 piwar; /* 0x.10 - Inbound window attributes register */
42 u8 res2[12];
43};
44
45/* PCI/PCI Express IO block registers for 85xx/86xx */
46struct ccsr_pci {
47 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
48 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
49 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
50 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
51 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
52 u8 res2[12];
53 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
54 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
55 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
56 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
57 u8 res3[3024];
58
59/* PCI/PCI Express outbound window 0-4
60 * Window 0 is the default window and is the only window enabled upon reset.
61 * The default outbound register set is used when a transaction misses
62 * in all of the other outbound windows.
63 */
64 struct pci_outbound_window_regs pow[5];
65
66 u8 res14[256];
67
68/* PCI/PCI Express inbound window 3-1
69 * inbound window 1 supports only a 32-bit base address and does not
70 * define an inbound window base extended address register.
71 */
72 struct pci_inbound_window_regs piw[3];
73
74 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
75 u8 res21[4];
76 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
77 u8 res22[4];
78 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
79 u8 res23[12];
80 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
81 u8 res24[4];
82 __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
83 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
84 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
85 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
86};
87
88extern int fsl_add_bridge(struct device_node *dev, int is_primary);
Kumar Gala6c0a11c2007-07-19 15:29:53 -050089extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
John Rigby76fe1ff2008-06-26 11:07:57 -060090extern int mpc83xx_add_bridge(struct device_node *dev);
Kumar Galab8f44ec2010-08-05 02:45:08 -050091u64 fsl_pci_immrbar_base(struct pci_controller *hose);
Zang Roy-r619119ac4dd32007-07-10 18:46:35 +080092
93#endif /* __POWERPC_FSL_PCI_H */
Zang Roy-r619119eb90a02007-03-09 13:27:28 +080094#endif /* __KERNEL__ */