Wu Zhangjin | 85749d2 | 2009-07-02 23:26:45 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology |
| 3 | * Author: Fuxin Zhang, zhangfx@lemote.com |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | */ |
| 10 | #include <linux/delay.h> |
| 11 | #include <linux/interrupt.h> |
| 12 | |
| 13 | #include <loongson.h> |
| 14 | /* |
| 15 | * the first level int-handler will jump here if it is a bonito irq |
| 16 | */ |
| 17 | void bonito_irqdispatch(void) |
| 18 | { |
| 19 | u32 int_status; |
| 20 | int i; |
| 21 | |
| 22 | /* workaround the IO dma problem: let cpu looping to allow DMA finish */ |
Wu Zhangjin | e2fee57 | 2009-10-16 14:17:19 +0800 | [diff] [blame] | 23 | int_status = LOONGSON_INTISR; |
Wu Zhangjin | 85749d2 | 2009-07-02 23:26:45 +0800 | [diff] [blame] | 24 | if (int_status & (1 << 10)) { |
| 25 | while (int_status & (1 << 10)) { |
| 26 | udelay(1); |
Wu Zhangjin | e2fee57 | 2009-10-16 14:17:19 +0800 | [diff] [blame] | 27 | int_status = LOONGSON_INTISR; |
Wu Zhangjin | 85749d2 | 2009-07-02 23:26:45 +0800 | [diff] [blame] | 28 | } |
| 29 | } |
| 30 | |
| 31 | /* Get pending sources, masked by current enables */ |
Wu Zhangjin | e2fee57 | 2009-10-16 14:17:19 +0800 | [diff] [blame] | 32 | int_status = LOONGSON_INTISR & LOONGSON_INTEN; |
Wu Zhangjin | 85749d2 | 2009-07-02 23:26:45 +0800 | [diff] [blame] | 33 | |
| 34 | if (int_status != 0) { |
| 35 | i = __ffs(int_status); |
| 36 | int_status &= ~(1 << i); |
Wu Zhangjin | e2fee57 | 2009-10-16 14:17:19 +0800 | [diff] [blame] | 37 | do_IRQ(LOONGSON_IRQ_BASE + i); |
Wu Zhangjin | 85749d2 | 2009-07-02 23:26:45 +0800 | [diff] [blame] | 38 | } |
| 39 | } |
| 40 | |
| 41 | asmlinkage void plat_irq_dispatch(void) |
| 42 | { |
| 43 | unsigned int pending; |
| 44 | |
| 45 | pending = read_c0_cause() & read_c0_status() & ST0_IM; |
| 46 | |
| 47 | /* machine-specific plat_irq_dispatch */ |
| 48 | mach_irq_dispatch(pending); |
| 49 | } |
| 50 | |
| 51 | void __init arch_init_irq(void) |
| 52 | { |
| 53 | /* |
| 54 | * Clear all of the interrupts while we change the able around a bit. |
| 55 | * int-handler is not on bootstrap |
| 56 | */ |
| 57 | clear_c0_status(ST0_IM | ST0_BEV); |
Wu Zhangjin | 85749d2 | 2009-07-02 23:26:45 +0800 | [diff] [blame] | 58 | |
| 59 | /* setting irq trigger mode */ |
| 60 | set_irq_trigger_mode(); |
| 61 | |
| 62 | /* no steer */ |
Wu Zhangjin | e2fee57 | 2009-10-16 14:17:19 +0800 | [diff] [blame] | 63 | LOONGSON_INTSTEER = 0; |
Wu Zhangjin | 85749d2 | 2009-07-02 23:26:45 +0800 | [diff] [blame] | 64 | |
| 65 | /* |
| 66 | * Mask out all interrupt by writing "1" to all bit position in |
| 67 | * the interrupt reset reg. |
| 68 | */ |
Wu Zhangjin | e2fee57 | 2009-10-16 14:17:19 +0800 | [diff] [blame] | 69 | LOONGSON_INTENCLR = ~0; |
Wu Zhangjin | 85749d2 | 2009-07-02 23:26:45 +0800 | [diff] [blame] | 70 | |
| 71 | /* machine specific irq init */ |
| 72 | mach_init_irq(); |
| 73 | } |