blob: eb4acf4528ff4bf12439ccec250a0ff24285a4b0 [file] [log] [blame]
Alex Deucher0fcdb612010-03-24 13:20:41 -04001/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef EVERGREEND_H
25#define EVERGREEND_H
26
Alex Deucher32fcdbf2010-03-24 13:33:47 -040027#define EVERGREEN_MAX_SH_GPRS 256
28#define EVERGREEN_MAX_TEMP_GPRS 16
29#define EVERGREEN_MAX_SH_THREADS 256
30#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31#define EVERGREEN_MAX_FRC_EOV_CNT 16384
32#define EVERGREEN_MAX_BACKENDS 8
33#define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34#define EVERGREEN_MAX_SIMDS 16
35#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36#define EVERGREEN_MAX_PIPES 8
37#define EVERGREEN_MAX_PIPES_MASK 0xFF
38#define EVERGREEN_MAX_LDS_NUM 0xFFFF
39
Alex Deucher0fcdb612010-03-24 13:20:41 -040040/* Registers */
41
Alex Deucher32fcdbf2010-03-24 13:33:47 -040042#define RCU_IND_INDEX 0x100
43#define RCU_IND_DATA 0x104
44
45#define GRBM_GFX_INDEX 0x802C
46#define INSTANCE_INDEX(x) ((x) << 0)
47#define SE_INDEX(x) ((x) << 16)
48#define INSTANCE_BROADCAST_WRITES (1 << 30)
49#define SE_BROADCAST_WRITES (1 << 31)
50#define RLC_GFX_INDEX 0x3fC4
51#define CC_GC_SHADER_PIPE_CONFIG 0x8950
52#define WRITE_DIS (1 << 0)
53#define CC_RB_BACKEND_DISABLE 0x98F4
54#define BACKEND_DISABLE(x) ((x) << 16)
55#define GB_ADDR_CONFIG 0x98F8
56#define NUM_PIPES(x) ((x) << 0)
57#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
58#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
59#define NUM_SHADER_ENGINES(x) ((x) << 12)
60#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
61#define NUM_GPUS(x) ((x) << 20)
62#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
63#define ROW_SIZE(x) ((x) << 28)
64#define GB_BACKEND_MAP 0x98FC
65#define DMIF_ADDR_CONFIG 0xBD4
66#define HDP_ADDR_CONFIG 0x2F48
67
Alex Deucher0fcdb612010-03-24 13:20:41 -040068#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
Alex Deucher32fcdbf2010-03-24 13:33:47 -040069#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
Alex Deucher0fcdb612010-03-24 13:20:41 -040070
71#define CGTS_SYS_TCC_DISABLE 0x3F90
72#define CGTS_TCC_DISABLE 0x9148
73#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
74#define CGTS_USER_TCC_DISABLE 0x914C
75
76#define CONFIG_MEMSIZE 0x5428
77
Alex Deucher32fcdbf2010-03-24 13:33:47 -040078#define CP_ME_CNTL 0x86D8
79#define CP_ME_HALT (1 << 28)
80#define CP_PFP_HALT (1 << 26)
Alex Deucher0fcdb612010-03-24 13:20:41 -040081#define CP_ME_RAM_DATA 0xC160
82#define CP_ME_RAM_RADDR 0xC158
83#define CP_ME_RAM_WADDR 0xC15C
84#define CP_MEQ_THRESHOLDS 0x8764
85#define STQ_SPLIT(x) ((x) << 0)
86#define CP_PERFMON_CNTL 0x87FC
87#define CP_PFP_UCODE_ADDR 0xC150
88#define CP_PFP_UCODE_DATA 0xC154
89#define CP_QUEUE_THRESHOLDS 0x8760
90#define ROQ_IB1_START(x) ((x) << 0)
91#define ROQ_IB2_START(x) ((x) << 8)
Alex Deucherfe251e22010-03-24 13:36:43 -040092#define CP_RB_BASE 0xC100
Alex Deucher0fcdb612010-03-24 13:20:41 -040093#define CP_RB_CNTL 0xC104
Alex Deucher32fcdbf2010-03-24 13:33:47 -040094#define RB_BUFSZ(x) ((x) << 0)
95#define RB_BLKSZ(x) ((x) << 8)
96#define RB_NO_UPDATE (1 << 27)
97#define RB_RPTR_WR_ENA (1 << 31)
Alex Deucher0fcdb612010-03-24 13:20:41 -040098#define BUF_SWAP_32BIT (2 << 16)
99#define CP_RB_RPTR 0x8700
100#define CP_RB_RPTR_ADDR 0xC10C
Alex Deucher0f234f5f2011-02-13 19:06:33 -0500101#define RB_RPTR_SWAP(x) ((x) << 0)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400102#define CP_RB_RPTR_ADDR_HI 0xC110
103#define CP_RB_RPTR_WR 0xC108
104#define CP_RB_WPTR 0xC114
105#define CP_RB_WPTR_ADDR 0xC118
106#define CP_RB_WPTR_ADDR_HI 0xC11C
107#define CP_RB_WPTR_DELAY 0x8704
108#define CP_SEM_WAIT_TIMER 0x85BC
Alex Deucherfe251e22010-03-24 13:36:43 -0400109#define CP_DEBUG 0xC1FC
Alex Deucher0fcdb612010-03-24 13:20:41 -0400110
111
112#define GC_USER_SHADER_PIPE_CONFIG 0x8954
113#define INACTIVE_QD_PIPES(x) ((x) << 8)
114#define INACTIVE_QD_PIPES_MASK 0x0000FF00
115#define INACTIVE_SIMDS(x) ((x) << 16)
116#define INACTIVE_SIMDS_MASK 0x00FF0000
117
118#define GRBM_CNTL 0x8000
119#define GRBM_READ_TIMEOUT(x) ((x) << 0)
120#define GRBM_SOFT_RESET 0x8020
Alex Deucher747943e2010-03-24 13:26:36 -0400121#define SOFT_RESET_CP (1 << 0)
122#define SOFT_RESET_CB (1 << 1)
123#define SOFT_RESET_DB (1 << 3)
124#define SOFT_RESET_PA (1 << 5)
125#define SOFT_RESET_SC (1 << 6)
126#define SOFT_RESET_SPI (1 << 8)
127#define SOFT_RESET_SH (1 << 9)
128#define SOFT_RESET_SX (1 << 10)
129#define SOFT_RESET_TC (1 << 11)
130#define SOFT_RESET_TA (1 << 12)
131#define SOFT_RESET_VC (1 << 13)
132#define SOFT_RESET_VGT (1 << 14)
133
Alex Deucher0fcdb612010-03-24 13:20:41 -0400134#define GRBM_STATUS 0x8010
135#define CMDFIFO_AVAIL_MASK 0x0000000F
Alex Deucher747943e2010-03-24 13:26:36 -0400136#define SRBM_RQ_PENDING (1 << 5)
137#define CF_RQ_PENDING (1 << 7)
138#define PF_RQ_PENDING (1 << 8)
139#define GRBM_EE_BUSY (1 << 10)
140#define SX_CLEAN (1 << 11)
141#define DB_CLEAN (1 << 12)
142#define CB_CLEAN (1 << 13)
143#define TA_BUSY (1 << 14)
144#define VGT_BUSY_NO_DMA (1 << 16)
145#define VGT_BUSY (1 << 17)
146#define SX_BUSY (1 << 20)
147#define SH_BUSY (1 << 21)
148#define SPI_BUSY (1 << 22)
149#define SC_BUSY (1 << 24)
150#define PA_BUSY (1 << 25)
151#define DB_BUSY (1 << 26)
152#define CP_COHERENCY_BUSY (1 << 28)
153#define CP_BUSY (1 << 29)
154#define CB_BUSY (1 << 30)
155#define GUI_ACTIVE (1 << 31)
156#define GRBM_STATUS_SE0 0x8014
157#define GRBM_STATUS_SE1 0x8018
158#define SE_SX_CLEAN (1 << 0)
159#define SE_DB_CLEAN (1 << 1)
160#define SE_CB_CLEAN (1 << 2)
161#define SE_TA_BUSY (1 << 25)
162#define SE_SX_BUSY (1 << 26)
163#define SE_SPI_BUSY (1 << 27)
164#define SE_SH_BUSY (1 << 28)
165#define SE_SC_BUSY (1 << 29)
166#define SE_DB_BUSY (1 << 30)
167#define SE_CB_BUSY (1 << 31)
Alex Deuchere33df252010-11-22 17:56:32 -0500168/* evergreen */
Alex Deucher21a81222010-07-02 12:58:16 -0400169#define CG_MULT_THERMAL_STATUS 0x740
170#define ASIC_T(x) ((x) << 16)
171#define ASIC_T_MASK 0x7FF0000
172#define ASIC_T_SHIFT 16
Alex Deuchere33df252010-11-22 17:56:32 -0500173/* APU */
174#define CG_THERMAL_STATUS 0x678
Alex Deucher21a81222010-07-02 12:58:16 -0400175
Alex Deucher0fcdb612010-03-24 13:20:41 -0400176#define HDP_HOST_PATH_CNTL 0x2C00
177#define HDP_NONSURFACE_BASE 0x2C04
178#define HDP_NONSURFACE_INFO 0x2C08
179#define HDP_NONSURFACE_SIZE 0x2C0C
Alex Deucher6f2f48a2010-12-15 11:01:56 -0500180#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
Alex Deucher0fcdb612010-03-24 13:20:41 -0400181#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
182#define HDP_TILING_CONFIG 0x2F3C
183
184#define MC_SHARED_CHMAP 0x2004
185#define NOOFCHAN_SHIFT 12
186#define NOOFCHAN_MASK 0x00003000
Alex Deucher9535ab72010-11-22 17:56:18 -0500187#define MC_SHARED_CHREMAP 0x2008
Alex Deucher0fcdb612010-03-24 13:20:41 -0400188
189#define MC_ARB_RAMCFG 0x2760
190#define NOOFBANK_SHIFT 0
191#define NOOFBANK_MASK 0x00000003
192#define NOOFRANK_SHIFT 2
193#define NOOFRANK_MASK 0x00000004
194#define NOOFROWS_SHIFT 3
195#define NOOFROWS_MASK 0x00000038
196#define NOOFCOLS_SHIFT 6
197#define NOOFCOLS_MASK 0x000000C0
198#define CHANSIZE_SHIFT 8
199#define CHANSIZE_MASK 0x00000100
200#define BURSTLENGTH_SHIFT 9
201#define BURSTLENGTH_MASK 0x00000200
202#define CHANSIZE_OVERRIDE (1 << 11)
203#define MC_VM_AGP_TOP 0x2028
204#define MC_VM_AGP_BOT 0x202C
205#define MC_VM_AGP_BASE 0x2030
206#define MC_VM_FB_LOCATION 0x2024
Alex Deucherb4183e32010-12-15 11:04:10 -0500207#define MC_FUS_VM_FB_OFFSET 0x2898
Alex Deucher0fcdb612010-03-24 13:20:41 -0400208#define MC_VM_MB_L1_TLB0_CNTL 0x2234
209#define MC_VM_MB_L1_TLB1_CNTL 0x2238
210#define MC_VM_MB_L1_TLB2_CNTL 0x223C
211#define MC_VM_MB_L1_TLB3_CNTL 0x2240
212#define ENABLE_L1_TLB (1 << 0)
213#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
214#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
215#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
216#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
217#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
218#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
219#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
220#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
221#define MC_VM_MD_L1_TLB0_CNTL 0x2654
222#define MC_VM_MD_L1_TLB1_CNTL 0x2658
223#define MC_VM_MD_L1_TLB2_CNTL 0x265C
224#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
225#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
226#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
227
228#define PA_CL_ENHANCE 0x8A14
229#define CLIP_VTX_REORDER_ENA (1 << 0)
230#define NUM_CLIP_SEQ(x) ((x) << 1)
231#define PA_SC_AA_CONFIG 0x28C04
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400232#define MSAA_NUM_SAMPLES_SHIFT 0
233#define MSAA_NUM_SAMPLES_MASK 0x3
Alex Deucher0fcdb612010-03-24 13:20:41 -0400234#define PA_SC_CLIPRECT_RULE 0x2820C
235#define PA_SC_EDGERULE 0x28230
236#define PA_SC_FIFO_SIZE 0x8BCC
237#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
238#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400239#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400240#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400241#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
242#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400243#define PA_SC_LINE_STIPPLE 0x28A0C
Alex Deucher12920592011-02-02 12:37:40 -0500244#define PA_SU_LINE_STIPPLE_VALUE 0x8A60
Alex Deucher0fcdb612010-03-24 13:20:41 -0400245#define PA_SC_LINE_STIPPLE_STATE 0x8B10
246
247#define SCRATCH_REG0 0x8500
248#define SCRATCH_REG1 0x8504
249#define SCRATCH_REG2 0x8508
250#define SCRATCH_REG3 0x850C
251#define SCRATCH_REG4 0x8510
252#define SCRATCH_REG5 0x8514
253#define SCRATCH_REG6 0x8518
254#define SCRATCH_REG7 0x851C
255#define SCRATCH_UMSK 0x8540
256#define SCRATCH_ADDR 0x8544
257
258#define SMX_DC_CTL0 0xA020
259#define USE_HASH_FUNCTION (1 << 0)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400260#define NUMBER_OF_SETS(x) ((x) << 1)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400261#define FLUSH_ALL_ON_EVENT (1 << 10)
262#define STALL_ON_EVENT (1 << 11)
263#define SMX_EVENT_CTL 0xA02C
264#define ES_FLUSH_CTL(x) ((x) << 0)
265#define GS_FLUSH_CTL(x) ((x) << 3)
266#define ACK_FLUSH_CTL(x) ((x) << 6)
267#define SYNC_FLUSH_CTL (1 << 8)
268
269#define SPI_CONFIG_CNTL 0x9100
270#define GPR_WRITE_PRIORITY(x) ((x) << 0)
271#define SPI_CONFIG_CNTL_1 0x913C
272#define VTX_DONE_DELAY(x) ((x) << 0)
273#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
274#define SPI_INPUT_Z 0x286D8
275#define SPI_PS_IN_CONTROL_0 0x286CC
276#define NUM_INTERP(x) ((x)<<0)
277#define POSITION_ENA (1<<8)
278#define POSITION_CENTROID (1<<9)
279#define POSITION_ADDR(x) ((x)<<10)
280#define PARAM_GEN(x) ((x)<<15)
281#define PARAM_GEN_ADDR(x) ((x)<<19)
282#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
283#define PERSP_GRADIENT_ENA (1<<28)
284#define LINEAR_GRADIENT_ENA (1<<29)
285#define POSITION_SAMPLE (1<<30)
286#define BARYC_AT_SAMPLE_ENA (1<<31)
287
288#define SQ_CONFIG 0x8C00
289#define VC_ENABLE (1 << 0)
290#define EXPORT_SRC_C (1 << 1)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400291#define CS_PRIO(x) ((x) << 18)
292#define LS_PRIO(x) ((x) << 20)
293#define HS_PRIO(x) ((x) << 22)
294#define PS_PRIO(x) ((x) << 24)
295#define VS_PRIO(x) ((x) << 26)
296#define GS_PRIO(x) ((x) << 28)
297#define ES_PRIO(x) ((x) << 30)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400298#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
299#define NUM_PS_GPRS(x) ((x) << 0)
300#define NUM_VS_GPRS(x) ((x) << 16)
301#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
302#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
303#define NUM_GS_GPRS(x) ((x) << 0)
304#define NUM_ES_GPRS(x) ((x) << 16)
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400305#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
306#define NUM_HS_GPRS(x) ((x) << 0)
307#define NUM_LS_GPRS(x) ((x) << 16)
308#define SQ_THREAD_RESOURCE_MGMT 0x8C18
309#define NUM_PS_THREADS(x) ((x) << 0)
310#define NUM_VS_THREADS(x) ((x) << 8)
311#define NUM_GS_THREADS(x) ((x) << 16)
312#define NUM_ES_THREADS(x) ((x) << 24)
313#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
314#define NUM_HS_THREADS(x) ((x) << 0)
315#define NUM_LS_THREADS(x) ((x) << 8)
316#define SQ_STACK_RESOURCE_MGMT_1 0x8C20
317#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
318#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
319#define SQ_STACK_RESOURCE_MGMT_2 0x8C24
320#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
321#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
322#define SQ_STACK_RESOURCE_MGMT_3 0x8C28
323#define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
324#define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
325#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
326#define SQ_LDS_RESOURCE_MGMT 0x8E2C
327
Alex Deucher0fcdb612010-03-24 13:20:41 -0400328#define SQ_MS_FIFO_SIZES 0x8CF0
329#define CACHE_FIFO_SIZE(x) ((x) << 0)
330#define FETCH_FIFO_HIWATER(x) ((x) << 8)
331#define DONE_FIFO_HIWATER(x) ((x) << 16)
332#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
333
334#define SX_DEBUG_1 0x9058
335#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
336#define SX_EXPORT_BUFFER_SIZES 0x900C
337#define COLOR_BUFFER_SIZE(x) ((x) << 0)
338#define POSITION_BUFFER_SIZE(x) ((x) << 8)
339#define SMX_BUFFER_SIZE(x) ((x) << 16)
340#define SX_MISC 0x28350
341
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400342#define CB_PERF_CTR0_SEL_0 0x9A20
343#define CB_PERF_CTR0_SEL_1 0x9A24
344#define CB_PERF_CTR1_SEL_0 0x9A28
345#define CB_PERF_CTR1_SEL_1 0x9A2C
346#define CB_PERF_CTR2_SEL_0 0x9A30
347#define CB_PERF_CTR2_SEL_1 0x9A34
348#define CB_PERF_CTR3_SEL_0 0x9A38
349#define CB_PERF_CTR3_SEL_1 0x9A3C
350
Alex Deucher0fcdb612010-03-24 13:20:41 -0400351#define TA_CNTL_AUX 0x9508
352#define DISABLE_CUBE_WRAP (1 << 0)
353#define DISABLE_CUBE_ANISO (1 << 1)
354#define SYNC_GRADIENT (1 << 24)
355#define SYNC_WALKER (1 << 25)
356#define SYNC_ALIGNER (1 << 26)
357
Alex Deucher9535ab72010-11-22 17:56:18 -0500358#define TCP_CHAN_STEER_LO 0x960c
359#define TCP_CHAN_STEER_HI 0x9610
360
Alex Deucher0fcdb612010-03-24 13:20:41 -0400361#define VGT_CACHE_INVALIDATION 0x88C4
Alex Deucher32fcdbf2010-03-24 13:33:47 -0400362#define CACHE_INVALIDATION(x) ((x) << 0)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400363#define VC_ONLY 0
364#define TC_ONLY 1
365#define VC_AND_TC 2
366#define AUTO_INVLD_EN(x) ((x) << 6)
367#define NO_AUTO 0
368#define ES_AUTO 1
369#define GS_AUTO 2
370#define ES_AND_GS_AUTO 3
371#define VGT_GS_VERTEX_REUSE 0x88D4
372#define VGT_NUM_INSTANCES 0x8974
373#define VGT_OUT_DEALLOC_CNTL 0x28C5C
374#define DEALLOC_DIST_MASK 0x0000007F
375#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
376#define VTX_REUSE_DEPTH_MASK 0x000000FF
377
378#define VM_CONTEXT0_CNTL 0x1410
379#define ENABLE_CONTEXT (1 << 0)
380#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
381#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
382#define VM_CONTEXT1_CNTL 0x1414
383#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
384#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
385#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
386#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
387#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
388#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
389#define RESPONSE_TYPE_MASK 0x000000F0
390#define RESPONSE_TYPE_SHIFT 4
391#define VM_L2_CNTL 0x1400
392#define ENABLE_L2_CACHE (1 << 0)
393#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
394#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
395#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
396#define VM_L2_CNTL2 0x1404
397#define INVALIDATE_ALL_L1_TLBS (1 << 0)
398#define INVALIDATE_L2_CACHE (1 << 1)
399#define VM_L2_CNTL3 0x1408
400#define BANK_SELECT(x) ((x) << 0)
401#define CACHE_UPDATE_MODE(x) ((x) << 6)
402#define VM_L2_STATUS 0x140C
403#define L2_BUSY (1 << 0)
404
405#define WAIT_UNTIL 0x8040
406
407#define SRBM_STATUS 0x0E50
Alex Deucher747943e2010-03-24 13:26:36 -0400408#define SRBM_SOFT_RESET 0x0E60
409#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
410#define SOFT_RESET_BIF (1 << 1)
411#define SOFT_RESET_CG (1 << 2)
412#define SOFT_RESET_DC (1 << 5)
413#define SOFT_RESET_GRBM (1 << 8)
414#define SOFT_RESET_HDP (1 << 9)
415#define SOFT_RESET_IH (1 << 10)
416#define SOFT_RESET_MC (1 << 11)
417#define SOFT_RESET_RLC (1 << 13)
418#define SOFT_RESET_ROM (1 << 14)
419#define SOFT_RESET_SEM (1 << 15)
420#define SOFT_RESET_VMC (1 << 17)
421#define SOFT_RESET_TST (1 << 21)
422#define SOFT_RESET_REGBB (1 << 22)
423#define SOFT_RESET_ORB (1 << 23)
Alex Deucher0fcdb612010-03-24 13:20:41 -0400424
Alex Deucherf9d9c362010-10-22 02:51:05 -0400425/* display watermarks */
426#define DC_LB_MEMORY_SPLIT 0x6b0c
427#define PRIORITY_A_CNT 0x6b18
428#define PRIORITY_MARK_MASK 0x7fff
429#define PRIORITY_OFF (1 << 16)
430#define PRIORITY_ALWAYS_ON (1 << 20)
431#define PRIORITY_B_CNT 0x6b1c
432#define PIPE0_ARBITRATION_CONTROL3 0x0bf0
433# define LATENCY_WATERMARK_MASK(x) ((x) << 16)
434#define PIPE0_LATENCY_CONTROL 0x0bf4
435# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
436# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
437
Alex Deucher45f9a392010-03-24 13:55:51 -0400438#define IH_RB_CNTL 0x3e00
439# define IH_RB_ENABLE (1 << 0)
440# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
441# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
442# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
443# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
444# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
445# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
446#define IH_RB_BASE 0x3e04
447#define IH_RB_RPTR 0x3e08
448#define IH_RB_WPTR 0x3e0c
449# define RB_OVERFLOW (1 << 0)
450# define WPTR_OFFSET_MASK 0x3fffc
451#define IH_RB_WPTR_ADDR_HI 0x3e10
452#define IH_RB_WPTR_ADDR_LO 0x3e14
453#define IH_CNTL 0x3e18
454# define ENABLE_INTR (1 << 0)
455# define IH_MC_SWAP(x) ((x) << 2)
456# define IH_MC_SWAP_NONE 0
457# define IH_MC_SWAP_16BIT 1
458# define IH_MC_SWAP_32BIT 2
459# define IH_MC_SWAP_64BIT 3
460# define RPTR_REARM (1 << 4)
461# define MC_WRREQ_CREDIT(x) ((x) << 15)
462# define MC_WR_CLEAN_CNT(x) ((x) << 20)
463
464#define CP_INT_CNTL 0xc124
465# define CNTX_BUSY_INT_ENABLE (1 << 19)
466# define CNTX_EMPTY_INT_ENABLE (1 << 20)
467# define SCRATCH_INT_ENABLE (1 << 25)
468# define TIME_STAMP_INT_ENABLE (1 << 26)
469# define IB2_INT_ENABLE (1 << 29)
470# define IB1_INT_ENABLE (1 << 30)
471# define RB_INT_ENABLE (1 << 31)
472#define CP_INT_STATUS 0xc128
473# define SCRATCH_INT_STAT (1 << 25)
474# define TIME_STAMP_INT_STAT (1 << 26)
475# define IB2_INT_STAT (1 << 29)
476# define IB1_INT_STAT (1 << 30)
477# define RB_INT_STAT (1 << 31)
478
479#define GRBM_INT_CNTL 0x8060
480# define RDERR_INT_ENABLE (1 << 0)
481# define GUI_IDLE_INT_ENABLE (1 << 19)
482
483/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
484#define CRTC_STATUS_FRAME_COUNT 0x6e98
485
486/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
487#define VLINE_STATUS 0x6bb8
488# define VLINE_OCCURRED (1 << 0)
489# define VLINE_ACK (1 << 4)
490# define VLINE_STAT (1 << 12)
491# define VLINE_INTERRUPT (1 << 16)
492# define VLINE_INTERRUPT_TYPE (1 << 17)
493/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
494#define VBLANK_STATUS 0x6bbc
495# define VBLANK_OCCURRED (1 << 0)
496# define VBLANK_ACK (1 << 4)
497# define VBLANK_STAT (1 << 12)
498# define VBLANK_INTERRUPT (1 << 16)
499# define VBLANK_INTERRUPT_TYPE (1 << 17)
500
501/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
502#define INT_MASK 0x6b40
503# define VBLANK_INT_MASK (1 << 0)
504# define VLINE_INT_MASK (1 << 4)
505
506#define DISP_INTERRUPT_STATUS 0x60f4
507# define LB_D1_VLINE_INTERRUPT (1 << 2)
508# define LB_D1_VBLANK_INTERRUPT (1 << 3)
509# define DC_HPD1_INTERRUPT (1 << 17)
510# define DC_HPD1_RX_INTERRUPT (1 << 18)
511# define DACA_AUTODETECT_INTERRUPT (1 << 22)
512# define DACB_AUTODETECT_INTERRUPT (1 << 23)
513# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
514# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
515#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
516# define LB_D2_VLINE_INTERRUPT (1 << 2)
517# define LB_D2_VBLANK_INTERRUPT (1 << 3)
518# define DC_HPD2_INTERRUPT (1 << 17)
519# define DC_HPD2_RX_INTERRUPT (1 << 18)
520# define DISP_TIMER_INTERRUPT (1 << 24)
521#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
522# define LB_D3_VLINE_INTERRUPT (1 << 2)
523# define LB_D3_VBLANK_INTERRUPT (1 << 3)
524# define DC_HPD3_INTERRUPT (1 << 17)
525# define DC_HPD3_RX_INTERRUPT (1 << 18)
526#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
527# define LB_D4_VLINE_INTERRUPT (1 << 2)
528# define LB_D4_VBLANK_INTERRUPT (1 << 3)
529# define DC_HPD4_INTERRUPT (1 << 17)
530# define DC_HPD4_RX_INTERRUPT (1 << 18)
531#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
532# define LB_D5_VLINE_INTERRUPT (1 << 2)
533# define LB_D5_VBLANK_INTERRUPT (1 << 3)
534# define DC_HPD5_INTERRUPT (1 << 17)
535# define DC_HPD5_RX_INTERRUPT (1 << 18)
536#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050
537# define LB_D6_VLINE_INTERRUPT (1 << 2)
538# define LB_D6_VBLANK_INTERRUPT (1 << 3)
539# define DC_HPD6_INTERRUPT (1 << 17)
540# define DC_HPD6_RX_INTERRUPT (1 << 18)
541
542/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
543#define GRPH_INT_STATUS 0x6858
544# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
545# define GRPH_PFLIP_INT_CLEAR (1 << 8)
546/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
547#define GRPH_INT_CONTROL 0x685c
548# define GRPH_PFLIP_INT_MASK (1 << 0)
549# define GRPH_PFLIP_INT_TYPE (1 << 8)
550
551#define DACA_AUTODETECT_INT_CONTROL 0x66c8
552#define DACB_AUTODETECT_INT_CONTROL 0x67c8
553
554#define DC_HPD1_INT_STATUS 0x601c
555#define DC_HPD2_INT_STATUS 0x6028
556#define DC_HPD3_INT_STATUS 0x6034
557#define DC_HPD4_INT_STATUS 0x6040
558#define DC_HPD5_INT_STATUS 0x604c
559#define DC_HPD6_INT_STATUS 0x6058
560# define DC_HPDx_INT_STATUS (1 << 0)
561# define DC_HPDx_SENSE (1 << 1)
562# define DC_HPDx_RX_INT_STATUS (1 << 8)
563
564#define DC_HPD1_INT_CONTROL 0x6020
565#define DC_HPD2_INT_CONTROL 0x602c
566#define DC_HPD3_INT_CONTROL 0x6038
567#define DC_HPD4_INT_CONTROL 0x6044
568#define DC_HPD5_INT_CONTROL 0x6050
569#define DC_HPD6_INT_CONTROL 0x605c
570# define DC_HPDx_INT_ACK (1 << 0)
571# define DC_HPDx_INT_POLARITY (1 << 8)
572# define DC_HPDx_INT_EN (1 << 16)
573# define DC_HPDx_RX_INT_ACK (1 << 20)
574# define DC_HPDx_RX_INT_EN (1 << 24)
575
576#define DC_HPD1_CONTROL 0x6024
577#define DC_HPD2_CONTROL 0x6030
578#define DC_HPD3_CONTROL 0x603c
579#define DC_HPD4_CONTROL 0x6048
580#define DC_HPD5_CONTROL 0x6054
581#define DC_HPD6_CONTROL 0x6060
582# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
583# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
584# define DC_HPDx_EN (1 << 28)
585
Alex Deucher9e46a482011-01-06 18:49:35 -0500586/* PCIE link stuff */
587#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
588#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
589# define LC_LINK_WIDTH_SHIFT 0
590# define LC_LINK_WIDTH_MASK 0x7
591# define LC_LINK_WIDTH_X0 0
592# define LC_LINK_WIDTH_X1 1
593# define LC_LINK_WIDTH_X2 2
594# define LC_LINK_WIDTH_X4 3
595# define LC_LINK_WIDTH_X8 4
596# define LC_LINK_WIDTH_X16 6
597# define LC_LINK_WIDTH_RD_SHIFT 4
598# define LC_LINK_WIDTH_RD_MASK 0x70
599# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
600# define LC_RECONFIG_NOW (1 << 8)
601# define LC_RENEGOTIATION_SUPPORT (1 << 9)
602# define LC_RENEGOTIATE_EN (1 << 10)
603# define LC_SHORT_RECONFIG_EN (1 << 11)
604# define LC_UPCONFIGURE_SUPPORT (1 << 12)
605# define LC_UPCONFIGURE_DIS (1 << 13)
606#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
607# define LC_GEN2_EN_STRAP (1 << 0)
608# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
609# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
610# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
611# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
612# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
613# define LC_CURRENT_DATA_RATE (1 << 11)
614# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
615# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
616# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
617# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
618#define MM_CFGREGS_CNTL 0x544c
619# define MM_WR_TO_CFG_EN (1 << 3)
620#define LINK_CNTL2 0x88 /* F0 */
621# define TARGET_LINK_SPEED_MASK (0xf << 0)
622# define SELECTABLE_DEEMPHASIS (1 << 6)
623
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400624/*
625 * PM4
626 */
627#define PACKET_TYPE0 0
628#define PACKET_TYPE1 1
629#define PACKET_TYPE2 2
630#define PACKET_TYPE3 3
631
632#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
633#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
634#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
635#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
636#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
637 (((reg) >> 2) & 0xFFFF) | \
638 ((n) & 0x3FFF) << 16)
639#define CP_PACKET2 0x80000000
640#define PACKET2_PAD_SHIFT 0
641#define PACKET2_PAD_MASK (0x3fffffff << 0)
642
643#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
644
645#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
646 (((op) & 0xFF) << 8) | \
647 ((n) & 0x3FFF) << 16)
648
649/* Packet 3 types */
650#define PACKET3_NOP 0x10
651#define PACKET3_SET_BASE 0x11
652#define PACKET3_CLEAR_STATE 0x12
Alex Deucher32171d22011-01-06 19:13:32 -0500653#define PACKET3_INDEX_BUFFER_SIZE 0x13
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400654#define PACKET3_DISPATCH_DIRECT 0x15
655#define PACKET3_DISPATCH_INDIRECT 0x16
656#define PACKET3_INDIRECT_BUFFER_END 0x17
Alex Deucher12920592011-02-02 12:37:40 -0500657#define PACKET3_MODE_CONTROL 0x18
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400658#define PACKET3_SET_PREDICATION 0x20
659#define PACKET3_REG_RMW 0x21
660#define PACKET3_COND_EXEC 0x22
661#define PACKET3_PRED_EXEC 0x23
662#define PACKET3_DRAW_INDIRECT 0x24
663#define PACKET3_DRAW_INDEX_INDIRECT 0x25
664#define PACKET3_INDEX_BASE 0x26
665#define PACKET3_DRAW_INDEX_2 0x27
666#define PACKET3_CONTEXT_CONTROL 0x28
667#define PACKET3_DRAW_INDEX_OFFSET 0x29
668#define PACKET3_INDEX_TYPE 0x2A
669#define PACKET3_DRAW_INDEX 0x2B
670#define PACKET3_DRAW_INDEX_AUTO 0x2D
671#define PACKET3_DRAW_INDEX_IMMD 0x2E
672#define PACKET3_NUM_INSTANCES 0x2F
673#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
674#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
675#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
676#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
677#define PACKET3_MEM_SEMAPHORE 0x39
678#define PACKET3_MPEG_INDEX 0x3A
679#define PACKET3_WAIT_REG_MEM 0x3C
680#define PACKET3_MEM_WRITE 0x3D
681#define PACKET3_INDIRECT_BUFFER 0x32
682#define PACKET3_SURFACE_SYNC 0x43
683# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
684# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
685# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
686# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
687# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
688# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
689# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
690# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
691# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
692# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
693# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
694# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
Alex Deucher32171d22011-01-06 19:13:32 -0500695# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400696# define PACKET3_FULL_CACHE_ENA (1 << 20)
697# define PACKET3_TC_ACTION_ENA (1 << 23)
698# define PACKET3_VC_ACTION_ENA (1 << 24)
699# define PACKET3_CB_ACTION_ENA (1 << 25)
700# define PACKET3_DB_ACTION_ENA (1 << 26)
701# define PACKET3_SH_ACTION_ENA (1 << 27)
Alex Deucher32171d22011-01-06 19:13:32 -0500702# define PACKET3_SX_ACTION_ENA (1 << 28)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400703#define PACKET3_ME_INITIALIZE 0x44
704#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
705#define PACKET3_COND_WRITE 0x45
706#define PACKET3_EVENT_WRITE 0x46
707#define PACKET3_EVENT_WRITE_EOP 0x47
708#define PACKET3_EVENT_WRITE_EOS 0x48
709#define PACKET3_PREAMBLE_CNTL 0x4A
Alex Deucher2281a372010-10-21 13:31:38 -0400710# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
711# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400712#define PACKET3_RB_OFFSET 0x4B
713#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
714#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
715#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
716#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
717#define PACKET3_ONE_REG_WRITE 0x57
718#define PACKET3_SET_CONFIG_REG 0x68
719#define PACKET3_SET_CONFIG_REG_START 0x00008000
720#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
721#define PACKET3_SET_CONTEXT_REG 0x69
722#define PACKET3_SET_CONTEXT_REG_START 0x00028000
723#define PACKET3_SET_CONTEXT_REG_END 0x00029000
724#define PACKET3_SET_ALU_CONST 0x6A
725/* alu const buffers only; no reg file */
726#define PACKET3_SET_BOOL_CONST 0x6B
727#define PACKET3_SET_BOOL_CONST_START 0x0003a500
728#define PACKET3_SET_BOOL_CONST_END 0x0003a518
729#define PACKET3_SET_LOOP_CONST 0x6C
730#define PACKET3_SET_LOOP_CONST_START 0x0003a200
731#define PACKET3_SET_LOOP_CONST_END 0x0003a500
732#define PACKET3_SET_RESOURCE 0x6D
733#define PACKET3_SET_RESOURCE_START 0x00030000
734#define PACKET3_SET_RESOURCE_END 0x00038000
735#define PACKET3_SET_SAMPLER 0x6E
736#define PACKET3_SET_SAMPLER_START 0x0003c000
737#define PACKET3_SET_SAMPLER_END 0x0003c600
738#define PACKET3_SET_CTL_CONST 0x6F
739#define PACKET3_SET_CTL_CONST_START 0x0003cff0
740#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
741#define PACKET3_SET_RESOURCE_OFFSET 0x70
742#define PACKET3_SET_ALU_CONST_VS 0x71
743#define PACKET3_SET_ALU_CONST_DI 0x72
744#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
745#define PACKET3_SET_RESOURCE_INDIRECT 0x74
746#define PACKET3_SET_APPEND_CNT 0x75
747
748#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
749#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
750#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
751#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
752#define SQ_TEX_VTX_INVALID_BUFFER 0x1
753#define SQ_TEX_VTX_VALID_TEXTURE 0x2
754#define SQ_TEX_VTX_VALID_BUFFER 0x3
755
756#define SQ_CONST_MEM_BASE 0x8df8
757
758#define SQ_ESGS_RING_SIZE 0x8c44
759#define SQ_GSVS_RING_SIZE 0x8c4c
760#define SQ_ESTMP_RING_SIZE 0x8c54
761#define SQ_GSTMP_RING_SIZE 0x8c5c
762#define SQ_VSTMP_RING_SIZE 0x8c64
763#define SQ_PSTMP_RING_SIZE 0x8c6c
764#define SQ_LSTMP_RING_SIZE 0x8e14
765#define SQ_HSTMP_RING_SIZE 0x8e1c
766#define VGT_TF_RING_SIZE 0x8988
767
768#define SQ_ESGS_RING_ITEMSIZE 0x28900
769#define SQ_GSVS_RING_ITEMSIZE 0x28904
770#define SQ_ESTMP_RING_ITEMSIZE 0x28908
771#define SQ_GSTMP_RING_ITEMSIZE 0x2890c
772#define SQ_VSTMP_RING_ITEMSIZE 0x28910
773#define SQ_PSTMP_RING_ITEMSIZE 0x28914
774#define SQ_LSTMP_RING_ITEMSIZE 0x28830
775#define SQ_HSTMP_RING_ITEMSIZE 0x28834
776
777#define SQ_GS_VERT_ITEMSIZE 0x2891c
778#define SQ_GS_VERT_ITEMSIZE_1 0x28920
779#define SQ_GS_VERT_ITEMSIZE_2 0x28924
780#define SQ_GS_VERT_ITEMSIZE_3 0x28928
781#define SQ_GSVS_RING_OFFSET_1 0x2892c
782#define SQ_GSVS_RING_OFFSET_2 0x28930
783#define SQ_GSVS_RING_OFFSET_3 0x28934
784
Alex Deucher60a4a3e2010-06-29 17:03:35 -0400785#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
786#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
787
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400788#define SQ_ALU_CONST_CACHE_PS_0 0x28940
789#define SQ_ALU_CONST_CACHE_PS_1 0x28944
790#define SQ_ALU_CONST_CACHE_PS_2 0x28948
791#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
792#define SQ_ALU_CONST_CACHE_PS_4 0x28950
793#define SQ_ALU_CONST_CACHE_PS_5 0x28954
794#define SQ_ALU_CONST_CACHE_PS_6 0x28958
795#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
796#define SQ_ALU_CONST_CACHE_PS_8 0x28960
797#define SQ_ALU_CONST_CACHE_PS_9 0x28964
798#define SQ_ALU_CONST_CACHE_PS_10 0x28968
799#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
800#define SQ_ALU_CONST_CACHE_PS_12 0x28970
801#define SQ_ALU_CONST_CACHE_PS_13 0x28974
802#define SQ_ALU_CONST_CACHE_PS_14 0x28978
803#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
804#define SQ_ALU_CONST_CACHE_VS_0 0x28980
805#define SQ_ALU_CONST_CACHE_VS_1 0x28984
806#define SQ_ALU_CONST_CACHE_VS_2 0x28988
807#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
808#define SQ_ALU_CONST_CACHE_VS_4 0x28990
809#define SQ_ALU_CONST_CACHE_VS_5 0x28994
810#define SQ_ALU_CONST_CACHE_VS_6 0x28998
811#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
812#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
813#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
814#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
815#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
816#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
817#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
818#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
819#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
820#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
821#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
822#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
823#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
824#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
825#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
826#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
827#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
828#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
829#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
830#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
831#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
832#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
833#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
834#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
835#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
836#define SQ_ALU_CONST_CACHE_HS_0 0x28f00
837#define SQ_ALU_CONST_CACHE_HS_1 0x28f04
838#define SQ_ALU_CONST_CACHE_HS_2 0x28f08
839#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
840#define SQ_ALU_CONST_CACHE_HS_4 0x28f10
841#define SQ_ALU_CONST_CACHE_HS_5 0x28f14
842#define SQ_ALU_CONST_CACHE_HS_6 0x28f18
843#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
844#define SQ_ALU_CONST_CACHE_HS_8 0x28f20
845#define SQ_ALU_CONST_CACHE_HS_9 0x28f24
846#define SQ_ALU_CONST_CACHE_HS_10 0x28f28
847#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
848#define SQ_ALU_CONST_CACHE_HS_12 0x28f30
849#define SQ_ALU_CONST_CACHE_HS_13 0x28f34
850#define SQ_ALU_CONST_CACHE_HS_14 0x28f38
851#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
852#define SQ_ALU_CONST_CACHE_LS_0 0x28f40
853#define SQ_ALU_CONST_CACHE_LS_1 0x28f44
854#define SQ_ALU_CONST_CACHE_LS_2 0x28f48
855#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
856#define SQ_ALU_CONST_CACHE_LS_4 0x28f50
857#define SQ_ALU_CONST_CACHE_LS_5 0x28f54
858#define SQ_ALU_CONST_CACHE_LS_6 0x28f58
859#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
860#define SQ_ALU_CONST_CACHE_LS_8 0x28f60
861#define SQ_ALU_CONST_CACHE_LS_9 0x28f64
862#define SQ_ALU_CONST_CACHE_LS_10 0x28f68
863#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
864#define SQ_ALU_CONST_CACHE_LS_12 0x28f70
865#define SQ_ALU_CONST_CACHE_LS_13 0x28f74
866#define SQ_ALU_CONST_CACHE_LS_14 0x28f78
867#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
868
Alex Deucherd7ccd8f2010-09-09 11:33:36 -0400869#define PA_SC_SCREEN_SCISSOR_TL 0x28030
870#define PA_SC_GENERIC_SCISSOR_TL 0x28240
871#define PA_SC_WINDOW_SCISSOR_TL 0x28204
872#define VGT_PRIMITIVE_TYPE 0x8958
873
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400874#define DB_DEPTH_CONTROL 0x28800
875#define DB_DEPTH_VIEW 0x28008
876#define DB_HTILE_DATA_BASE 0x28014
877#define DB_Z_INFO 0x28040
878# define Z_ARRAY_MODE(x) ((x) << 4)
879#define DB_STENCIL_INFO 0x28044
880#define DB_Z_READ_BASE 0x28048
881#define DB_STENCIL_READ_BASE 0x2804c
882#define DB_Z_WRITE_BASE 0x28050
883#define DB_STENCIL_WRITE_BASE 0x28054
884#define DB_DEPTH_SIZE 0x28058
885
886#define SQ_PGM_START_PS 0x28840
887#define SQ_PGM_START_VS 0x2885c
888#define SQ_PGM_START_GS 0x28874
889#define SQ_PGM_START_ES 0x2888c
890#define SQ_PGM_START_FS 0x288a4
891#define SQ_PGM_START_HS 0x288b8
892#define SQ_PGM_START_LS 0x288d0
893
894#define VGT_STRMOUT_CONFIG 0x28b94
895#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
896
897#define CB_TARGET_MASK 0x28238
898#define CB_SHADER_MASK 0x2823c
899
900#define GDS_ADDR_BASE 0x28720
901
902#define CB_IMMED0_BASE 0x28b9c
903#define CB_IMMED1_BASE 0x28ba0
904#define CB_IMMED2_BASE 0x28ba4
905#define CB_IMMED3_BASE 0x28ba8
906#define CB_IMMED4_BASE 0x28bac
907#define CB_IMMED5_BASE 0x28bb0
908#define CB_IMMED6_BASE 0x28bb4
909#define CB_IMMED7_BASE 0x28bb8
910#define CB_IMMED8_BASE 0x28bbc
911#define CB_IMMED9_BASE 0x28bc0
912#define CB_IMMED10_BASE 0x28bc4
913#define CB_IMMED11_BASE 0x28bc8
914
915/* all 12 CB blocks have these regs */
916#define CB_COLOR0_BASE 0x28c60
917#define CB_COLOR0_PITCH 0x28c64
918#define CB_COLOR0_SLICE 0x28c68
919#define CB_COLOR0_VIEW 0x28c6c
920#define CB_COLOR0_INFO 0x28c70
921# define CB_ARRAY_MODE(x) ((x) << 8)
922# define ARRAY_LINEAR_GENERAL 0
923# define ARRAY_LINEAR_ALIGNED 1
924# define ARRAY_1D_TILED_THIN1 2
925# define ARRAY_2D_TILED_THIN1 4
926#define CB_COLOR0_ATTRIB 0x28c74
927#define CB_COLOR0_DIM 0x28c78
928/* only CB0-7 blocks have these regs */
929#define CB_COLOR0_CMASK 0x28c7c
930#define CB_COLOR0_CMASK_SLICE 0x28c80
931#define CB_COLOR0_FMASK 0x28c84
932#define CB_COLOR0_FMASK_SLICE 0x28c88
933#define CB_COLOR0_CLEAR_WORD0 0x28c8c
934#define CB_COLOR0_CLEAR_WORD1 0x28c90
935#define CB_COLOR0_CLEAR_WORD2 0x28c94
936#define CB_COLOR0_CLEAR_WORD3 0x28c98
937
938#define CB_COLOR1_BASE 0x28c9c
939#define CB_COLOR2_BASE 0x28cd8
940#define CB_COLOR3_BASE 0x28d14
941#define CB_COLOR4_BASE 0x28d50
942#define CB_COLOR5_BASE 0x28d8c
943#define CB_COLOR6_BASE 0x28dc8
944#define CB_COLOR7_BASE 0x28e04
945#define CB_COLOR8_BASE 0x28e40
946#define CB_COLOR9_BASE 0x28e5c
947#define CB_COLOR10_BASE 0x28e78
948#define CB_COLOR11_BASE 0x28e94
949
950#define CB_COLOR1_PITCH 0x28ca0
951#define CB_COLOR2_PITCH 0x28cdc
952#define CB_COLOR3_PITCH 0x28d18
953#define CB_COLOR4_PITCH 0x28d54
954#define CB_COLOR5_PITCH 0x28d90
955#define CB_COLOR6_PITCH 0x28dcc
956#define CB_COLOR7_PITCH 0x28e08
957#define CB_COLOR8_PITCH 0x28e44
958#define CB_COLOR9_PITCH 0x28e60
959#define CB_COLOR10_PITCH 0x28e7c
960#define CB_COLOR11_PITCH 0x28e98
961
962#define CB_COLOR1_SLICE 0x28ca4
963#define CB_COLOR2_SLICE 0x28ce0
964#define CB_COLOR3_SLICE 0x28d1c
965#define CB_COLOR4_SLICE 0x28d58
966#define CB_COLOR5_SLICE 0x28d94
967#define CB_COLOR6_SLICE 0x28dd0
968#define CB_COLOR7_SLICE 0x28e0c
969#define CB_COLOR8_SLICE 0x28e48
970#define CB_COLOR9_SLICE 0x28e64
971#define CB_COLOR10_SLICE 0x28e80
972#define CB_COLOR11_SLICE 0x28e9c
973
974#define CB_COLOR1_VIEW 0x28ca8
975#define CB_COLOR2_VIEW 0x28ce4
976#define CB_COLOR3_VIEW 0x28d20
977#define CB_COLOR4_VIEW 0x28d5c
978#define CB_COLOR5_VIEW 0x28d98
979#define CB_COLOR6_VIEW 0x28dd4
980#define CB_COLOR7_VIEW 0x28e10
981#define CB_COLOR8_VIEW 0x28e4c
982#define CB_COLOR9_VIEW 0x28e68
983#define CB_COLOR10_VIEW 0x28e84
984#define CB_COLOR11_VIEW 0x28ea0
985
986#define CB_COLOR1_INFO 0x28cac
987#define CB_COLOR2_INFO 0x28ce8
988#define CB_COLOR3_INFO 0x28d24
989#define CB_COLOR4_INFO 0x28d60
990#define CB_COLOR5_INFO 0x28d9c
991#define CB_COLOR6_INFO 0x28dd8
992#define CB_COLOR7_INFO 0x28e14
993#define CB_COLOR8_INFO 0x28e50
994#define CB_COLOR9_INFO 0x28e6c
995#define CB_COLOR10_INFO 0x28e88
996#define CB_COLOR11_INFO 0x28ea4
997
998#define CB_COLOR1_ATTRIB 0x28cb0
999#define CB_COLOR2_ATTRIB 0x28cec
1000#define CB_COLOR3_ATTRIB 0x28d28
1001#define CB_COLOR4_ATTRIB 0x28d64
1002#define CB_COLOR5_ATTRIB 0x28da0
1003#define CB_COLOR6_ATTRIB 0x28ddc
1004#define CB_COLOR7_ATTRIB 0x28e18
1005#define CB_COLOR8_ATTRIB 0x28e54
1006#define CB_COLOR9_ATTRIB 0x28e70
1007#define CB_COLOR10_ATTRIB 0x28e8c
1008#define CB_COLOR11_ATTRIB 0x28ea8
1009
1010#define CB_COLOR1_DIM 0x28cb4
1011#define CB_COLOR2_DIM 0x28cf0
1012#define CB_COLOR3_DIM 0x28d2c
1013#define CB_COLOR4_DIM 0x28d68
1014#define CB_COLOR5_DIM 0x28da4
1015#define CB_COLOR6_DIM 0x28de0
1016#define CB_COLOR7_DIM 0x28e1c
1017#define CB_COLOR8_DIM 0x28e58
1018#define CB_COLOR9_DIM 0x28e74
1019#define CB_COLOR10_DIM 0x28e90
1020#define CB_COLOR11_DIM 0x28eac
1021
1022#define CB_COLOR1_CMASK 0x28cb8
1023#define CB_COLOR2_CMASK 0x28cf4
1024#define CB_COLOR3_CMASK 0x28d30
1025#define CB_COLOR4_CMASK 0x28d6c
1026#define CB_COLOR5_CMASK 0x28da8
1027#define CB_COLOR6_CMASK 0x28de4
1028#define CB_COLOR7_CMASK 0x28e20
1029
1030#define CB_COLOR1_CMASK_SLICE 0x28cbc
1031#define CB_COLOR2_CMASK_SLICE 0x28cf8
1032#define CB_COLOR3_CMASK_SLICE 0x28d34
1033#define CB_COLOR4_CMASK_SLICE 0x28d70
1034#define CB_COLOR5_CMASK_SLICE 0x28dac
1035#define CB_COLOR6_CMASK_SLICE 0x28de8
1036#define CB_COLOR7_CMASK_SLICE 0x28e24
1037
1038#define CB_COLOR1_FMASK 0x28cc0
1039#define CB_COLOR2_FMASK 0x28cfc
1040#define CB_COLOR3_FMASK 0x28d38
1041#define CB_COLOR4_FMASK 0x28d74
1042#define CB_COLOR5_FMASK 0x28db0
1043#define CB_COLOR6_FMASK 0x28dec
1044#define CB_COLOR7_FMASK 0x28e28
1045
1046#define CB_COLOR1_FMASK_SLICE 0x28cc4
1047#define CB_COLOR2_FMASK_SLICE 0x28d00
1048#define CB_COLOR3_FMASK_SLICE 0x28d3c
1049#define CB_COLOR4_FMASK_SLICE 0x28d78
1050#define CB_COLOR5_FMASK_SLICE 0x28db4
1051#define CB_COLOR6_FMASK_SLICE 0x28df0
1052#define CB_COLOR7_FMASK_SLICE 0x28e2c
1053
1054#define CB_COLOR1_CLEAR_WORD0 0x28cc8
1055#define CB_COLOR2_CLEAR_WORD0 0x28d04
1056#define CB_COLOR3_CLEAR_WORD0 0x28d40
1057#define CB_COLOR4_CLEAR_WORD0 0x28d7c
1058#define CB_COLOR5_CLEAR_WORD0 0x28db8
1059#define CB_COLOR6_CLEAR_WORD0 0x28df4
1060#define CB_COLOR7_CLEAR_WORD0 0x28e30
1061
1062#define CB_COLOR1_CLEAR_WORD1 0x28ccc
1063#define CB_COLOR2_CLEAR_WORD1 0x28d08
1064#define CB_COLOR3_CLEAR_WORD1 0x28d44
1065#define CB_COLOR4_CLEAR_WORD1 0x28d80
1066#define CB_COLOR5_CLEAR_WORD1 0x28dbc
1067#define CB_COLOR6_CLEAR_WORD1 0x28df8
1068#define CB_COLOR7_CLEAR_WORD1 0x28e34
1069
1070#define CB_COLOR1_CLEAR_WORD2 0x28cd0
1071#define CB_COLOR2_CLEAR_WORD2 0x28d0c
1072#define CB_COLOR3_CLEAR_WORD2 0x28d48
1073#define CB_COLOR4_CLEAR_WORD2 0x28d84
1074#define CB_COLOR5_CLEAR_WORD2 0x28dc0
1075#define CB_COLOR6_CLEAR_WORD2 0x28dfc
1076#define CB_COLOR7_CLEAR_WORD2 0x28e38
1077
1078#define CB_COLOR1_CLEAR_WORD3 0x28cd4
1079#define CB_COLOR2_CLEAR_WORD3 0x28d10
1080#define CB_COLOR3_CLEAR_WORD3 0x28d4c
1081#define CB_COLOR4_CLEAR_WORD3 0x28d88
1082#define CB_COLOR5_CLEAR_WORD3 0x28dc4
1083#define CB_COLOR6_CLEAR_WORD3 0x28e00
1084#define CB_COLOR7_CLEAR_WORD3 0x28e3c
1085
1086#define SQ_TEX_RESOURCE_WORD0_0 0x30000
1087#define SQ_TEX_RESOURCE_WORD1_0 0x30004
1088# define TEX_ARRAY_MODE(x) ((x) << 28)
1089#define SQ_TEX_RESOURCE_WORD2_0 0x30008
1090#define SQ_TEX_RESOURCE_WORD3_0 0x3000C
1091#define SQ_TEX_RESOURCE_WORD4_0 0x30010
1092#define SQ_TEX_RESOURCE_WORD5_0 0x30014
1093#define SQ_TEX_RESOURCE_WORD6_0 0x30018
1094#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
1095
1096
Alex Deucher0fcdb612010-03-24 13:20:41 -04001097#endif