Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Common boot and setup code. |
| 4 | * |
| 5 | * Copyright (C) 2001 PPC64 Team, IBM Corp |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * as published by the Free Software Foundation; either version |
| 10 | * 2 of the License, or (at your option) any later version. |
| 11 | */ |
| 12 | |
Benjamin Herrenschmidt | 7191b61 | 2013-07-25 12:12:32 +1000 | [diff] [blame] | 13 | #define DEBUG |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 14 | |
Paul Gortmaker | 4b16f8e | 2011-07-22 18:24:23 -0400 | [diff] [blame] | 15 | #include <linux/export.h> |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 16 | #include <linux/string.h> |
| 17 | #include <linux/sched.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/reboot.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/initrd.h> |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 23 | #include <linux/seq_file.h> |
| 24 | #include <linux/ioport.h> |
| 25 | #include <linux/console.h> |
| 26 | #include <linux/utsname.h> |
| 27 | #include <linux/tty.h> |
| 28 | #include <linux/root_dev.h> |
| 29 | #include <linux/notifier.h> |
| 30 | #include <linux/cpu.h> |
| 31 | #include <linux/unistd.h> |
| 32 | #include <linux/serial.h> |
| 33 | #include <linux/serial_8250.h> |
Anton Blanchard | 7a0268f | 2006-01-11 13:16:44 +1100 | [diff] [blame] | 34 | #include <linux/bootmem.h> |
Benjamin Herrenschmidt | 12d04ee | 2006-11-11 17:25:02 +1100 | [diff] [blame] | 35 | #include <linux/pci.h> |
Benjamin Herrenschmidt | 945feb1 | 2008-04-17 14:35:01 +1000 | [diff] [blame] | 36 | #include <linux/lockdep.h> |
Yinghai Lu | 95f72d1 | 2010-07-12 14:36:09 +1000 | [diff] [blame] | 37 | #include <linux/memblock.h> |
Becky Bruce | a614688 | 2011-10-10 10:50:43 +0000 | [diff] [blame] | 38 | #include <linux/hugetlb.h> |
Anton Blanchard | a5d8625 | 2014-06-04 17:50:47 +1000 | [diff] [blame] | 39 | #include <linux/memory.h> |
Becky Bruce | a614688 | 2011-10-10 10:50:43 +0000 | [diff] [blame] | 40 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 41 | #include <asm/io.h> |
Michael Ellerman | 0cc4746 | 2005-12-04 18:39:37 +1100 | [diff] [blame] | 42 | #include <asm/kdump.h> |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 43 | #include <asm/prom.h> |
| 44 | #include <asm/processor.h> |
| 45 | #include <asm/pgtable.h> |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 46 | #include <asm/smp.h> |
| 47 | #include <asm/elf.h> |
| 48 | #include <asm/machdep.h> |
| 49 | #include <asm/paca.h> |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 50 | #include <asm/time.h> |
| 51 | #include <asm/cputable.h> |
| 52 | #include <asm/sections.h> |
| 53 | #include <asm/btext.h> |
| 54 | #include <asm/nvram.h> |
| 55 | #include <asm/setup.h> |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 56 | #include <asm/rtas.h> |
| 57 | #include <asm/iommu.h> |
| 58 | #include <asm/serial.h> |
| 59 | #include <asm/cache.h> |
| 60 | #include <asm/page.h> |
| 61 | #include <asm/mmu.h> |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 62 | #include <asm/firmware.h> |
Paul Mackerras | f78541d | 2005-10-28 22:53:37 +1000 | [diff] [blame] | 63 | #include <asm/xmon.h> |
David Gibson | dcad47f | 2005-11-07 09:49:43 +1100 | [diff] [blame] | 64 | #include <asm/udbg.h> |
Michael Ellerman | 593e537 | 2005-11-12 00:06:06 +1100 | [diff] [blame] | 65 | #include <asm/kexec.h> |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 66 | #include <asm/mmu_context.h> |
Kumar Gala | d36b4c4 | 2011-04-06 00:18:48 -0500 | [diff] [blame] | 67 | #include <asm/code-patching.h> |
Paul Mackerras | aa04b4c | 2011-06-29 00:25:44 +0000 | [diff] [blame] | 68 | #include <asm/kvm_ppc.h> |
Becky Bruce | a614688 | 2011-10-10 10:50:43 +0000 | [diff] [blame] | 69 | #include <asm/hugetlb.h> |
Laurentiu TUDOR | 4e21b94 | 2013-07-03 17:13:15 +0300 | [diff] [blame] | 70 | #include <asm/epapr_hcalls.h> |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 71 | |
| 72 | #ifdef DEBUG |
| 73 | #define DBG(fmt...) udbg_printf(fmt) |
| 74 | #else |
| 75 | #define DBG(fmt...) |
| 76 | #endif |
| 77 | |
Chen Gang | 8246aca | 2013-03-20 14:30:12 +0800 | [diff] [blame] | 78 | int spinning_secondaries; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 79 | u64 ppc64_pft_size; |
| 80 | |
Olof Johansson | dabcafd | 2005-12-08 19:40:17 -0600 | [diff] [blame] | 81 | /* Pick defaults since we might want to patch instructions |
| 82 | * before we've read this from the device tree. |
| 83 | */ |
| 84 | struct ppc64_caches ppc64_caches = { |
Olof Johansson | 5a2fe38 | 2006-09-06 14:34:41 -0500 | [diff] [blame] | 85 | .dline_size = 0x40, |
| 86 | .log_dline_size = 6, |
| 87 | .iline_size = 0x40, |
| 88 | .log_iline_size = 6 |
Olof Johansson | dabcafd | 2005-12-08 19:40:17 -0600 | [diff] [blame] | 89 | }; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 90 | EXPORT_SYMBOL_GPL(ppc64_caches); |
| 91 | |
| 92 | /* |
| 93 | * These are used in binfmt_elf.c to put aux entries on the stack |
| 94 | * for each elf executable being started. |
| 95 | */ |
| 96 | int dcache_bsize; |
| 97 | int icache_bsize; |
| 98 | int ucache_bsize; |
| 99 | |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 100 | #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) |
| 101 | static void setup_tlb_core_data(void) |
| 102 | { |
| 103 | int cpu; |
| 104 | |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 105 | BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); |
| 106 | |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 107 | for_each_possible_cpu(cpu) { |
| 108 | int first = cpu_first_thread_sibling(cpu); |
| 109 | |
| 110 | paca[cpu].tcd_ptr = &paca[first].tcd; |
| 111 | |
| 112 | /* |
| 113 | * If we have threads, we need either tlbsrx. |
| 114 | * or e6500 tablewalk mode, or else TLB handlers |
| 115 | * will be racy and could produce duplicate entries. |
| 116 | */ |
| 117 | if (smt_enabled_at_boot >= 2 && |
| 118 | !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && |
| 119 | book3e_htw_mode != PPC_HTW_E6500) { |
| 120 | /* Should we panic instead? */ |
| 121 | WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", |
| 122 | __func__); |
| 123 | } |
| 124 | } |
| 125 | } |
| 126 | #else |
| 127 | static void setup_tlb_core_data(void) |
| 128 | { |
| 129 | } |
| 130 | #endif |
| 131 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 132 | #ifdef CONFIG_SMP |
| 133 | |
Nathan Fontenot | 954e6da | 2010-08-05 07:42:11 +0000 | [diff] [blame] | 134 | static char *smt_enabled_cmdline; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 135 | |
| 136 | /* Look for ibm,smt-enabled OF option */ |
| 137 | static void check_smt_enabled(void) |
| 138 | { |
| 139 | struct device_node *dn; |
Jeremy Kerr | a7f67bd | 2006-07-12 15:35:54 +1000 | [diff] [blame] | 140 | const char *smt_option; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 141 | |
Nathan Fontenot | 954e6da | 2010-08-05 07:42:11 +0000 | [diff] [blame] | 142 | /* Default to enabling all threads */ |
| 143 | smt_enabled_at_boot = threads_per_core; |
| 144 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 145 | /* Allow the command line to overrule the OF option */ |
Nathan Fontenot | 954e6da | 2010-08-05 07:42:11 +0000 | [diff] [blame] | 146 | if (smt_enabled_cmdline) { |
| 147 | if (!strcmp(smt_enabled_cmdline, "on")) |
| 148 | smt_enabled_at_boot = threads_per_core; |
| 149 | else if (!strcmp(smt_enabled_cmdline, "off")) |
| 150 | smt_enabled_at_boot = 0; |
| 151 | else { |
Daniel Walter | 1618bd5 | 2014-08-08 14:24:01 -0700 | [diff] [blame] | 152 | int smt; |
Nathan Fontenot | 954e6da | 2010-08-05 07:42:11 +0000 | [diff] [blame] | 153 | int rc; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 154 | |
Daniel Walter | 1618bd5 | 2014-08-08 14:24:01 -0700 | [diff] [blame] | 155 | rc = kstrtoint(smt_enabled_cmdline, 10, &smt); |
Nathan Fontenot | 954e6da | 2010-08-05 07:42:11 +0000 | [diff] [blame] | 156 | if (!rc) |
| 157 | smt_enabled_at_boot = |
Daniel Walter | 1618bd5 | 2014-08-08 14:24:01 -0700 | [diff] [blame] | 158 | min(threads_per_core, smt); |
Nathan Fontenot | 954e6da | 2010-08-05 07:42:11 +0000 | [diff] [blame] | 159 | } |
| 160 | } else { |
| 161 | dn = of_find_node_by_path("/options"); |
| 162 | if (dn) { |
| 163 | smt_option = of_get_property(dn, "ibm,smt-enabled", |
| 164 | NULL); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 165 | |
Nathan Fontenot | 954e6da | 2010-08-05 07:42:11 +0000 | [diff] [blame] | 166 | if (smt_option) { |
| 167 | if (!strcmp(smt_option, "on")) |
| 168 | smt_enabled_at_boot = threads_per_core; |
| 169 | else if (!strcmp(smt_option, "off")) |
| 170 | smt_enabled_at_boot = 0; |
| 171 | } |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 172 | |
Nathan Fontenot | 954e6da | 2010-08-05 07:42:11 +0000 | [diff] [blame] | 173 | of_node_put(dn); |
| 174 | } |
| 175 | } |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 176 | } |
| 177 | |
| 178 | /* Look for smt-enabled= cmdline option */ |
| 179 | static int __init early_smt_enabled(char *p) |
| 180 | { |
Nathan Fontenot | 954e6da | 2010-08-05 07:42:11 +0000 | [diff] [blame] | 181 | smt_enabled_cmdline = p; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 182 | return 0; |
| 183 | } |
| 184 | early_param("smt-enabled", early_smt_enabled); |
| 185 | |
Paul Mackerras | 5ad5707 | 2005-11-05 10:33:55 +1100 | [diff] [blame] | 186 | #else |
| 187 | #define check_smt_enabled() |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 188 | #endif /* CONFIG_SMP */ |
| 189 | |
Michael Ellerman | 25e1381 | 2013-02-12 14:44:50 +0000 | [diff] [blame] | 190 | /** Fix up paca fields required for the boot cpu */ |
| 191 | static void fixup_boot_paca(void) |
| 192 | { |
| 193 | /* The boot cpu is started */ |
| 194 | get_paca()->cpu_start = 1; |
| 195 | /* Allow percpu accesses to work until we setup percpu data */ |
| 196 | get_paca()->data_offset = 0; |
| 197 | } |
| 198 | |
Benjamin Herrenschmidt | 8f619b54 | 2014-03-28 13:36:30 +1100 | [diff] [blame] | 199 | static void cpu_ready_for_interrupts(void) |
| 200 | { |
| 201 | /* Set IR and DR in PACA MSR */ |
| 202 | get_paca()->kernel_msr = MSR_KERNEL; |
| 203 | |
Michael Ellerman | 633440f | 2014-07-17 15:29:45 +1000 | [diff] [blame] | 204 | /* |
| 205 | * Enable AIL if supported, and we are in hypervisor mode. If we are |
| 206 | * not in hypervisor mode, we enable relocation-on interrupts later |
| 207 | * in pSeries_setup_arch() using the H_SET_MODE hcall. |
| 208 | */ |
Paul Mackerras | 18aa0da | 2014-04-11 16:43:35 +1000 | [diff] [blame] | 209 | if (cpu_has_feature(CPU_FTR_HVMODE) && |
| 210 | cpu_has_feature(CPU_FTR_ARCH_207S)) { |
Benjamin Herrenschmidt | 8f619b54 | 2014-03-28 13:36:30 +1100 | [diff] [blame] | 211 | unsigned long lpcr = mfspr(SPRN_LPCR); |
| 212 | mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); |
| 213 | } |
| 214 | } |
| 215 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 216 | /* |
| 217 | * Early initialization entry point. This is called by head.S |
| 218 | * with MMU translation disabled. We rely on the "feature" of |
| 219 | * the CPU that ignores the top 2 bits of the address in real |
| 220 | * mode so we can access kernel globals normally provided we |
| 221 | * only toy with things in the RMO region. From here, we do |
Yinghai Lu | 95f72d1 | 2010-07-12 14:36:09 +1000 | [diff] [blame] | 222 | * some early parsing of the device-tree to setup out MEMBLOCK |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 223 | * data structures, and allocate & initialize the hash table |
| 224 | * and segment tables so we can start running with translation |
| 225 | * enabled. |
| 226 | * |
| 227 | * It is this function which will call the probe() callback of |
| 228 | * the various platform types and copy the matching one to the |
| 229 | * global ppc_md structure. Your platform can eventually do |
| 230 | * some very early initializations from the probe() routine, but |
| 231 | * this is not recommended, be very careful as, for example, the |
| 232 | * device-tree is not accessible via normal means at this point. |
| 233 | */ |
| 234 | |
| 235 | void __init early_setup(unsigned long dt_ptr) |
| 236 | { |
Geoff Levand | 6a7e406 | 2013-02-13 17:03:16 +0000 | [diff] [blame] | 237 | static __initdata struct paca_struct boot_paca; |
| 238 | |
Benjamin Herrenschmidt | 24d9649 | 2008-05-07 10:00:56 +1000 | [diff] [blame] | 239 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
| 240 | |
Benjamin Herrenschmidt | 42c4aaa | 2006-10-24 16:42:40 +1000 | [diff] [blame] | 241 | /* Identify CPU type */ |
Paul Mackerras | 974a76f | 2006-11-10 20:38:53 +1100 | [diff] [blame] | 242 | identify_cpu(0, mfspr(SPRN_PVR)); |
Benjamin Herrenschmidt | 42c4aaa | 2006-10-24 16:42:40 +1000 | [diff] [blame] | 243 | |
Michael Ellerman | 33dbcf7 | 2006-06-28 13:18:53 +1000 | [diff] [blame] | 244 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
Michael Ellerman | 1426d5a | 2010-01-28 13:23:22 +0000 | [diff] [blame] | 245 | initialise_paca(&boot_paca, 0); |
| 246 | setup_paca(&boot_paca); |
Michael Ellerman | 25e1381 | 2013-02-12 14:44:50 +0000 | [diff] [blame] | 247 | fixup_boot_paca(); |
Michael Ellerman | 33dbcf7 | 2006-06-28 13:18:53 +1000 | [diff] [blame] | 248 | |
Benjamin Herrenschmidt | 945feb1 | 2008-04-17 14:35:01 +1000 | [diff] [blame] | 249 | /* Initialize lockdep early or else spinlocks will blow */ |
| 250 | lockdep_init(); |
| 251 | |
Benjamin Herrenschmidt | 24d9649 | 2008-05-07 10:00:56 +1000 | [diff] [blame] | 252 | /* -------- printk is now safe to use ------- */ |
| 253 | |
Benjamin Herrenschmidt | f2fd251 | 2008-05-07 10:25:34 +1000 | [diff] [blame] | 254 | /* Enable early debugging if any specified (see udbg.h) */ |
| 255 | udbg_early_init(); |
| 256 | |
Benjamin Herrenschmidt | e822250 | 2006-03-28 23:15:54 +1100 | [diff] [blame] | 257 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 258 | |
| 259 | /* |
Linas Vepstas | 3c607ce | 2007-09-07 03:47:29 +1000 | [diff] [blame] | 260 | * Do early initialization using the flattened device |
| 261 | * tree, such as retrieving the physical memory map or |
| 262 | * calculating/retrieving the hash table size. |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 263 | */ |
| 264 | early_init_devtree(__va(dt_ptr)); |
| 265 | |
Laurentiu TUDOR | 4e21b94 | 2013-07-03 17:13:15 +0300 | [diff] [blame] | 266 | epapr_paravirt_early_init(); |
| 267 | |
Anton Blanchard | 4df2046 | 2006-03-25 17:25:17 +1100 | [diff] [blame] | 268 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
Michael Ellerman | 1426d5a | 2010-01-28 13:23:22 +0000 | [diff] [blame] | 269 | setup_paca(&paca[boot_cpuid]); |
Michael Ellerman | 25e1381 | 2013-02-12 14:44:50 +0000 | [diff] [blame] | 270 | fixup_boot_paca(); |
Anton Blanchard | 4df2046 | 2006-03-25 17:25:17 +1100 | [diff] [blame] | 271 | |
Benjamin Herrenschmidt | e822250 | 2006-03-28 23:15:54 +1100 | [diff] [blame] | 272 | /* Probe the machine type */ |
| 273 | probe_machine(); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 274 | |
Michael Ellerman | 4731041 | 2006-05-17 18:00:49 +1000 | [diff] [blame] | 275 | setup_kdump_trampoline(); |
Michael Ellerman | 0cc4746 | 2005-12-04 18:39:37 +1100 | [diff] [blame] | 276 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 277 | DBG("Found, Initializing memory management...\n"); |
| 278 | |
Benjamin Herrenschmidt | 757c74d | 2009-03-19 19:34:16 +0000 | [diff] [blame] | 279 | /* Initialize the hash table or TLB handling */ |
| 280 | early_init_mmu(); |
Benjamin Herrenschmidt | 3c726f8 | 2005-11-07 11:06:55 +1100 | [diff] [blame] | 281 | |
Benjamin Herrenschmidt | a944a9c | 2014-03-28 13:36:29 +1100 | [diff] [blame] | 282 | /* |
| 283 | * At this point, we can let interrupts switch to virtual mode |
| 284 | * (the MMU has been setup), so adjust the MSR in the PACA to |
Benjamin Herrenschmidt | 8f619b54 | 2014-03-28 13:36:30 +1100 | [diff] [blame] | 285 | * have IR and DR set and enable AIL if it exists |
Benjamin Herrenschmidt | a944a9c | 2014-03-28 13:36:29 +1100 | [diff] [blame] | 286 | */ |
Benjamin Herrenschmidt | 8f619b54 | 2014-03-28 13:36:30 +1100 | [diff] [blame] | 287 | cpu_ready_for_interrupts(); |
Benjamin Herrenschmidt | a944a9c | 2014-03-28 13:36:29 +1100 | [diff] [blame] | 288 | |
| 289 | /* Reserve large chunks of memory for use by CMA for KVM */ |
Aneesh Kumar K.V | fa61a4e | 2013-07-02 11:15:16 +0530 | [diff] [blame] | 290 | kvm_cma_reserve(); |
| 291 | |
Becky Bruce | a614688 | 2011-10-10 10:50:43 +0000 | [diff] [blame] | 292 | /* |
| 293 | * Reserve any gigantic pages requested on the command line. |
| 294 | * memblock needs to have been initialized by the time this is |
| 295 | * called since this will reserve memory. |
| 296 | */ |
| 297 | reserve_hugetlb_gpages(); |
| 298 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 299 | DBG(" <- early_setup()\n"); |
Benjamin Herrenschmidt | 7191b61 | 2013-07-25 12:12:32 +1000 | [diff] [blame] | 300 | |
| 301 | #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX |
| 302 | /* |
| 303 | * This needs to be done *last* (after the above DBG() even) |
| 304 | * |
| 305 | * Right after we return from this function, we turn on the MMU |
| 306 | * which means the real-mode access trick that btext does will |
| 307 | * no longer work, it needs to switch to using a real MMU |
| 308 | * mapping. This call will ensure that it does |
| 309 | */ |
| 310 | btext_map(); |
| 311 | #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 312 | } |
| 313 | |
Paul Mackerras | 799d604 | 2005-11-10 13:37:51 +1100 | [diff] [blame] | 314 | #ifdef CONFIG_SMP |
| 315 | void early_setup_secondary(void) |
| 316 | { |
Paul Mackerras | d04c56f | 2006-10-04 16:47:49 +1000 | [diff] [blame] | 317 | /* Mark interrupts enabled in PACA */ |
Benjamin Herrenschmidt | 757c74d | 2009-03-19 19:34:16 +0000 | [diff] [blame] | 318 | get_paca()->soft_enabled = 0; |
Paul Mackerras | 799d604 | 2005-11-10 13:37:51 +1100 | [diff] [blame] | 319 | |
Benjamin Herrenschmidt | 757c74d | 2009-03-19 19:34:16 +0000 | [diff] [blame] | 320 | /* Initialize the hash table or TLB handling */ |
| 321 | early_init_mmu_secondary(); |
Benjamin Herrenschmidt | a944a9c | 2014-03-28 13:36:29 +1100 | [diff] [blame] | 322 | |
| 323 | /* |
| 324 | * At this point, we can let interrupts switch to virtual mode |
| 325 | * (the MMU has been setup), so adjust the MSR in the PACA to |
| 326 | * have IR and DR set. |
| 327 | */ |
Benjamin Herrenschmidt | 8f619b54 | 2014-03-28 13:36:30 +1100 | [diff] [blame] | 328 | cpu_ready_for_interrupts(); |
Paul Mackerras | 799d604 | 2005-11-10 13:37:51 +1100 | [diff] [blame] | 329 | } |
| 330 | |
| 331 | #endif /* CONFIG_SMP */ |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 332 | |
Michael Ellerman | b8f5102 | 2005-11-04 12:09:42 +1100 | [diff] [blame] | 333 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
| 334 | void smp_release_cpus(void) |
| 335 | { |
Michael Ellerman | 758438a | 2005-12-05 15:49:00 -0600 | [diff] [blame] | 336 | unsigned long *ptr; |
Benjamin Herrenschmidt | 9d07bc8 | 2011-03-16 14:54:35 +1100 | [diff] [blame] | 337 | int i; |
Michael Ellerman | b8f5102 | 2005-11-04 12:09:42 +1100 | [diff] [blame] | 338 | |
| 339 | DBG(" -> smp_release_cpus()\n"); |
| 340 | |
| 341 | /* All secondary cpus are spinning on a common spinloop, release them |
| 342 | * all now so they can start to spin on their individual paca |
| 343 | * spinloops. For non SMP kernels, the secondary cpus never get out |
| 344 | * of the common spinloop. |
Paul Mackerras | 1f6a93e | 2008-08-30 11:40:24 +1000 | [diff] [blame] | 345 | */ |
Michael Ellerman | b8f5102 | 2005-11-04 12:09:42 +1100 | [diff] [blame] | 346 | |
Michael Ellerman | 758438a | 2005-12-05 15:49:00 -0600 | [diff] [blame] | 347 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
| 348 | - PHYSICAL_START); |
Anton Blanchard | 2751b62 | 2014-03-11 11:54:06 +1100 | [diff] [blame] | 349 | *ptr = ppc_function_entry(generic_secondary_smp_init); |
Benjamin Herrenschmidt | 9d07bc8 | 2011-03-16 14:54:35 +1100 | [diff] [blame] | 350 | |
| 351 | /* And wait a bit for them to catch up */ |
| 352 | for (i = 0; i < 100000; i++) { |
| 353 | mb(); |
| 354 | HMT_low(); |
Matt Evans | 7ac87ab | 2011-05-25 18:09:12 +0000 | [diff] [blame] | 355 | if (spinning_secondaries == 0) |
Benjamin Herrenschmidt | 9d07bc8 | 2011-03-16 14:54:35 +1100 | [diff] [blame] | 356 | break; |
| 357 | udelay(1); |
| 358 | } |
Matt Evans | 7ac87ab | 2011-05-25 18:09:12 +0000 | [diff] [blame] | 359 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
Michael Ellerman | b8f5102 | 2005-11-04 12:09:42 +1100 | [diff] [blame] | 360 | |
| 361 | DBG(" <- smp_release_cpus()\n"); |
| 362 | } |
| 363 | #endif /* CONFIG_SMP || CONFIG_KEXEC */ |
| 364 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 365 | /* |
Paul Mackerras | 799d604 | 2005-11-10 13:37:51 +1100 | [diff] [blame] | 366 | * Initialize some remaining members of the ppc64_caches and systemcfg |
| 367 | * structures |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 368 | * (at least until we get rid of them completely). This is mostly some |
| 369 | * cache informations about the CPU that will be used by cache flush |
| 370 | * routines and/or provided to userland |
| 371 | */ |
| 372 | static void __init initialize_cache_info(void) |
| 373 | { |
| 374 | struct device_node *np; |
| 375 | unsigned long num_cpus = 0; |
| 376 | |
| 377 | DBG(" -> initialize_cache_info()\n"); |
| 378 | |
Anton Blanchard | 94db7c5 | 2011-08-10 20:44:22 +0000 | [diff] [blame] | 379 | for_each_node_by_type(np, "cpu") { |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 380 | num_cpus += 1; |
| 381 | |
Anton Blanchard | dfbe93a | 2011-08-10 20:44:23 +0000 | [diff] [blame] | 382 | /* |
| 383 | * We're assuming *all* of the CPUs have the same |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 384 | * d-cache and i-cache sizes... -Peter |
| 385 | */ |
Anton Blanchard | dfbe93a | 2011-08-10 20:44:23 +0000 | [diff] [blame] | 386 | if (num_cpus == 1) { |
Anton Blanchard | 7946d5a | 2013-08-07 02:01:30 +1000 | [diff] [blame] | 387 | const __be32 *sizep, *lsizep; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 388 | u32 size, lsize; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 389 | |
| 390 | size = 0; |
| 391 | lsize = cur_cpu_spec->dcache_bsize; |
Stephen Rothwell | e2eb639 | 2007-04-03 22:26:41 +1000 | [diff] [blame] | 392 | sizep = of_get_property(np, "d-cache-size", NULL); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 393 | if (sizep != NULL) |
Anton Blanchard | 7946d5a | 2013-08-07 02:01:30 +1000 | [diff] [blame] | 394 | size = be32_to_cpu(*sizep); |
Anton Blanchard | dfbe93a | 2011-08-10 20:44:23 +0000 | [diff] [blame] | 395 | lsizep = of_get_property(np, "d-cache-block-size", |
| 396 | NULL); |
Benjamin Herrenschmidt | 20474ab | 2007-10-28 08:49:28 +1100 | [diff] [blame] | 397 | /* fallback if block size missing */ |
| 398 | if (lsizep == NULL) |
Anton Blanchard | dfbe93a | 2011-08-10 20:44:23 +0000 | [diff] [blame] | 399 | lsizep = of_get_property(np, |
| 400 | "d-cache-line-size", |
| 401 | NULL); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 402 | if (lsizep != NULL) |
Anton Blanchard | 7946d5a | 2013-08-07 02:01:30 +1000 | [diff] [blame] | 403 | lsize = be32_to_cpu(*lsizep); |
Anton Blanchard | b0d436c | 2013-08-07 02:01:24 +1000 | [diff] [blame] | 404 | if (sizep == NULL || lsizep == NULL) |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 405 | DBG("Argh, can't find dcache properties ! " |
| 406 | "sizep: %p, lsizep: %p\n", sizep, lsizep); |
| 407 | |
Benjamin Herrenschmidt | a7f290d | 2005-11-11 21:15:21 +1100 | [diff] [blame] | 408 | ppc64_caches.dsize = size; |
| 409 | ppc64_caches.dline_size = lsize; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 410 | ppc64_caches.log_dline_size = __ilog2(lsize); |
| 411 | ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; |
| 412 | |
| 413 | size = 0; |
| 414 | lsize = cur_cpu_spec->icache_bsize; |
Stephen Rothwell | e2eb639 | 2007-04-03 22:26:41 +1000 | [diff] [blame] | 415 | sizep = of_get_property(np, "i-cache-size", NULL); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 416 | if (sizep != NULL) |
Anton Blanchard | 7946d5a | 2013-08-07 02:01:30 +1000 | [diff] [blame] | 417 | size = be32_to_cpu(*sizep); |
Anton Blanchard | dfbe93a | 2011-08-10 20:44:23 +0000 | [diff] [blame] | 418 | lsizep = of_get_property(np, "i-cache-block-size", |
| 419 | NULL); |
Benjamin Herrenschmidt | 20474ab | 2007-10-28 08:49:28 +1100 | [diff] [blame] | 420 | if (lsizep == NULL) |
Anton Blanchard | dfbe93a | 2011-08-10 20:44:23 +0000 | [diff] [blame] | 421 | lsizep = of_get_property(np, |
| 422 | "i-cache-line-size", |
| 423 | NULL); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 424 | if (lsizep != NULL) |
Anton Blanchard | 7946d5a | 2013-08-07 02:01:30 +1000 | [diff] [blame] | 425 | lsize = be32_to_cpu(*lsizep); |
Anton Blanchard | b0d436c | 2013-08-07 02:01:24 +1000 | [diff] [blame] | 426 | if (sizep == NULL || lsizep == NULL) |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 427 | DBG("Argh, can't find icache properties ! " |
| 428 | "sizep: %p, lsizep: %p\n", sizep, lsizep); |
| 429 | |
Benjamin Herrenschmidt | a7f290d | 2005-11-11 21:15:21 +1100 | [diff] [blame] | 430 | ppc64_caches.isize = size; |
| 431 | ppc64_caches.iline_size = lsize; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 432 | ppc64_caches.log_iline_size = __ilog2(lsize); |
| 433 | ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; |
| 434 | } |
| 435 | } |
| 436 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 437 | DBG(" <- initialize_cache_info()\n"); |
| 438 | } |
| 439 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 440 | |
| 441 | /* |
| 442 | * Do some initial setup of the system. The parameters are those which |
| 443 | * were passed in from the bootloader. |
| 444 | */ |
| 445 | void __init setup_system(void) |
| 446 | { |
| 447 | DBG(" -> setup_system()\n"); |
| 448 | |
Tony Breeds | 826ea8f | 2007-07-18 16:17:48 +1000 | [diff] [blame] | 449 | /* Apply the CPUs-specific and firmware specific fixups to kernel |
| 450 | * text (nop out sections not relevant to this CPU or this firmware) |
Benjamin Herrenschmidt | 42c4aaa | 2006-10-24 16:42:40 +1000 | [diff] [blame] | 451 | */ |
Benjamin Herrenschmidt | 0909c8c | 2006-10-20 11:47:18 +1000 | [diff] [blame] | 452 | do_feature_fixups(cur_cpu_spec->cpu_features, |
Benjamin Herrenschmidt | 42c4aaa | 2006-10-24 16:42:40 +1000 | [diff] [blame] | 453 | &__start___ftr_fixup, &__stop___ftr_fixup); |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 454 | do_feature_fixups(cur_cpu_spec->mmu_features, |
| 455 | &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); |
Tony Breeds | 826ea8f | 2007-07-18 16:17:48 +1000 | [diff] [blame] | 456 | do_feature_fixups(powerpc_firmware_features, |
| 457 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); |
Kumar Gala | 2d1b202 | 2008-07-02 01:16:40 +1000 | [diff] [blame] | 458 | do_lwsync_fixups(cur_cpu_spec->cpu_features, |
| 459 | &__start___lwsync_fixup, &__stop___lwsync_fixup); |
Anton Blanchard | d715e43 | 2011-11-14 12:54:47 +0000 | [diff] [blame] | 460 | do_final_fixups(); |
Benjamin Herrenschmidt | 42c4aaa | 2006-10-24 16:42:40 +1000 | [diff] [blame] | 461 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 462 | /* |
| 463 | * Unflatten the device-tree passed by prom_init or kexec |
| 464 | */ |
| 465 | unflatten_device_tree(); |
| 466 | |
| 467 | /* |
| 468 | * Fill the ppc64_caches & systemcfg structures with informations |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 469 | * retrieved from the device-tree. |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 470 | */ |
| 471 | initialize_cache_info(); |
| 472 | |
| 473 | #ifdef CONFIG_PPC_RTAS |
| 474 | /* |
| 475 | * Initialize RTAS if available |
| 476 | */ |
| 477 | rtas_initialize(); |
| 478 | #endif /* CONFIG_PPC_RTAS */ |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 479 | |
| 480 | /* |
| 481 | * Check if we have an initrd provided via the device-tree |
| 482 | */ |
| 483 | check_for_initrd(); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 484 | |
| 485 | /* |
| 486 | * Do some platform specific early initializations, that includes |
| 487 | * setting up the hash table pointers. It also sets up some interrupt-mapping |
| 488 | * related options that will be used by finish_device_tree() |
| 489 | */ |
Geoff Levand | 57744ea | 2006-11-10 12:01:02 -0800 | [diff] [blame] | 490 | if (ppc_md.init_early) |
| 491 | ppc_md.init_early(); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 492 | |
Benjamin Herrenschmidt | 463ce0e | 2005-11-23 17:56:06 +1100 | [diff] [blame] | 493 | /* |
| 494 | * We can discover serial ports now since the above did setup the |
| 495 | * hash table management for us, thus ioremap works. We do that early |
| 496 | * so that further code can be debugged |
| 497 | */ |
Benjamin Herrenschmidt | 463ce0e | 2005-11-23 17:56:06 +1100 | [diff] [blame] | 498 | find_legacy_serial_ports(); |
Benjamin Herrenschmidt | 463ce0e | 2005-11-23 17:56:06 +1100 | [diff] [blame] | 499 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 500 | /* |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 501 | * Register early console |
| 502 | */ |
| 503 | register_early_udbg_console(); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 504 | |
Michael Ellerman | 47679283 | 2006-10-03 14:12:08 +1000 | [diff] [blame] | 505 | /* |
| 506 | * Initialize xmon |
| 507 | */ |
| 508 | xmon_setup(); |
Michael Ellerman | 480f6f3 | 2006-05-17 18:00:41 +1000 | [diff] [blame] | 509 | |
Paul Mackerras | 5ad5707 | 2005-11-05 10:33:55 +1100 | [diff] [blame] | 510 | smp_setup_cpu_maps(); |
Nathan Fontenot | 954e6da | 2010-08-05 07:42:11 +0000 | [diff] [blame] | 511 | check_smt_enabled(); |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 512 | setup_tlb_core_data(); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 513 | |
Andy Fleming | e16c876 | 2011-12-08 01:20:27 -0600 | [diff] [blame] | 514 | /* |
| 515 | * Freescale Book3e parts spin in a loop provided by firmware, |
| 516 | * so smp_release_cpus() does nothing for them |
| 517 | */ |
| 518 | #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_FSL_BOOK3E) |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 519 | /* Release secondary cpus out of their spinloops at 0x60 now that |
| 520 | * we can map physical -> logical CPU ids |
| 521 | */ |
| 522 | smp_release_cpus(); |
Michael Ellerman | f018b36 | 2006-02-16 14:13:50 +1100 | [diff] [blame] | 523 | #endif |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 524 | |
Serge E. Hallyn | 96b644b | 2006-10-02 02:18:13 -0700 | [diff] [blame] | 525 | printk("Starting Linux PPC64 %s\n", init_utsname()->version); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 526 | |
| 527 | printk("-----------------------------------------------------\n"); |
Ingo Molnar | fe33332 | 2009-01-06 14:26:03 +0000 | [diff] [blame] | 528 | printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); |
Yinghai Lu | 95f72d1 | 2010-07-12 14:36:09 +1000 | [diff] [blame] | 529 | printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); |
Anton Blanchard | 9697add | 2007-10-15 05:33:17 +1000 | [diff] [blame] | 530 | if (ppc64_caches.dline_size != 0x80) |
| 531 | printk("ppc64_caches.dcache_line_size = 0x%x\n", |
| 532 | ppc64_caches.dline_size); |
| 533 | if (ppc64_caches.iline_size != 0x80) |
| 534 | printk("ppc64_caches.icache_line_size = 0x%x\n", |
| 535 | ppc64_caches.iline_size); |
Benjamin Herrenschmidt | 9449168 | 2009-06-02 21:17:45 +0000 | [diff] [blame] | 536 | #ifdef CONFIG_PPC_STD_MMU_64 |
Anton Blanchard | 9697add | 2007-10-15 05:33:17 +1000 | [diff] [blame] | 537 | if (htab_address) |
| 538 | printk("htab_address = 0x%p\n", htab_address); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 539 | printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); |
Benjamin Herrenschmidt | 9449168 | 2009-06-02 21:17:45 +0000 | [diff] [blame] | 540 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
Michael Neuling | b160544 | 2008-10-22 19:39:49 +0000 | [diff] [blame] | 541 | if (PHYSICAL_START > 0) |
Michael Ellerman | e468455 | 2009-06-10 19:05:00 +0000 | [diff] [blame] | 542 | printk("physical_start = 0x%llx\n", |
| 543 | (unsigned long long)PHYSICAL_START); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 544 | printk("-----------------------------------------------------\n"); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 545 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 546 | DBG(" <- setup_system()\n"); |
| 547 | } |
| 548 | |
Benjamin Herrenschmidt | 40bd587 | 2011-05-03 14:07:01 +0000 | [diff] [blame] | 549 | /* This returns the limit below which memory accesses to the linear |
| 550 | * mapping are guarnateed not to cause a TLB or SLB miss. This is |
| 551 | * used to allocate interrupt or emergency stacks for which our |
| 552 | * exception entry path doesn't deal with being interrupted. |
| 553 | */ |
| 554 | static u64 safe_stack_limit(void) |
Anton Blanchard | 095c796 | 2010-05-10 18:59:18 +0000 | [diff] [blame] | 555 | { |
Benjamin Herrenschmidt | 40bd587 | 2011-05-03 14:07:01 +0000 | [diff] [blame] | 556 | #ifdef CONFIG_PPC_BOOK3E |
| 557 | /* Freescale BookE bolts the entire linear mapping */ |
| 558 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) |
| 559 | return linear_map_top; |
| 560 | /* Other BookE, we assume the first GB is bolted */ |
| 561 | return 1ul << 30; |
| 562 | #else |
| 563 | /* BookS, the first segment is bolted */ |
| 564 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) |
Anton Blanchard | 095c796 | 2010-05-10 18:59:18 +0000 | [diff] [blame] | 565 | return 1UL << SID_SHIFT_1T; |
Anton Blanchard | 095c796 | 2010-05-10 18:59:18 +0000 | [diff] [blame] | 566 | return 1UL << SID_SHIFT; |
Benjamin Herrenschmidt | 40bd587 | 2011-05-03 14:07:01 +0000 | [diff] [blame] | 567 | #endif |
Anton Blanchard | 095c796 | 2010-05-10 18:59:18 +0000 | [diff] [blame] | 568 | } |
| 569 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 570 | static void __init irqstack_early_init(void) |
| 571 | { |
Benjamin Herrenschmidt | 40bd587 | 2011-05-03 14:07:01 +0000 | [diff] [blame] | 572 | u64 limit = safe_stack_limit(); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 573 | unsigned int i; |
| 574 | |
| 575 | /* |
Anton Blanchard | 8f4da26 | 2010-12-08 00:55:03 +0000 | [diff] [blame] | 576 | * Interrupt stacks must be in the first segment since we |
| 577 | * cannot afford to take SLB misses on them. |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 578 | */ |
KAMEZAWA Hiroyuki | 0e55195 | 2006-03-28 14:50:51 -0800 | [diff] [blame] | 579 | for_each_possible_cpu(i) { |
Benjamin Herrenschmidt | 3c726f8 | 2005-11-07 11:06:55 +1100 | [diff] [blame] | 580 | softirq_ctx[i] = (struct thread_info *) |
Yinghai Lu | 95f72d1 | 2010-07-12 14:36:09 +1000 | [diff] [blame] | 581 | __va(memblock_alloc_base(THREAD_SIZE, |
Anton Blanchard | 095c796 | 2010-05-10 18:59:18 +0000 | [diff] [blame] | 582 | THREAD_SIZE, limit)); |
Benjamin Herrenschmidt | 3c726f8 | 2005-11-07 11:06:55 +1100 | [diff] [blame] | 583 | hardirq_ctx[i] = (struct thread_info *) |
Yinghai Lu | 95f72d1 | 2010-07-12 14:36:09 +1000 | [diff] [blame] | 584 | __va(memblock_alloc_base(THREAD_SIZE, |
Anton Blanchard | 095c796 | 2010-05-10 18:59:18 +0000 | [diff] [blame] | 585 | THREAD_SIZE, limit)); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 586 | } |
| 587 | } |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 588 | |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 589 | #ifdef CONFIG_PPC_BOOK3E |
| 590 | static void __init exc_lvl_early_init(void) |
| 591 | { |
| 592 | unsigned int i; |
Tiejun Chen | 160c732 | 2013-10-23 17:31:21 +0800 | [diff] [blame] | 593 | unsigned long sp; |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 594 | |
| 595 | for_each_possible_cpu(i) { |
Tiejun Chen | 160c732 | 2013-10-23 17:31:21 +0800 | [diff] [blame] | 596 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
| 597 | critirq_ctx[i] = (struct thread_info *)__va(sp); |
| 598 | paca[i].crit_kstack = __va(sp + THREAD_SIZE); |
| 599 | |
| 600 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
| 601 | dbgirq_ctx[i] = (struct thread_info *)__va(sp); |
| 602 | paca[i].dbg_kstack = __va(sp + THREAD_SIZE); |
| 603 | |
| 604 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
| 605 | mcheckirq_ctx[i] = (struct thread_info *)__va(sp); |
| 606 | paca[i].mc_kstack = __va(sp + THREAD_SIZE); |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 607 | } |
Kumar Gala | d36b4c4 | 2011-04-06 00:18:48 -0500 | [diff] [blame] | 608 | |
| 609 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) |
Kevin Hao | 565c2f2 | 2013-05-12 07:26:23 +0800 | [diff] [blame] | 610 | patch_exception(0x040, exc_debug_debug_book3e); |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 611 | } |
| 612 | #else |
| 613 | #define exc_lvl_early_init() |
| 614 | #endif |
| 615 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 616 | /* |
| 617 | * Stack space used when we detect a bad kernel stack pointer, and |
Mahesh Salgaonkar | 729b0f7 | 2013-10-30 20:04:00 +0530 | [diff] [blame] | 618 | * early in SMP boots before relocation is enabled. Exclusive emergency |
| 619 | * stack for machine checks. |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 620 | */ |
| 621 | static void __init emergency_stack_init(void) |
| 622 | { |
Anton Blanchard | 095c796 | 2010-05-10 18:59:18 +0000 | [diff] [blame] | 623 | u64 limit; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 624 | unsigned int i; |
| 625 | |
| 626 | /* |
| 627 | * Emergency stacks must be under 256MB, we cannot afford to take |
| 628 | * SLB misses on them. The ABI also requires them to be 128-byte |
| 629 | * aligned. |
| 630 | * |
| 631 | * Since we use these as temporary stacks during secondary CPU |
| 632 | * bringup, we need to get at them in real mode. This means they |
| 633 | * must also be within the RMO region. |
| 634 | */ |
Benjamin Herrenschmidt | 40bd587 | 2011-05-03 14:07:01 +0000 | [diff] [blame] | 635 | limit = min(safe_stack_limit(), ppc64_rma_size); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 636 | |
Michael Ellerman | 3243d87 | 2008-04-30 13:21:45 +1000 | [diff] [blame] | 637 | for_each_possible_cpu(i) { |
| 638 | unsigned long sp; |
Yinghai Lu | 95f72d1 | 2010-07-12 14:36:09 +1000 | [diff] [blame] | 639 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); |
Michael Ellerman | 3243d87 | 2008-04-30 13:21:45 +1000 | [diff] [blame] | 640 | sp += THREAD_SIZE; |
| 641 | paca[i].emergency_sp = __va(sp); |
Mahesh Salgaonkar | 729b0f7 | 2013-10-30 20:04:00 +0530 | [diff] [blame] | 642 | |
| 643 | #ifdef CONFIG_PPC_BOOK3S_64 |
| 644 | /* emergency stack for machine check exception handling. */ |
| 645 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); |
| 646 | sp += THREAD_SIZE; |
| 647 | paca[i].mc_emergency_sp = __va(sp); |
| 648 | #endif |
Michael Ellerman | 3243d87 | 2008-04-30 13:21:45 +1000 | [diff] [blame] | 649 | } |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 650 | } |
| 651 | |
| 652 | /* |
Alessio Igor Bogani | 0f6b77c | 2010-11-16 07:55:16 +0000 | [diff] [blame] | 653 | * Called into from start_kernel this initializes bootmem, which is used |
| 654 | * to manage page allocation until mem_init is called. |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 655 | */ |
| 656 | void __init setup_arch(char **cmdline_p) |
| 657 | { |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 658 | ppc64_boot_msg(0x12, "Setup Arch"); |
| 659 | |
| 660 | *cmdline_p = cmd_line; |
| 661 | |
| 662 | /* |
| 663 | * Set cache line size based on type of cpu as a default. |
| 664 | * Systems with OF can look in the properties on the cpu node(s) |
| 665 | * for a possibly more accurate value. |
| 666 | */ |
| 667 | dcache_bsize = ppc64_caches.dline_size; |
| 668 | icache_bsize = ppc64_caches.iline_size; |
| 669 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 670 | if (ppc_md.panic) |
Kumar Gala | 7e99026 | 2006-05-05 00:02:08 -0500 | [diff] [blame] | 671 | setup_panic(); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 672 | |
Kumar Gala | 4846c5d | 2008-04-16 05:52:26 +1000 | [diff] [blame] | 673 | init_mm.start_code = (unsigned long)_stext; |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 674 | init_mm.end_code = (unsigned long) _etext; |
| 675 | init_mm.end_data = (unsigned long) _edata; |
| 676 | init_mm.brk = klimit; |
Aneesh Kumar K.V | 5c1f6ee | 2013-04-28 09:37:33 +0000 | [diff] [blame] | 677 | #ifdef CONFIG_PPC_64K_PAGES |
| 678 | init_mm.context.pte_frag = NULL; |
| 679 | #endif |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 680 | irqstack_early_init(); |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 681 | exc_lvl_early_init(); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 682 | emergency_stack_init(); |
| 683 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 684 | /* set up the bootmem stuff with available memory */ |
| 685 | do_init_bootmem(); |
| 686 | sparse_init(); |
| 687 | |
Paul Mackerras | 0458060 | 2005-10-20 21:00:20 +1000 | [diff] [blame] | 688 | #ifdef CONFIG_DUMMY_CONSOLE |
| 689 | conswitchp = &dummy_con; |
| 690 | #endif |
| 691 | |
Grant Likely | 38db7e7 | 2007-10-11 04:48:18 +1000 | [diff] [blame] | 692 | if (ppc_md.setup_arch) |
| 693 | ppc_md.setup_arch(); |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 694 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 695 | paging_init(); |
Benjamin Herrenschmidt | 6f0ef0f | 2009-07-23 23:15:26 +0000 | [diff] [blame] | 696 | |
| 697 | /* Initialize the MMU context management stuff */ |
| 698 | mmu_context_init(); |
| 699 | |
Michael Neuling | 61e2390 | 2012-11-05 17:10:35 +1100 | [diff] [blame] | 700 | /* Interrupt code needs to be 64K-aligned */ |
| 701 | if ((unsigned long)_stext & 0xffff) |
| 702 | panic("Kernelbase not 64K-aligned (0x%lx)!\n", |
| 703 | (unsigned long)_stext); |
| 704 | |
Paul Mackerras | 40ef8cb | 2005-10-10 22:50:37 +1000 | [diff] [blame] | 705 | ppc64_boot_msg(0x15, "Setup Done"); |
| 706 | } |
| 707 | |
| 708 | |
| 709 | /* ToDo: do something useful if ppc_md is not yet setup. */ |
| 710 | #define PPC64_LINUX_FUNCTION 0x0f000000 |
| 711 | #define PPC64_IPL_MESSAGE 0xc0000000 |
| 712 | #define PPC64_TERM_MESSAGE 0xb0000000 |
| 713 | |
| 714 | static void ppc64_do_msg(unsigned int src, const char *msg) |
| 715 | { |
| 716 | if (ppc_md.progress) { |
| 717 | char buf[128]; |
| 718 | |
| 719 | sprintf(buf, "%08X\n", src); |
| 720 | ppc_md.progress(buf, 0); |
| 721 | snprintf(buf, 128, "%s", msg); |
| 722 | ppc_md.progress(buf, 0); |
| 723 | } |
| 724 | } |
| 725 | |
| 726 | /* Print a boot progress message. */ |
| 727 | void ppc64_boot_msg(unsigned int src, const char *msg) |
| 728 | { |
| 729 | ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); |
| 730 | printk("[boot]%04x %s\n", src, msg); |
| 731 | } |
| 732 | |
Anton Blanchard | 7a0268f | 2006-01-11 13:16:44 +1100 | [diff] [blame] | 733 | #ifdef CONFIG_SMP |
Tejun Heo | c2a7e81 | 2009-08-14 15:00:53 +0900 | [diff] [blame] | 734 | #define PCPU_DYN_SIZE () |
| 735 | |
| 736 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) |
| 737 | { |
| 738 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
| 739 | __pa(MAX_DMA_ADDRESS)); |
| 740 | } |
| 741 | |
| 742 | static void __init pcpu_fc_free(void *ptr, size_t size) |
| 743 | { |
| 744 | free_bootmem(__pa(ptr), size); |
| 745 | } |
| 746 | |
| 747 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
| 748 | { |
| 749 | if (cpu_to_node(from) == cpu_to_node(to)) |
| 750 | return LOCAL_DISTANCE; |
| 751 | else |
| 752 | return REMOTE_DISTANCE; |
| 753 | } |
| 754 | |
Anton Blanchard | ae01f84 | 2010-05-31 18:45:11 +0000 | [diff] [blame] | 755 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
| 756 | EXPORT_SYMBOL(__per_cpu_offset); |
| 757 | |
Anton Blanchard | 7a0268f | 2006-01-11 13:16:44 +1100 | [diff] [blame] | 758 | void __init setup_per_cpu_areas(void) |
| 759 | { |
Tejun Heo | c2a7e81 | 2009-08-14 15:00:53 +0900 | [diff] [blame] | 760 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; |
| 761 | size_t atom_size; |
| 762 | unsigned long delta; |
| 763 | unsigned int cpu; |
| 764 | int rc; |
Anton Blanchard | 7a0268f | 2006-01-11 13:16:44 +1100 | [diff] [blame] | 765 | |
Tejun Heo | c2a7e81 | 2009-08-14 15:00:53 +0900 | [diff] [blame] | 766 | /* |
| 767 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need |
| 768 | * to group units. For larger mappings, use 1M atom which |
| 769 | * should be large enough to contain a number of units. |
| 770 | */ |
| 771 | if (mmu_linear_psize == MMU_PAGE_4K) |
| 772 | atom_size = PAGE_SIZE; |
| 773 | else |
| 774 | atom_size = 1 << 20; |
Anton Blanchard | 7a0268f | 2006-01-11 13:16:44 +1100 | [diff] [blame] | 775 | |
Tejun Heo | c2a7e81 | 2009-08-14 15:00:53 +0900 | [diff] [blame] | 776 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, |
| 777 | pcpu_fc_alloc, pcpu_fc_free); |
| 778 | if (rc < 0) |
| 779 | panic("cannot initialize percpu area (err=%d)", rc); |
Anton Blanchard | 7a0268f | 2006-01-11 13:16:44 +1100 | [diff] [blame] | 780 | |
Tejun Heo | c2a7e81 | 2009-08-14 15:00:53 +0900 | [diff] [blame] | 781 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; |
Anton Blanchard | ae01f84 | 2010-05-31 18:45:11 +0000 | [diff] [blame] | 782 | for_each_possible_cpu(cpu) { |
| 783 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; |
| 784 | paca[cpu].data_offset = __per_cpu_offset[cpu]; |
| 785 | } |
Anton Blanchard | 7a0268f | 2006-01-11 13:16:44 +1100 | [diff] [blame] | 786 | } |
| 787 | #endif |
Benjamin Herrenschmidt | 4cb3cee | 2006-11-11 17:25:10 +1100 | [diff] [blame] | 788 | |
Anton Blanchard | a5d8625 | 2014-06-04 17:50:47 +1000 | [diff] [blame] | 789 | #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
| 790 | unsigned long memory_block_size_bytes(void) |
| 791 | { |
| 792 | if (ppc_md.memory_block_size) |
| 793 | return ppc_md.memory_block_size(); |
| 794 | |
| 795 | return MIN_MEMORY_BLOCK_SIZE; |
| 796 | } |
| 797 | #endif |
Benjamin Herrenschmidt | 4cb3cee | 2006-11-11 17:25:10 +1100 | [diff] [blame] | 798 | |
Benjamin Herrenschmidt | ecd73cc | 2013-07-15 13:03:08 +1000 | [diff] [blame] | 799 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) |
Benjamin Herrenschmidt | 4cb3cee | 2006-11-11 17:25:10 +1100 | [diff] [blame] | 800 | struct ppc_pci_io ppc_pci_io; |
| 801 | EXPORT_SYMBOL(ppc_pci_io); |
Benjamin Herrenschmidt | ecd73cc | 2013-07-15 13:03:08 +1000 | [diff] [blame] | 802 | #endif |