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Jamie Iles7ada1892010-02-02 20:24:58 +01001/*
2 * linux/arch/arm/include/asm/perf_event.h
3 *
4 * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef __ARM_PERF_EVENT_H__
13#define __ARM_PERF_EVENT_H__
14
15/*
16 * NOP: on *most* (read: all supported) ARM platforms, the performance
17 * counter interrupts are regular interrupts and not an NMI. This
18 * means that when we receive the interrupt we can call
19 * perf_event_do_pending() that handles all of the work with
Will Deacon25d35842010-08-16 15:15:14 +010020 * interrupts disabled.
Jamie Iles7ada1892010-02-02 20:24:58 +010021 */
22static inline void
23set_perf_event_pending(void)
24{
25}
26
27/* ARM performance counters start from 1 (in the cp15 accesses) so use the
28 * same indexes here for consistency. */
29#define PERF_EVENT_INDEX_OFFSET 1
30
Will Deacon181193f2010-04-30 11:32:44 +010031/* ARM perf PMU IDs for use by internal perf clients. */
32enum arm_perf_pmu_ids {
33 ARM_PERF_PMU_ID_XSCALE1 = 0,
34 ARM_PERF_PMU_ID_XSCALE2,
35 ARM_PERF_PMU_ID_V6,
36 ARM_PERF_PMU_ID_V6MP,
37 ARM_PERF_PMU_ID_CA8,
38 ARM_PERF_PMU_ID_CA9,
39 ARM_NUM_PMU_IDS,
40};
41
42extern enum arm_perf_pmu_ids
43armpmu_get_pmu_id(void);
44
Will Deacon929f5192010-04-30 11:34:26 +010045extern int
46armpmu_get_max_events(void);
47
Jamie Iles7ada1892010-02-02 20:24:58 +010048#endif /* __ARM_PERF_EVENT_H__ */