| Jesper Nilsson | 035e111 | 2007-11-29 17:11:23 +0100 | [diff] [blame] | 1 | /* |
| 2 | * DDR SDRAM initialization - alter with care |
| 3 | * This file is intended to be included from other assembler files |
| 4 | * |
| 5 | * Note: This file may not modify r8 or r9 because they are used to |
| 6 | * carry information from the decompresser to the kernel |
| 7 | * |
| 8 | * Copyright (C) 2005-2007 Axis Communications AB |
| 9 | * |
| 10 | * Authors: Mikael Starvik <starvik@axis.com> |
| 11 | */ |
| 12 | |
| 13 | /* Just to be certain the config file is included, we include it here |
| 14 | * explicitely instead of depending on it being included in the file that |
| 15 | * uses this code. |
| 16 | */ |
| 17 | |
| 18 | #include <hwregs/asm/reg_map_asm.h> |
| 19 | #include <hwregs/asm/ddr2_defs_asm.h> |
| 20 | |
| 21 | ;; WARNING! The registers r8 and r9 are used as parameters carrying |
| 22 | ;; information from the decompressor (if the kernel was compressed). |
| 23 | ;; They should not be used in the code below. |
| 24 | |
| 25 | ;; Refer to ddr2 MDS for initialization sequence |
| 26 | |
| 27 | ; Start clock |
| 28 | move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0 |
| 29 | move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1 |
| 30 | move.d $r1, [$r0] |
| 31 | |
| 32 | ; Reset phy and start calibration |
| 33 | move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0 |
| 34 | move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \ |
| 35 | REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1 |
| 36 | move.d $r1, [$r0] |
| 37 | move.d REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1 |
| 38 | move.d $r1, [$r0] |
| 39 | |
| 40 | ; 2. Wait 200us |
| 41 | move.d 10000, $r2 |
| 42 | 1: bne 1b |
| 43 | subq 1, $r2 |
| 44 | |
| 45 | ; Issue commands |
| 46 | move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0 |
| 47 | move.d sdram_commands_start, $r2 |
| 48 | command_loop: |
| 49 | movu.b [$r2+], $r1 |
| 50 | movu.w [$r2+], $r3 |
| 51 | do_cmd: |
| 52 | lslq 16, $r1 |
| 53 | or.d $r3, $r1 |
| 54 | move.d $r1, [$r0] |
| 55 | cmp.d sdram_commands_end, $r2 |
| 56 | blo command_loop |
| 57 | nop |
| 58 | |
| 59 | ; Set timing |
| 60 | move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0 |
| 61 | move.d CONFIG_ETRAX_DDR2_TIMING, $r1 |
| 62 | move.d $r1, [$r0] |
| 63 | |
| 64 | ; Set latency |
| 65 | move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0 |
| 66 | move.d 0x13, $r1 |
| 67 | move.d $r1, [$r0] |
| 68 | |
| 69 | ; Set configuration |
| 70 | move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0 |
| 71 | move.d CONFIG_ETRAX_DDR2_CONFIG, $r1 |
| 72 | move.d $r1, [$r0] |
| 73 | |
| 74 | ba after_sdram_commands |
| 75 | nop |
| 76 | |
| 77 | sdram_commands_start: |
| 78 | .byte regk_ddr2_deselect |
| 79 | .word 0 |
| 80 | .byte regk_ddr2_pre |
| 81 | .word regk_ddr2_pre_all |
| 82 | .byte regk_ddr2_emrs2 |
| 83 | .word 0 |
| 84 | .byte regk_ddr2_emrs3 |
| 85 | .word 0 |
| 86 | .byte regk_ddr2_emrs |
| 87 | .word regk_ddr2_dll_en |
| 88 | .byte regk_ddr2_mrs |
| 89 | .word regk_ddr2_dll_rst |
| 90 | .byte regk_ddr2_pre |
| 91 | .word regk_ddr2_pre_all |
| 92 | .byte regk_ddr2_ref |
| 93 | .word 0 |
| 94 | .byte regk_ddr2_ref |
| 95 | .word 0 |
| 96 | .byte regk_ddr2_mrs |
| 97 | .word CONFIG_ETRAX_DDR2_MRS & 0xffff |
| 98 | .byte regk_ddr2_emrs |
| 99 | .word regk_ddr2_ocd_default | regk_ddr2_dll_en |
| 100 | .byte regk_ddr2_emrs |
| 101 | .word regk_ddr2_ocd_exit | regk_ddr2_dll_en | (CONFIG_ETRAX_DDR2_MRS >> 16) |
| 102 | sdram_commands_end: |
| 103 | .align 1 |
| 104 | after_sdram_commands: |