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Alan Coxda9091e2005-06-27 15:24:30 -07001/*
Alan Coxccd32e22008-11-02 21:40:08 +01002 * Copyright (C) 2004 Red Hat
Bartlomiej Zolnierkiewicz0e9b4e52007-05-05 22:03:50 +02003 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Alan Coxda9091e2005-06-27 15:24:30 -07004 *
5 * May be copied or modified under the terms of the GNU General Public License
6 * Based in part on the ITE vendor provided SCSI driver.
7 *
Bartlomiej Zolnierkiewiczf38344b2009-02-25 20:28:22 +01008 * Documentation:
9 * Datasheet is freely available, some other documents under NDA.
Alan Coxda9091e2005-06-27 15:24:30 -070010 *
11 * The ITE8212 isn't exactly a standard IDE controller. It has two
12 * modes. In pass through mode then it is an IDE controller. In its smart
13 * mode its actually quite a capable hardware raid controller disguised
14 * as an IDE controller. Smart mode only understands DMA read/write and
15 * identify, none of the fancier commands apply. The IT8211 is identical
16 * in other respects but lacks the raid mode.
17 *
18 * Errata:
19 * o Rev 0x10 also requires master/slave hold the same DMA timings and
20 * cannot do ATAPI MWDMA.
21 * o The identify data for raid volumes lacks CHS info (technically ok)
22 * but also fails to set the LBA28 and other bits. We fix these in
23 * the IDE probe quirk code.
24 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
25 * raid then the controller firmware dies
26 * o Smart mode without RAID doesn't clear all the necessary identify
27 * bits to reduce the command set to the one used
28 *
29 * This has a few impacts on the driver
30 * - In pass through mode we do all the work you would expect
31 * - In smart mode the clocking set up is done by the controller generally
32 * but we must watch the other limits and filter.
33 * - There are a few extra vendor commands that actually talk to the
34 * controller but only work PIO with no IRQ.
35 *
36 * Vendor areas of the identify block in smart mode are used for the
37 * timing and policy set up. Each HDD in raid mode also has a serial
38 * block on the disk. The hardware extra commands are get/set chip status,
39 * rebuild, get rebuild status.
40 *
41 * In Linux the driver supports pass through mode as if the device was
42 * just another IDE controller. If the smart mode is running then
43 * volumes are managed by the controller firmware and each IDE "disk"
44 * is a raid volume. Even more cute - the controller can do automated
45 * hotplug and rebuild.
46 *
47 * The pass through controller itself is a little demented. It has a
48 * flaw that it has a single set of PIO/MWDMA timings per channel so
49 * non UDMA devices restrict each others performance. It also has a
50 * single clock source per channel so mixed UDMA100/133 performance
51 * isn't perfect and we have to pick a clock. Thankfully none of this
52 * matters in smart mode. ATAPI DMA is not currently supported.
53 *
54 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
55 *
56 * TODO
57 * - ATAPI UDMA is ok but not MWDMA it seems
58 * - RAID configuration ioctls
59 * - Move to libata once it grows up
60 */
61
Alan Coxda9091e2005-06-27 15:24:30 -070062#include <linux/types.h>
63#include <linux/module.h>
64#include <linux/pci.h>
Alan Coxda9091e2005-06-27 15:24:30 -070065#include <linux/ide.h>
66#include <linux/init.h>
67
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +020068#define DRV_NAME "it821x"
69
Brandon Philipsb94b8982009-01-14 19:19:02 +010070#define QUIRK_VORTEX86 1
71
Alan Coxda9091e2005-06-27 15:24:30 -070072struct it821x_dev
73{
74 unsigned int smart:1, /* Are we in smart raid mode */
75 timing10:1; /* Rev 0x10 */
76 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
77 u8 want[2][2]; /* Mode/Pri log for master slave */
78 /* We need these for switching the clock when DMA goes on/off
79 The high byte is the 66Mhz timing */
80 u16 pio[2]; /* Cached PIO values */
81 u16 mwdma[2]; /* Cached MWDMA values */
82 u16 udma[2]; /* Cached UDMA values (per drive) */
Brandon Philipsb94b8982009-01-14 19:19:02 +010083 u16 quirks;
Alan Coxda9091e2005-06-27 15:24:30 -070084};
85
86#define ATA_66 0
87#define ATA_50 1
88#define ATA_ANY 2
89
90#define UDMA_OFF 0
91#define MWDMA_OFF 0
92
93/*
94 * We allow users to force the card into non raid mode without
Robert P. J. Day3a4fa0a2007-10-19 23:10:43 +020095 * flashing the alternative BIOS. This is also necessary right now
Alan Coxda9091e2005-06-27 15:24:30 -070096 * for embedded platforms that cannot run a PC BIOS but are using this
97 * device.
98 */
99
100static int it8212_noraid;
101
102/**
103 * it821x_program - program the PIO/MWDMA registers
104 * @drive: drive to tune
Bartlomiej Zolnierkiewicz0e9b4e52007-05-05 22:03:50 +0200105 * @timing: timing info
Alan Coxda9091e2005-06-27 15:24:30 -0700106 *
107 * Program the PIO/MWDMA timing for this channel according to the
108 * current clock.
109 */
110
111static void it821x_program(ide_drive_t *drive, u16 timing)
112{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100113 ide_hwif_t *hwif = drive->hwif;
114 struct pci_dev *dev = to_pci_dev(hwif->dev);
Alan Coxda9091e2005-06-27 15:24:30 -0700115 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
116 int channel = hwif->channel;
117 u8 conf;
118
119 /* Program PIO/MWDMA timing bits */
120 if(itdev->clock_mode == ATA_66)
121 conf = timing >> 8;
122 else
123 conf = timing & 0xFF;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100124
125 pci_write_config_byte(dev, 0x54 + 4 * channel, conf);
Alan Coxda9091e2005-06-27 15:24:30 -0700126}
127
128/**
129 * it821x_program_udma - program the UDMA registers
130 * @drive: drive to tune
Bartlomiej Zolnierkiewicz0e9b4e52007-05-05 22:03:50 +0200131 * @timing: timing info
Alan Coxda9091e2005-06-27 15:24:30 -0700132 *
133 * Program the UDMA timing for this drive according to the
134 * current clock.
135 */
136
137static void it821x_program_udma(ide_drive_t *drive, u16 timing)
138{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100139 ide_hwif_t *hwif = drive->hwif;
140 struct pci_dev *dev = to_pci_dev(hwif->dev);
Alan Coxda9091e2005-06-27 15:24:30 -0700141 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
142 int channel = hwif->channel;
Bartlomiej Zolnierkiewicz123995b2008-10-13 21:39:40 +0200143 u8 unit = drive->dn & 1, conf;
Alan Coxda9091e2005-06-27 15:24:30 -0700144
145 /* Program UDMA timing bits */
146 if(itdev->clock_mode == ATA_66)
147 conf = timing >> 8;
148 else
149 conf = timing & 0xFF;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100150
151 if (itdev->timing10 == 0)
152 pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf);
Alan Coxda9091e2005-06-27 15:24:30 -0700153 else {
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100154 pci_write_config_byte(dev, 0x56 + 4 * channel, conf);
155 pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf);
Alan Coxda9091e2005-06-27 15:24:30 -0700156 }
157}
158
Alan Coxda9091e2005-06-27 15:24:30 -0700159/**
160 * it821x_clock_strategy
Bartlomiej Zolnierkiewicz0e9b4e52007-05-05 22:03:50 +0200161 * @drive: drive to set up
Alan Coxda9091e2005-06-27 15:24:30 -0700162 *
163 * Select between the 50 and 66Mhz base clocks to get the best
164 * results for this interface.
165 */
166
167static void it821x_clock_strategy(ide_drive_t *drive)
168{
169 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100170 struct pci_dev *dev = to_pci_dev(hwif->dev);
Alan Coxda9091e2005-06-27 15:24:30 -0700171 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
Bartlomiej Zolnierkiewicz07af5a52009-01-06 17:20:56 +0100172 ide_drive_t *pair = ide_get_pair_dev(drive);
Bartlomiej Zolnierkiewicz123995b2008-10-13 21:39:40 +0200173 int clock, altclock, sel = 0;
174 u8 unit = drive->dn & 1, v;
Alan Coxda9091e2005-06-27 15:24:30 -0700175
Alan Coxda9091e2005-06-27 15:24:30 -0700176 if(itdev->want[0][0] > itdev->want[1][0]) {
177 clock = itdev->want[0][1];
178 altclock = itdev->want[1][1];
179 } else {
180 clock = itdev->want[1][1];
181 altclock = itdev->want[0][1];
182 }
183
Bartlomiej Zolnierkiewicz0e9b4e52007-05-05 22:03:50 +0200184 /*
185 * if both clocks can be used for the mode with the higher priority
186 * use the clock needed by the mode with the lower priority
187 */
188 if (clock == ATA_ANY)
Alan Coxda9091e2005-06-27 15:24:30 -0700189 clock = altclock;
190
191 /* Nobody cares - keep the same clock */
192 if(clock == ATA_ANY)
193 return;
194 /* No change */
195 if(clock == itdev->clock_mode)
196 return;
197
198 /* Load this into the controller ? */
199 if(clock == ATA_66)
200 itdev->clock_mode = ATA_66;
201 else {
202 itdev->clock_mode = ATA_50;
203 sel = 1;
204 }
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100205
206 pci_read_config_byte(dev, 0x50, &v);
Alan Coxda9091e2005-06-27 15:24:30 -0700207 v &= ~(1 << (1 + hwif->channel));
208 v |= sel << (1 + hwif->channel);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100209 pci_write_config_byte(dev, 0x50, v);
Alan Coxda9091e2005-06-27 15:24:30 -0700210
211 /*
212 * Reprogram the UDMA/PIO of the pair drive for the switch
213 * MWDMA will be dealt with by the dma switcher
214 */
215 if(pair && itdev->udma[1-unit] != UDMA_OFF) {
216 it821x_program_udma(pair, itdev->udma[1-unit]);
217 it821x_program(pair, itdev->pio[1-unit]);
218 }
219 /*
220 * Reprogram the UDMA/PIO of our drive for the switch.
221 * MWDMA will be dealt with by the dma switcher
222 */
223 if(itdev->udma[unit] != UDMA_OFF) {
224 it821x_program_udma(drive, itdev->udma[unit]);
225 it821x_program(drive, itdev->pio[unit]);
226 }
227}
228
229/**
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200230 * it821x_set_pio_mode - set host controller for PIO mode
Bartlomiej Zolnierkiewicze085b3c2010-01-19 01:44:41 -0800231 * @hwif: port
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200232 * @drive: drive
Alan Coxda9091e2005-06-27 15:24:30 -0700233 *
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200234 * Tune the host to the desired PIO mode taking into the consideration
235 * the maximum PIO mode supported by the other device on the cable.
Alan Coxda9091e2005-06-27 15:24:30 -0700236 */
237
Bartlomiej Zolnierkiewicze085b3c2010-01-19 01:44:41 -0800238static void it821x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
Alan Coxda9091e2005-06-27 15:24:30 -0700239{
Alan Coxda9091e2005-06-27 15:24:30 -0700240 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
Bartlomiej Zolnierkiewicz07af5a52009-01-06 17:20:56 +0100241 ide_drive_t *pair = ide_get_pair_dev(drive);
Bartlomiej Zolnierkiewicze085b3c2010-01-19 01:44:41 -0800242 const u8 pio = drive->pio_mode - XFER_PIO_0;
Bartlomiej Zolnierkiewicz123995b2008-10-13 21:39:40 +0200243 u8 unit = drive->dn & 1, set_pio = pio;
Alan Coxda9091e2005-06-27 15:24:30 -0700244
245 /* Spec says 89 ref driver uses 88 */
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200246 static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
Alan Coxda9091e2005-06-27 15:24:30 -0700247 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
248
Bartlomiej Zolnierkiewicz0e9b4e52007-05-05 22:03:50 +0200249 /*
250 * Compute the best PIO mode we can for a given device. We must
251 * pick a speed that does not cause problems with the other device
252 * on the cable.
253 */
254 if (pair) {
Bartlomiej Zolnierkiewiczf6579112010-01-18 07:22:02 +0000255 u8 pair_pio = pair->pio_mode - XFER_PIO_0;
Bartlomiej Zolnierkiewicz0e9b4e52007-05-05 22:03:50 +0200256 /* trim PIO to the slowest of the master/slave */
257 if (pair_pio < set_pio)
258 set_pio = pair_pio;
259 }
260
Alan Coxda9091e2005-06-27 15:24:30 -0700261 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
Bartlomiej Zolnierkiewicz0e9b4e52007-05-05 22:03:50 +0200262 itdev->want[unit][1] = pio_want[set_pio];
Alan Coxda9091e2005-06-27 15:24:30 -0700263 itdev->want[unit][0] = 1; /* PIO is lowest priority */
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200264 itdev->pio[unit] = pio_timings[set_pio];
Alan Coxda9091e2005-06-27 15:24:30 -0700265 it821x_clock_strategy(drive);
266 it821x_program(drive, itdev->pio[unit]);
267}
268
269/**
270 * it821x_tune_mwdma - tune a channel for MWDMA
271 * @drive: drive to set up
272 * @mode_wanted: the target operating mode
273 *
274 * Load the timing settings for this device mode into the
275 * controller when doing MWDMA in pass through mode. The caller
276 * must manage the whole lack of per device MWDMA/PIO timings and
277 * the shared MWDMA/PIO timing register.
278 */
279
Bartlomiej Zolnierkiewicz9892ec52009-01-06 17:20:53 +0100280static void it821x_tune_mwdma(ide_drive_t *drive, u8 mode_wanted)
Alan Coxda9091e2005-06-27 15:24:30 -0700281{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100282 ide_hwif_t *hwif = drive->hwif;
283 struct pci_dev *dev = to_pci_dev(hwif->dev);
Alan Coxda9091e2005-06-27 15:24:30 -0700284 struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
Bartlomiej Zolnierkiewicz123995b2008-10-13 21:39:40 +0200285 u8 unit = drive->dn & 1, channel = hwif->channel, conf;
Alan Coxda9091e2005-06-27 15:24:30 -0700286
287 static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
288 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
289
290 itdev->want[unit][1] = mwdma_want[mode_wanted];
291 itdev->want[unit][0] = 2; /* MWDMA is low priority */
292 itdev->mwdma[unit] = dma[mode_wanted];
293 itdev->udma[unit] = UDMA_OFF;
294
295 /* UDMA bits off - Revision 0x10 do them in pairs */
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100296 pci_read_config_byte(dev, 0x50, &conf);
297 if (itdev->timing10)
Alan Coxda9091e2005-06-27 15:24:30 -0700298 conf |= channel ? 0x60: 0x18;
299 else
300 conf |= 1 << (3 + 2 * channel + unit);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100301 pci_write_config_byte(dev, 0x50, conf);
Alan Coxda9091e2005-06-27 15:24:30 -0700302
303 it821x_clock_strategy(drive);
304 /* FIXME: do we need to program this ? */
305 /* it821x_program(drive, itdev->mwdma[unit]); */
306}
307
308/**
309 * it821x_tune_udma - tune a channel for UDMA
310 * @drive: drive to set up
311 * @mode_wanted: the target operating mode
312 *
313 * Load the timing settings for this device mode into the
314 * controller when doing UDMA modes in pass through.
315 */
316
Bartlomiej Zolnierkiewicz9892ec52009-01-06 17:20:53 +0100317static void it821x_tune_udma(ide_drive_t *drive, u8 mode_wanted)
Alan Coxda9091e2005-06-27 15:24:30 -0700318{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100319 ide_hwif_t *hwif = drive->hwif;
320 struct pci_dev *dev = to_pci_dev(hwif->dev);
Alan Coxda9091e2005-06-27 15:24:30 -0700321 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
Bartlomiej Zolnierkiewicz123995b2008-10-13 21:39:40 +0200322 u8 unit = drive->dn & 1, channel = hwif->channel, conf;
Alan Coxda9091e2005-06-27 15:24:30 -0700323
324 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
325 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
326
327 itdev->want[unit][1] = udma_want[mode_wanted];
328 itdev->want[unit][0] = 3; /* UDMA is high priority */
329 itdev->mwdma[unit] = MWDMA_OFF;
330 itdev->udma[unit] = udma[mode_wanted];
331 if(mode_wanted >= 5)
332 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
333
334 /* UDMA on. Again revision 0x10 must do the pair */
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100335 pci_read_config_byte(dev, 0x50, &conf);
336 if (itdev->timing10)
Alan Coxda9091e2005-06-27 15:24:30 -0700337 conf &= channel ? 0x9F: 0xE7;
338 else
339 conf &= ~ (1 << (3 + 2 * channel + unit));
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100340 pci_write_config_byte(dev, 0x50, conf);
Alan Coxda9091e2005-06-27 15:24:30 -0700341
342 it821x_clock_strategy(drive);
343 it821x_program_udma(drive, itdev->udma[unit]);
344
345}
346
347/**
Alan Coxda9091e2005-06-27 15:24:30 -0700348 * it821x_dma_read - DMA hook
349 * @drive: drive for DMA
350 *
351 * The IT821x has a single timing register for MWDMA and for PIO
352 * operations. As we flip back and forth we have to reload the
353 * clock. In addition the rev 0x10 device only works if the same
354 * timing value is loaded into the master and slave UDMA clock
355 * so we must also reload that.
356 *
357 * FIXME: we could figure out in advance if we need to do reloads
358 */
359
360static void it821x_dma_start(ide_drive_t *drive)
361{
362 ide_hwif_t *hwif = drive->hwif;
363 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
Bartlomiej Zolnierkiewicz123995b2008-10-13 21:39:40 +0200364 u8 unit = drive->dn & 1;
365
Alan Coxda9091e2005-06-27 15:24:30 -0700366 if(itdev->mwdma[unit] != MWDMA_OFF)
367 it821x_program(drive, itdev->mwdma[unit]);
368 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
369 it821x_program_udma(drive, itdev->udma[unit]);
370 ide_dma_start(drive);
371}
372
373/**
374 * it821x_dma_write - DMA hook
375 * @drive: drive for DMA stop
376 *
377 * The IT821x has a single timing register for MWDMA and for PIO
378 * operations. As we flip back and forth we have to reload the
379 * clock.
380 */
381
382static int it821x_dma_end(ide_drive_t *drive)
383{
384 ide_hwif_t *hwif = drive->hwif;
Alan Coxda9091e2005-06-27 15:24:30 -0700385 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
Bartlomiej Zolnierkiewicz653bcf52008-10-13 21:39:46 +0200386 int ret = ide_dma_end(drive);
Bartlomiej Zolnierkiewicz123995b2008-10-13 21:39:40 +0200387 u8 unit = drive->dn & 1;
388
Alan Coxda9091e2005-06-27 15:24:30 -0700389 if(itdev->mwdma[unit] != MWDMA_OFF)
390 it821x_program(drive, itdev->pio[unit]);
391 return ret;
392}
393
Alan Coxda9091e2005-06-27 15:24:30 -0700394/**
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200395 * it821x_set_dma_mode - set host controller for DMA mode
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800396 * @hwif: port
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200397 * @drive: drive
Alan Coxda9091e2005-06-27 15:24:30 -0700398 *
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200399 * Tune the ITE chipset for the desired DMA mode.
Alan Coxda9091e2005-06-27 15:24:30 -0700400 */
401
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800402static void it821x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
Alan Coxda9091e2005-06-27 15:24:30 -0700403{
Bartlomiej Zolnierkiewicz87761682010-01-19 01:45:29 -0800404 const u8 speed = drive->dma_mode;
405
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200406 /*
407 * MWDMA tuning is really hard because our MWDMA and PIO
408 * timings are kept in the same place. We can switch in the
409 * host dma on/off callbacks.
410 */
411 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6)
412 it821x_tune_udma(drive, speed - XFER_UDMA_0);
413 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
414 it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0);
Alan Coxda9091e2005-06-27 15:24:30 -0700415}
416
417/**
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200418 * it821x_cable_detect - cable detection
Alan Coxda9091e2005-06-27 15:24:30 -0700419 * @hwif: interface to check
420 *
421 * Check for the presence of an ATA66 capable cable on the
422 * interface. Problematic as it seems some cards don't have
423 * the needed logic onboard.
424 */
425
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +0200426static u8 it821x_cable_detect(ide_hwif_t *hwif)
Alan Coxda9091e2005-06-27 15:24:30 -0700427{
428 /* The reference driver also only does disk side */
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200429 return ATA_CBL_PATA80;
Alan Coxda9091e2005-06-27 15:24:30 -0700430}
431
432/**
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100433 * it821x_quirkproc - post init callback
434 * @drive: drive
Alan Coxda9091e2005-06-27 15:24:30 -0700435 *
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100436 * This callback is run after the drive has been probed but
Alan Coxda9091e2005-06-27 15:24:30 -0700437 * before anything gets attached. It allows drivers to do any
438 * final tuning that is needed, or fixups to work around bugs.
439 */
440
Bartlomiej Zolnierkiewicz36de9942008-08-05 18:17:03 +0200441static void it821x_quirkproc(ide_drive_t *drive)
Alan Coxda9091e2005-06-27 15:24:30 -0700442{
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100443 struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif);
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200444 u16 *id = drive->id;
Alan Coxda9091e2005-06-27 15:24:30 -0700445
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100446 if (!itdev->smart) {
Alan Coxda9091e2005-06-27 15:24:30 -0700447 /*
448 * If we are in pass through mode then not much
449 * needs to be done, but we do bother to clear the
450 * IRQ mask as we may well be in PIO (eg rev 0x10)
451 * for now and we know unmasking is safe on this chipset.
452 */
Bartlomiej Zolnierkiewicz97100fc2008-10-13 21:39:36 +0200453 drive->dev_flags |= IDE_DFLAG_UNMASK;
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100454 } else {
Alan Coxda9091e2005-06-27 15:24:30 -0700455 /*
456 * Perform fixups on smart mode. We need to "lose" some
457 * capabilities the firmware lacks but does not filter, and
458 * also patch up some capability bits that it forgets to set
459 * in RAID mode.
460 */
461
Alan Coxda9091e2005-06-27 15:24:30 -0700462 /* Check for RAID v native */
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200463 if (strstr((char *)&id[ATA_ID_PROD],
464 "Integrated Technology Express")) {
Alan Coxda9091e2005-06-27 15:24:30 -0700465 /* In raid mode the ident block is slightly buggy
466 We need to set the bits so that the IDE layer knows
467 LBA28. LBA48 and DMA ar valid */
Bartlomiej Zolnierkiewicz48fb2682008-10-10 22:39:19 +0200468 id[ATA_ID_CAPABILITY] |= (3 << 8); /* LBA28, DMA */
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200469 id[ATA_ID_COMMAND_SET_2] |= 0x0400; /* LBA48 valid */
470 id[ATA_ID_CFS_ENABLE_2] |= 0x0400; /* LBA48 on */
Alan Coxda9091e2005-06-27 15:24:30 -0700471 /* Reporting logic */
472 printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200473 drive->name, id[147] ? "Bootable " : "",
474 id[ATA_ID_CSFO]);
475 if (id[ATA_ID_CSFO] != 1)
476 printk(KERN_CONT "(%dK stripe)", id[146]);
477 printk(KERN_CONT ".\n");
Alan Coxda9091e2005-06-27 15:24:30 -0700478 } else {
479 /* Non RAID volume. Fixups to stop the core code
480 doing unsupported things */
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200481 id[ATA_ID_FIELD_VALID] &= 3;
482 id[ATA_ID_QUEUE_DEPTH] = 0;
483 id[ATA_ID_COMMAND_SET_1] = 0;
484 id[ATA_ID_COMMAND_SET_2] &= 0xC400;
485 id[ATA_ID_CFSSE] &= 0xC000;
486 id[ATA_ID_CFS_ENABLE_1] = 0;
487 id[ATA_ID_CFS_ENABLE_2] &= 0xC400;
488 id[ATA_ID_CSF_DEFAULT] &= 0xC000;
489 id[127] = 0;
490 id[ATA_ID_DLF] = 0;
491 id[ATA_ID_CSFO] = 0;
492 id[ATA_ID_CFA_POWER] = 0;
Alan Coxda9091e2005-06-27 15:24:30 -0700493 printk(KERN_INFO "%s: Performing identify fixups.\n",
494 drive->name);
495 }
Bartlomiej Zolnierkiewicz0380dad2007-06-08 15:14:29 +0200496
497 /*
498 * Set MWDMA0 mode as enabled/support - just to tell
499 * IDE core that DMA is supported (it821x hardware
500 * takes care of DMA mode programming).
501 */
Bartlomiej Zolnierkiewicz48fb2682008-10-10 22:39:19 +0200502 if (ata_id_has_dma(id)) {
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200503 id[ATA_ID_MWDMA_MODES] |= 0x0101;
Bartlomiej Zolnierkiewicz0380dad2007-06-08 15:14:29 +0200504 drive->current_speed = XFER_MW_DMA_0;
505 }
Alan Coxda9091e2005-06-27 15:24:30 -0700506 }
507
508}
509
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200510static struct ide_dma_ops it821x_pass_through_dma_ops = {
Dimitri Gorokhovik84e0f3f2008-07-16 20:33:34 +0200511 .dma_host_set = ide_dma_host_set,
512 .dma_setup = ide_dma_setup,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200513 .dma_start = it821x_dma_start,
514 .dma_end = it821x_dma_end,
Dimitri Gorokhovik84e0f3f2008-07-16 20:33:34 +0200515 .dma_test_irq = ide_dma_test_irq,
Dimitri Gorokhovik84e0f3f2008-07-16 20:33:34 +0200516 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz35c9b4d2009-03-31 20:15:19 +0200517 .dma_timer_expiry = ide_dma_sff_timer_expiry,
Sergei Shtylyov592b5312009-01-06 17:21:02 +0100518 .dma_sff_read_status = ide_dma_sff_read_status,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200519};
520
Alan Coxda9091e2005-06-27 15:24:30 -0700521/**
522 * init_hwif_it821x - set up hwif structs
523 * @hwif: interface to set up
524 *
525 * We do the basic set up of the interface structure. The IT8212
526 * requires several custom handlers so we override the default
527 * ide DMA handlers appropriately
528 */
529
530static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
531{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100532 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewicz1d76d9d2008-07-24 22:53:16 +0200533 struct ide_host *host = pci_get_drvdata(dev);
534 struct it821x_dev *itdevs = host->host_priv;
535 struct it821x_dev *idev = itdevs + hwif->channel;
Alan Coxda9091e2005-06-27 15:24:30 -0700536 u8 conf;
537
Alan Coxda9091e2005-06-27 15:24:30 -0700538 ide_set_hwifdata(hwif, idev);
539
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100540 pci_read_config_byte(dev, 0x50, &conf);
Bartlomiej Zolnierkiewicz33c10022007-10-19 00:30:06 +0200541 if (conf & 1) {
Alan Coxda9091e2005-06-27 15:24:30 -0700542 idev->smart = 1;
Bartlomiej Zolnierkiewicz33c10022007-10-19 00:30:06 +0200543 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
Alan Coxda9091e2005-06-27 15:24:30 -0700544 /* Long I/O's although allowed in LBA48 space cause the
545 onboard firmware to enter the twighlight zone */
546 hwif->rqsize = 256;
547 }
548
549 /* Pull the current clocks from 0x50 also */
550 if (conf & (1 << (1 + hwif->channel)))
551 idev->clock_mode = ATA_50;
552 else
553 idev->clock_mode = ATA_66;
554
555 idev->want[0][1] = ATA_ANY;
556 idev->want[1][1] = ATA_ANY;
557
558 /*
559 * Not in the docs but according to the reference driver
Robert P. J. Day3a4fa0a2007-10-19 23:10:43 +0200560 * this is necessary.
Alan Coxda9091e2005-06-27 15:24:30 -0700561 */
562
Brandon Philips4a246262009-01-14 19:19:03 +0100563 if (dev->revision == 0x10) {
Alan Coxda9091e2005-06-27 15:24:30 -0700564 idev->timing10 = 1;
Bartlomiej Zolnierkiewicz33c10022007-10-19 00:30:06 +0200565 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
566 if (idev->smart == 0)
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200567 printk(KERN_WARNING DRV_NAME " %s: revision 0x10, "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200568 "workarounds activated\n", pci_name(dev));
Alan Coxda9091e2005-06-27 15:24:30 -0700569 }
570
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200571 if (idev->smart == 0) {
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200572 /* MWDMA/PIO clock switching for pass through mode */
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200573 hwif->dma_ops = &it821x_pass_through_dma_ops;
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200574 } else
575 hwif->host_flags |= IDE_HFLAG_NO_SET_MODE;
Alan Coxda9091e2005-06-27 15:24:30 -0700576
Bartlomiej Zolnierkiewicz9ff6f722007-10-16 22:29:58 +0200577 if (hwif->dma_base == 0)
578 return;
Alan Coxda9091e2005-06-27 15:24:30 -0700579
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +0200580 hwif->ultra_mask = ATA_UDMA6;
581 hwif->mwdma_mask = ATA_MWDMA2;
Brandon Philipsb94b8982009-01-14 19:19:02 +0100582
583 /* Vortex86SX quirk: prevent Ultra-DMA mode to fix BadCRC issue */
584 if (idev->quirks & QUIRK_VORTEX86) {
585 if (dev->revision == 0x11)
586 hwif->ultra_mask = 0;
587 }
Alan Coxda9091e2005-06-27 15:24:30 -0700588}
589
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200590static void it8212_disable_raid(struct pci_dev *dev)
Alan Coxda9091e2005-06-27 15:24:30 -0700591{
592 /* Reset local CPU, and set BIOS not ready */
593 pci_write_config_byte(dev, 0x5E, 0x01);
594
595 /* Set to bypass mode, and reset PCI bus */
596 pci_write_config_byte(dev, 0x50, 0x00);
597 pci_write_config_word(dev, PCI_COMMAND,
598 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
599 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
600 pci_write_config_word(dev, 0x40, 0xA0F3);
601
602 pci_write_config_dword(dev,0x4C, 0x02040204);
603 pci_write_config_byte(dev, 0x42, 0x36);
Alan Cox0c866b52006-02-03 03:04:58 -0800604 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
Alan Coxda9091e2005-06-27 15:24:30 -0700605}
606
Bartlomiej Zolnierkiewicz2ed0ef52009-03-24 23:22:53 +0100607static int init_chipset_it821x(struct pci_dev *dev)
Alan Coxda9091e2005-06-27 15:24:30 -0700608{
609 u8 conf;
610 static char *mode[2] = { "pass through", "smart" };
611
612 /* Force the card into bypass mode if so requested */
613 if (it8212_noraid) {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200614 printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n",
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200615 pci_name(dev));
Alan Coxda9091e2005-06-27 15:24:30 -0700616 it8212_disable_raid(dev);
617 }
618 pci_read_config_byte(dev, 0x50, &conf);
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200619 printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n",
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200620 pci_name(dev), mode[conf & 1]);
Alan Coxda9091e2005-06-27 15:24:30 -0700621 return 0;
622}
623
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200624static const struct ide_port_ops it821x_port_ops = {
625 /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */
626 .set_pio_mode = it821x_set_pio_mode,
627 .set_dma_mode = it821x_set_dma_mode,
628 .quirkproc = it821x_quirkproc,
629 .cable_detect = it821x_cable_detect,
630};
Alan Coxda9091e2005-06-27 15:24:30 -0700631
Bartlomiej Zolnierkiewicz04ba6e72008-07-24 22:53:32 +0200632static const struct ide_port_info it821x_chipset __devinitdata = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200633 .name = DRV_NAME,
Bartlomiej Zolnierkiewicz04ba6e72008-07-24 22:53:32 +0200634 .init_chipset = init_chipset_it821x,
635 .init_hwif = init_hwif_it821x,
636 .port_ops = &it821x_port_ops,
637 .pio_mask = ATA_PIO4,
Alan Coxda9091e2005-06-27 15:24:30 -0700638};
639
640/**
641 * it821x_init_one - pci layer discovery entry
642 * @dev: PCI device
643 * @id: ident table entry
644 *
645 * Called by the PCI code when it finds an ITE821x controller.
646 * We then use the IDE PCI generic helper to do most of the work.
647 */
648
649static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
650{
Bartlomiej Zolnierkiewicz1d76d9d2008-07-24 22:53:16 +0200651 struct it821x_dev *itdevs;
652 int rc;
Bartlomiej Zolnierkiewiczeb7a07e2008-04-26 17:36:42 +0200653
Bartlomiej Zolnierkiewicz1d76d9d2008-07-24 22:53:16 +0200654 itdevs = kzalloc(2 * sizeof(*itdevs), GFP_KERNEL);
655 if (itdevs == NULL) {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200656 printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev));
Bartlomiej Zolnierkiewicz1d76d9d2008-07-24 22:53:16 +0200657 return -ENOMEM;
Bartlomiej Zolnierkiewiczeb7a07e2008-04-26 17:36:42 +0200658 }
659
Brandon Philipsb94b8982009-01-14 19:19:02 +0100660 itdevs->quirks = id->driver_data;
661
Bartlomiej Zolnierkiewicz04ba6e72008-07-24 22:53:32 +0200662 rc = ide_pci_init_one(dev, &it821x_chipset, itdevs);
Bartlomiej Zolnierkiewicz1d76d9d2008-07-24 22:53:16 +0200663 if (rc)
664 kfree(itdevs);
Bartlomiej Zolnierkiewiczeb7a07e2008-04-26 17:36:42 +0200665
Bartlomiej Zolnierkiewicz1d76d9d2008-07-24 22:53:16 +0200666 return rc;
Alan Coxda9091e2005-06-27 15:24:30 -0700667}
668
Bartlomiej Zolnierkiewicz87d8b612008-07-24 22:53:22 +0200669static void __devexit it821x_remove(struct pci_dev *dev)
670{
671 struct ide_host *host = pci_get_drvdata(dev);
672 struct it821x_dev *itdevs = host->host_priv;
673
674 ide_pci_remove(dev);
675 kfree(itdevs);
676}
677
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +0200678static const struct pci_device_id it821x_pci_tbl[] = {
679 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 },
680 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 },
Brandon Philipsb94b8982009-01-14 19:19:02 +0100681 { PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), QUIRK_VORTEX86 },
Alan Coxda9091e2005-06-27 15:24:30 -0700682 { 0, },
683};
684
685MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
686
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200687static struct pci_driver it821x_pci_driver = {
Alan Coxda9091e2005-06-27 15:24:30 -0700688 .name = "ITE821x IDE",
689 .id_table = it821x_pci_tbl,
690 .probe = it821x_init_one,
Adrian Bunka69999e2008-08-18 21:40:03 +0200691 .remove = __devexit_p(it821x_remove),
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200692 .suspend = ide_pci_suspend,
693 .resume = ide_pci_resume,
Alan Coxda9091e2005-06-27 15:24:30 -0700694};
695
696static int __init it821x_ide_init(void)
697{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200698 return ide_pci_register_driver(&it821x_pci_driver);
Alan Coxda9091e2005-06-27 15:24:30 -0700699}
700
Bartlomiej Zolnierkiewicz87d8b612008-07-24 22:53:22 +0200701static void __exit it821x_ide_exit(void)
702{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200703 pci_unregister_driver(&it821x_pci_driver);
Bartlomiej Zolnierkiewicz87d8b612008-07-24 22:53:22 +0200704}
705
Alan Coxda9091e2005-06-27 15:24:30 -0700706module_init(it821x_ide_init);
Bartlomiej Zolnierkiewicz87d8b612008-07-24 22:53:22 +0200707module_exit(it821x_ide_exit);
Alan Coxda9091e2005-06-27 15:24:30 -0700708
709module_param_named(noraid, it8212_noraid, int, S_IRUGO);
Paul Bolleda195662008-04-17 01:14:33 +0200710MODULE_PARM_DESC(noraid, "Force card into bypass mode");
Alan Coxda9091e2005-06-27 15:24:30 -0700711
712MODULE_AUTHOR("Alan Cox");
713MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
714MODULE_LICENSE("GPL");