dmitry pervushin | 34acb09 | 2009-04-22 23:54:05 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * STMP APBX Register Definitions |
| 3 | * |
| 4 | * Copyright (c) 2008 Freescale Semiconductor |
| 5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | */ |
| 21 | #ifndef _INCLUDE_ASM_ARCH_REGS_APBX_H |
| 22 | #define _INCLUDE_ASM_ARCH_REGS_APBX_H |
| 23 | |
| 24 | #include <mach/stmp3xxx_regs.h> |
| 25 | |
| 26 | #ifndef REGS_APBX_BASE |
| 27 | #define REGS_APBX_BASE (REGS_BASE + 0x00024000) |
| 28 | #endif |
| 29 | |
| 30 | HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00) |
| 31 | #define BP_APBX_CTRL0_SFTRST 31 |
| 32 | #define BM_APBX_CTRL0_SFTRST 0x80000000 |
| 33 | #define BP_APBX_CTRL0_CLKGATE 30 |
| 34 | #define BM_APBX_CTRL0_CLKGATE 0x40000000 |
| 35 | #define BP_APBX_CTRL0_RESET_CHANNEL 16 |
| 36 | #define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000 |
| 37 | #define BF_APBX_CTRL0_RESET_CHANNEL(v) \ |
| 38 | (((v) << BP_APBX_CTRL0_RESET_CHANNEL) & BM_APBX_CTRL0_RESET_CHANNEL) |
| 39 | HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x10) |
| 40 | HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x20) |
| 41 | #define BP_APBX_DEVSEL_CH7 28 |
| 42 | #define BM_APBX_DEVSEL_CH7 0xF0000000 |
| 43 | #define BF_APBX_DEVSEL_CH7(v) \ |
| 44 | (((v) << BP_APBX_DEVSEL_CH7) & BM_APBX_DEVSEL_CH7) |
| 45 | #define BV_APBX_DEVSEL_CH7__USE_UART 0x0 |
| 46 | #define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 |
| 47 | #define BP_APBX_DEVSEL_CH6 24 |
| 48 | #define BM_APBX_DEVSEL_CH6 0x0F000000 |
| 49 | #define BF_APBX_DEVSEL_CH6(v) \ |
| 50 | (((v) << BP_APBX_DEVSEL_CH6) & BM_APBX_DEVSEL_CH6) |
| 51 | #define BV_APBX_DEVSEL_CH6__USE_UART 0x0 |
| 52 | #define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1 |
| 53 | #define BP_APBX_CTRL1_CH7_AHB_ERROR_IRQ 23 |
| 54 | #define BM_APBX_CTRL1_CH7_AHB_ERROR_IRQ 0x00800000 |
| 55 | #define BP_APBX_CTRL1_CH6_AHB_ERROR_IRQ 22 |
| 56 | #define BM_APBX_CTRL1_CH6_AHB_ERROR_IRQ 0x00400000 |
| 57 | #define BP_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 15 |
| 58 | #define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00008000 |
| 59 | #define BP_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 14 |
| 60 | #define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00004000 |
| 61 | |
| 62 | HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x40, 0x70) |
| 63 | HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x50, 0x70) |
| 64 | #define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 |
| 65 | #define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF |
| 66 | #define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v) |
| 67 | HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x60, 0x70) |
| 68 | #define BP_APBX_CHn_CMD_XFER_COUNT 16 |
| 69 | #define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 |
| 70 | #define BF_APBX_CHn_CMD_XFER_COUNT(v) \ |
| 71 | (((v) << BP_APBX_CHn_CMD_XFER_COUNT) & BM_APBX_CHn_CMD_XFER_COUNT) |
| 72 | #define BP_APBX_CHn_CMD_CMDWORDS 12 |
| 73 | #define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 |
| 74 | #define BF_APBX_CHn_CMD_CMDWORDS(v) \ |
| 75 | (((v) << BP_APBX_CHn_CMD_CMDWORDS) & BM_APBX_CHn_CMD_CMDWORDS) |
| 76 | #define BP_APBX_CHn_CMD_WAIT4ENDCMD 7 |
| 77 | #define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 |
| 78 | #define BP_APBX_CHn_CMD_SEMAPHORE 6 |
| 79 | #define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 |
| 80 | #define BP_APBX_CHn_CMD_IRQONCMPLT 3 |
| 81 | #define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 |
| 82 | #define BP_APBX_CHn_CMD_CHAIN 2 |
| 83 | #define BM_APBX_CHn_CMD_CHAIN 0x00000004 |
| 84 | #define BM_APBX_CHn_CMD_DMA_READ 0x00000003 |
| 85 | #define BP_APBX_CHn_CMD_DMA_READ 0 |
| 86 | #define BF_APBX_CHn_CMD_DMA_READ(v) \ |
| 87 | (((v) << BP_APBX_CHn_CMD_DMA_READ) & BM_APBX_CHn_CMD_DMA_READ) |
| 88 | #define BP_APBX_CHn_CMD_COMMAND 0 |
| 89 | #define BM_APBX_CHn_CMD_COMMAND 0x00000003 |
| 90 | #define BF_APBX_CHn_CMD_COMMAND(v) \ |
| 91 | (((v) << BP_APBX_CHn_CMD_COMMAND) & BM_APBX_CHn_CMD_COMMAND) |
| 92 | #define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 |
| 93 | #define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 |
| 94 | #define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 |
| 95 | |
| 96 | HW_REGISTER_RO_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x70, 0x70) |
| 97 | HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x80, 0x70) |
| 98 | #define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 |
| 99 | #define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF |
| 100 | #define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \ |
| 101 | (((v) << BP_APBX_CHn_SEMA_INCREMENT_SEMA) & \ |
| 102 | BM_APBX_CHn_SEMA_INCREMENT_SEMA) |
| 103 | #define BP_APBX_CHn_SEMA_PHORE 16 |
| 104 | #define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 |
| 105 | HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x90, 0x70) |
| 106 | HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0xA0, 0x70) |
| 107 | HW_REGISTER_RO(HW_APBX_VERSION, REGS_APBX_BASE, 0x3F0) |
| 108 | |
| 109 | #endif /* _INCLUDE_ASM_ARCH_REGS_APBX_H */ |