| Mike Frysinger | fec84d2 | 2010-10-22 04:41:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * bfin_ppi.h - interface to Blackfin PPIs |
| 3 | * |
| 4 | * Copyright 2005-2010 Analog Devices Inc. |
| 5 | * |
| 6 | * Licensed under the GPL-2 or later. |
| 7 | */ |
| 8 | |
| 9 | #ifndef __ASM_BFIN_PPI_H__ |
| 10 | #define __ASM_BFIN_PPI_H__ |
| 11 | |
| 12 | #include <linux/types.h> |
| 13 | |
| 14 | /* |
| 15 | * All Blackfin system MMRs are padded to 32bits even if the register |
| 16 | * itself is only 16bits. So use a helper macro to streamline this. |
| 17 | */ |
| 18 | #define __BFP(m) u16 m; u16 __pad_##m |
| 19 | |
| 20 | /* |
| 21 | * bfin ppi registers layout |
| 22 | */ |
| 23 | struct bfin_ppi_regs { |
| 24 | __BFP(control); |
| 25 | __BFP(status); |
| 26 | __BFP(count); |
| 27 | __BFP(delay); |
| 28 | __BFP(frame); |
| 29 | }; |
| 30 | |
| 31 | /* |
| 32 | * bfin eppi registers layout |
| 33 | */ |
| 34 | struct bfin_eppi_regs { |
| 35 | __BFP(status); |
| 36 | __BFP(hcount); |
| 37 | __BFP(hdelay); |
| 38 | __BFP(vcount); |
| 39 | __BFP(vdelay); |
| 40 | __BFP(frame); |
| 41 | __BFP(line); |
| 42 | __BFP(clkdiv); |
| 43 | u32 control; |
| 44 | u32 fs1w_hbl; |
| 45 | u32 fs1p_avpl; |
| 46 | u32 fs2w_lvb; |
| 47 | u32 fs2p_lavf; |
| 48 | u32 clip; |
| 49 | }; |
| 50 | |
| Mike Frysinger | ff7cbc4 | 2010-10-24 18:13:31 +0000 | [diff] [blame] | 51 | #undef __BFP |
| 52 | |
| Mike Frysinger | fec84d2 | 2010-10-22 04:41:13 +0000 | [diff] [blame] | 53 | #endif |